The published atlas now shows only actual die micrographs and accepts local GDSII files. The original photonics research notes below are historical references; interpreted circuit maps and source presentation slides are excluded from the viewer.

Original PIC and EIC catalog

For the cross-industry collection, open the searchable catalog and coverage report. This document preserves the original photonics subset.

This catalog separates physical chips from modules, optical engines, and demonstrations. It covers explicit examples in the core articles and selected OFC 2026 photographs. The wider source archive contains additional newsletter material and OCR leads.

Open the interactive chip maps for source-image annotations and functional views of the 16 cataloged dies. Actual mask files, when available, can be opened separately in the local GDSII viewer.

A PIC is a photonic integrated circuit. An EIC is an electronic integrated circuit. A TIA converts photodetector current into a voltage. Unknown die models, dimensions, rates and power remain empty in the structured catalog.

Chips and dies

Assembly or example	Chips described	Evidence and limits
Intel 100G CWDM4	Transmit PIC, modulator driver/EIC, receiver detector die, TIA	Teardown, Intel section. Roles are the author's identifications. Exact die vendors and part numbers are unspecified.
Infinera 1.6T example	Silicon photonics PIC, die marking reported as TR6A_301	Article, map, October audit. Bonded InP sections provide gain and amplification.
Cisco / Finisar 400G DR4	Possible modulator PIC	Teardown. The source alternates between EML and CW-laser interpretations. The die identity is unresolved.
Intel OCI	Separate EIC and PIC	CPO tutorial. The quoted energy applies to the engine example.
NVIDIA clock-forwarded DWDM	7 nm FinFET EIC on 65 nm SOI PIC	ISSCC example, OFC photo IMG_4147. Research demonstration.
Marvell COUPE MRM CPO	TSMC N3P EIC and 65 nm PIC	OFC photo IMG_4055. Hybrid bonding, PIC TSVs and vertical grating couplers are slide-reported.
Marvell Photonic Fabric	TSMC 4/5nm EIC and EAM photonic interposer or bridge	OFC photo IMG_4056. The slide does not select one electrical node or give the photonic node.
LightXcelerate LightX-1	VCSEL/PD PIC over PHY, driver and TIA EIC	OFC photo IMG_4178. Footprint and channel count apply to the engine statement.

Modules and optical engines

Example	Reported configuration	Scope to preserve
Intel 100G CWDM4	Four optical channels at 25 Gb/s	Module example
Innolight 200G QSFP56 FR4	1310 nm module label	Opening teardown caption; nearby EML photographs have an uncertain module association.
Cisco / Finisar 400G DR4	Eight electrical lanes to four optical PAM4 lanes	Teardown; separate host lane and optical lane rates.
Innolight 400G OSFP DR4+	Photographs and module identification	Teardown; detailed chip descriptions are pending in the source.
Innolight 800G OSFP PSM8	Photographs and module identification	Teardown; detailed chip descriptions are pending in the source.
Infinera 1.6T DWDM	Two wavelengths, two polarizations, DP-64QAM; author gives 96 GBd	Article; nominal and gross rates require reconciliation before a sweep.
Intel OCI	8 fiber pairs, 8 wavelengths, 32 Gb/s per lane; roughly 2 Tb/s each direction	Tutorial; quoted 5 pJ/bit has no per-die allocation.
Ranovus / MediaTek engine	6.4 Tb/s; 8 fibers × 8 wavelengths × 100 Gb/s	Tutorial; quoted 4 pJ/bit includes the laser.
NVIDIA DWDM demonstration	8 data wavelengths × 32 Gb/s = 256 Gb/s per fiber; one additional clock wavelength	Visually checked slide; original energy and sensitivity footnotes need review before use.
Marvell COUPE MRM CPO	16 wavelengths per fiber; 1 Tb/s per fiber	Visually checked slide; direction convention and link conditions unspecified.
Marvell Photonic Fabric	Generation labels show 16 Tb/s and 64 Tb/s	Visually checked slide; these are architecture claims, with shipping status and rate accounting unspecified.
LightXcelerate LightX-1	57 Tx and 57 Rx; 1.5 × 1.6 mm footprint	Visually checked slide; lane rate and power unspecified.

Infinera map interpretation

The captured registry contains 489 entries and 329 connections. It marks 132 entries as L and 357 as I. L means a die label or an identification in the article. I means an inferred layout interpretation. Entries include pads, routes, markers and test structures, so 489 is not a die count or active-device count. Category totals are saved in the map summary.

The October audit places fast modulation before amplitude and thermal phase tuning. It leaves the WLL light direction unresolved: injection locking and an off-chip wavelength-locker path both fit the layout. Use the audited registry when interpreting the earlier article. Source audit.

Inputs still needed for architecture sweeps

Record the direction convention, payload versus gross rate, FEC overhead, reach, BER target, optical loss budget, operating temperature and energy boundary for every comparison. Keep measured results, vendor slide claims and layout inferences distinct. A module rate or engine energy figure does not establish a PIC or EIC rate or power by itself.