{
  "schema_version": "1.0",
  "snapshot_date": "2026-10-22",
  "title": "Outside Five Sigma industry chip catalog",
  "scope": "Curated explicit chip and assembly examples from the three core articles, Infinera map and audit, and selected visually checked OFC2026 photographs. Weekly newsletters and unreviewed OCR remain searchable in the source archive; this is not an exhaustive vendor product database.",
  "null_convention": "Null means the cited source does not establish this value. No process, power or rate is inferred from the assembly vendor or nominal module name.",
  "evidence_convention": {
    "author_identification": "Identity or role stated by Outside Five Sigma; not independently validated",
    "author_inference": "Author gives a tentative interpretation",
    "photographed_slide_visually_checked": "The text was checked in the source photo; the vendor claim itself is not independently measured",
    "cited_report": "Outside Five Sigma attributes the value to another publication or announcement",
    "source_registry": "Data from the interactive map, preserving its own confidence convention"
  },
  "assemblies": [
    {
      "id": "intel100",
      "record_type": "pluggable_module",
      "vendor_or_presenter": "Intel",
      "name": "100G CWDM4 transceiver around 2017",
      "architecture": "Four-wavelength silicon photonics with integrated III-V source coupons and MZM modulation",
      "reported_metrics": [
        {
          "name": "nominal_capacity",
          "value": 100,
          "unit": "Gb/s",
          "scope": "module"
        },
        {
          "name": "optical_channels",
          "value": 4,
          "unit": "channels",
          "scope": "module"
        },
        {
          "name": "lane_rate",
          "value": 25,
          "unit": "Gb/s",
          "scope": "optical channel"
        }
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/teardown/100G-200G-400G-800G/#intel",
          "section": "Intel",
          "basis": "author_identification",
          "supports": "Intel 100G CWDM4 silicon-photonics teardown"
        },
        {
          "url": "https://outside5sigma.com/tutorial/silicon-photonics-and-co-packaged-optics/#how-to-send-bits-with-light",
          "section": "How to send bits with light",
          "basis": "author_report",
          "supports": "Four 25 Gb/s channels; MZM discussed under Modulation"
        }
      ],
      "limits": [
        "No exact module part number, driver model, TIA model, or process node is given in the article text.",
        "The tutorial says the module is roughly 18 mm long. Its mechanical boundary is unclear, so this is not used as a die dimension."
      ]
    },
    {
      "id": "innolight200",
      "record_type": "pluggable_module",
      "vendor_or_presenter": "Innolight",
      "name": "200G QSFP56 FR4 1310 nm",
      "architecture": "FR4; detailed laser/PIC assignment unresolved in the mixed Intel section",
      "reported_metrics": [
        {
          "name": "nominal_capacity",
          "value": 200,
          "unit": "Gb/s",
          "scope": "module"
        },
        {
          "name": "nominal_wavelength",
          "value": 1310,
          "unit": "nm",
          "scope": "module label"
        }
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/teardown/100G-200G-400G-800G/#intel",
          "section": "Intel opening caption",
          "basis": "author_identification",
          "supports": "Red module identified as Innolight 200G QSFP56 FR4 1310 nm"
        }
      ],
      "limits": [
        "The nearby EML, detector and TIA photographs are not unambiguously assigned to this module in the prose."
      ]
    },
    {
      "id": "cisco400",
      "record_type": "pluggable_module",
      "vendor_or_presenter": "Cisco / Finisar",
      "name": "400G DR4",
      "architecture": "8 electrical lanes to 4 optical PAM4 lanes; optical source and modulator identification remains uncertain",
      "reported_metrics": [
        {
          "name": "nominal_capacity",
          "value": 400,
          "unit": "Gb/s",
          "scope": "module"
        },
        {
          "name": "electrical_lane_count",
          "value": 8,
          "unit": "lanes",
          "scope": "module"
        },
        {
          "name": "electrical_lane_rate_class",
          "value": 50,
          "unit": "Gb/s",
          "scope": "electrical lane"
        },
        {
          "name": "optical_lane_count",
          "value": 4,
          "unit": "lanes",
          "scope": "module"
        },
        {
          "name": "optical_lane_rate_class",
          "value": 100,
          "unit": "Gb/s",
          "scope": "optical lane"
        }
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/teardown/100G-200G-400G-800G/#cisco-finisar",
          "section": "Cisco Finisar",
          "basis": "author_report",
          "supports": "8x50G to 4x100G PAM4 conversion"
        }
      ],
      "limits": [
        "The author first calls two visible sources EMLs, then describes CW lasers feeding a modulator chip. Preserve both readings.",
        "The 26.5626 GBd / 53.125 Gb/s host-lane statement is internally approximate and is not a symbol-rate specification for the optical lanes."
      ]
    },
    {
      "id": "innolight400",
      "record_type": "pluggable_module",
      "vendor_or_presenter": "Innolight",
      "name": "400G OSFP DR4+",
      "architecture": "DR4+",
      "reported_metrics": [
        {
          "name": "nominal_capacity",
          "value": 400,
          "unit": "Gb/s",
          "scope": "module"
        }
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/teardown/100G-200G-400G-800G/#innolight",
          "section": "Innolight",
          "basis": "author_identification",
          "supports": "Module identification beside teardown photographs"
        }
      ],
      "limits": [
        "The article supplies photographs and says further descriptions are to be added. Chip identities and electrical details are not specified."
      ]
    },
    {
      "id": "innolight800",
      "record_type": "pluggable_module",
      "vendor_or_presenter": "Innolight",
      "name": "800G OSFP PSM8",
      "architecture": "PSM8",
      "reported_metrics": [
        {
          "name": "nominal_capacity",
          "value": 800,
          "unit": "Gb/s",
          "scope": "module"
        }
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/teardown/100G-200G-400G-800G/#innolight",
          "section": "Innolight",
          "basis": "author_identification",
          "supports": "Module identification beside teardown photographs"
        }
      ],
      "limits": [
        "The article supplies photographs and says further descriptions are to be added. Chip identities and electrical details are not specified."
      ]
    },
    {
      "id": "infinera1600",
      "record_type": "transceiver_example",
      "vendor_or_presenter": "Infinera",
      "name": "1.6T DWDM DP-64QAM transceiver PIC example",
      "architecture": "Two-wavelength dual-polarization coherent transceiver",
      "reported_metrics": [
        {
          "name": "nominal_capacity",
          "value": 1.6,
          "unit": "Tb/s",
          "scope": "module as reported by author"
        },
        {
          "name": "wavelength_count",
          "value": 2,
          "unit": "wavelengths",
          "scope": "reported optical architecture"
        },
        {
          "name": "polarization_count",
          "value": 2,
          "unit": "polarizations",
          "scope": "per wavelength"
        },
        {
          "name": "reported_symbol_rate",
          "value": 96,
          "unit": "GBd",
          "scope": "author statement; channel basis not further specified"
        }
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/tutorial/infinera-DP-64QAM/",
          "section": "Opening paragraph",
          "basis": "author_report",
          "supports": "1.6T, two wavelengths, DP-64QAM and 96 GBd"
        }
      ],
      "limits": [
        "These numbers do not form a complete net-versus-gross rate budget. DSP, FEC and operating modes must be checked before calculating payload capacity.",
        "The PIC image is a die-level observation. The article does not identify the associated DSP."
      ]
    },
    {
      "id": "inteloci",
      "record_type": "optical_io_chiplet",
      "vendor_or_presenter": "Intel",
      "name": "Optical Compute Interconnect chiplet example",
      "architecture": "WDM optical I/O with distinct electrical and photonic ICs",
      "reported_metrics": [
        {
          "name": "fiber_pairs",
          "value": 8,
          "unit": "pairs",
          "scope": "engine"
        },
        {
          "name": "wavelengths_per_fiber",
          "value": 8,
          "unit": "wavelengths",
          "scope": "engine"
        },
        {
          "name": "per_lane_rate",
          "value": 32,
          "unit": "Gb/s",
          "scope": "per direction"
        },
        {
          "name": "reported_one_way_capacity",
          "value": 2,
          "unit": "Tb/s",
          "scope": "engine",
          "condition_or_limit": "Rounded in the tutorial"
        },
        {
          "name": "reported_bidirectional_capacity",
          "value": 4,
          "unit": "Tb/s",
          "scope": "engine",
          "condition_or_limit": "Rounded aggregate, both directions"
        },
        {
          "name": "reported_energy",
          "value": 5,
          "unit": "pJ/bit",
          "scope": "Intel-reported figure cited by tutorial",
          "condition_or_limit": "System boundary is not established in the tutorial"
        }
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/tutorial/silicon-photonics-and-co-packaged-optics/#how-to-read-the-cpo-bandwidth-numbers",
          "section": "How to read the CPO bandwidth numbers",
          "basis": "cited_report",
          "supports": "Intel OCI lane count, rate, direction convention and energy figure; figure identifies EIC and PIC"
        }
      ],
      "limits": [
        "No per-die process node, size or power is assigned here."
      ]
    },
    {
      "id": "ranovus6400",
      "record_type": "optical_engine",
      "vendor_or_presenter": "Ranovus / MediaTek",
      "name": "6.4 Tb/s optical engine example",
      "architecture": "8 fibers × 8 wavelengths × 100 Gb/s; internal- and external-laser options",
      "reported_metrics": [
        {
          "name": "reported_capacity",
          "value": 6.4,
          "unit": "Tb/s",
          "scope": "one optical engine; direction convention not restated"
        },
        {
          "name": "fiber_count",
          "value": 8,
          "unit": "fibers",
          "scope": "configuration in tutorial"
        },
        {
          "name": "wavelength_count_per_fiber",
          "value": 8,
          "unit": "wavelengths",
          "scope": "configuration in tutorial"
        },
        {
          "name": "lane_rate",
          "value": 100,
          "unit": "Gb/s",
          "scope": "optical channel"
        },
        {
          "name": "reported_energy",
          "value": 4,
          "unit": "pJ/bit",
          "scope": "engine, including laser as quoted by tutorial"
        }
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/tutorial/silicon-photonics-and-co-packaged-optics/#how-to-read-the-cpo-bandwidth-numbers",
          "section": "How to read the CPO bandwidth numbers",
          "basis": "cited_report",
          "supports": "Ranovus/MediaTek OFC2024 configuration and energy quote"
        }
      ],
      "limits": [
        "The 51.2 Tb/s number in the tutorial is eight engines around an ASIC, not one PIC.",
        "The tutorial does not assign a part number, process node or per-chip energy to these engines."
      ]
    },
    {
      "id": "nvidia256",
      "record_type": "research_demonstrator",
      "vendor_or_presenter": "NVIDIA",
      "name": "Clock-forwarded DWDM test chip at ISSCC 2026",
      "architecture": "3D-stacked 7 nm EIC on 65 nm SOI PIC; eight data wavelengths plus forwarded clock",
      "reported_metrics": [
        {
          "name": "per_data_wavelength_rate",
          "value": 32,
          "unit": "Gb/s",
          "scope": "data channel"
        },
        {
          "name": "data_capacity_per_fiber",
          "value": 256,
          "unit": "Gb/s",
          "scope": "8 data wavelengths"
        },
        {
          "name": "wavelength_count_including_clock",
          "value": 9,
          "unit": "wavelengths",
          "scope": "8 data plus clock"
        }
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/tutorial/silicon-photonics-and-co-packaged-optics/#energy",
          "section": "Energy",
          "basis": "cited_paper_title",
          "supports": "ISSCC2026 paper title gives 7nm EIC, 65nm PIC and 32Gb/s per wavelength /256Gb/s per fiber"
        },
        {
          "url": "https://outside5sigma.com/blog/OFC2026/#img_4147jpg",
          "section": "IMG_4147.JPG",
          "basis": "photographed_slide_visually_checked",
          "supports": "NVIDIA slide identifies process, 8x32 Gb/s data, and 9 total wavelengths",
          "image_url": "https://outside5sigma.com/assets/images/2026/OFC2026/IMG_4147.JPG"
        }
      ],
      "limits": [
        "A test chip is not evidence of a shipping transceiver product.",
        "The slide contains energy, sensitivity, BER and density data with multiple footnotes. Retain the original photo and verify those conditions before a numerical sweep."
      ]
    },
    {
      "id": "marvellmrm",
      "record_type": "optical_engine_architecture",
      "vendor_or_presenter": "Marvell",
      "name": "COUPE MRM CPO",
      "architecture": "TSMC COUPE; hybrid bonded EIC and MRM PIC; TSVs through PIC; C4 to organic substrate",
      "reported_metrics": [
        {
          "name": "wavelengths_per_fiber",
          "value": 16,
          "unit": "wavelengths",
          "scope": "DWDM configuration"
        },
        {
          "name": "reported_capacity_per_fiber",
          "value": 1,
          "unit": "Tb/s",
          "scope": "slide-reported"
        }
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/blog/OFC2026/#img_4055jpg",
          "section": "IMG_4055.JPG",
          "basis": "photographed_slide_visually_checked",
          "supports": "Marvell slide specifies N3P EIC, 65nm PIC, 16 wavelengths/fiber and 1Tb/s/fiber",
          "image_url": "https://outside5sigma.com/assets/images/2026/OFC2026/IMG_4055.JPG"
        }
      ],
      "limits": [
        "Production status, per-lane rate, direction convention, BER and energy are not established by this slide."
      ]
    },
    {
      "id": "marvellfabric",
      "record_type": "optical_io_chiplet_architecture",
      "vendor_or_presenter": "Marvell",
      "name": "Photonic Fabric chiplet for CPO",
      "architecture": "Photonic interposer or bridge with EAM, PD, SiPh waveguides, grating couplers and EIC protocol/control blocks",
      "reported_metrics": [
        {
          "name": "generation_1_reported_capacity",
          "value": 16,
          "unit": "Tb/s",
          "scope": "slide-reported chiplet architecture; direction convention unspecified"
        },
        {
          "name": "generation_2_reported_capacity",
          "value": 64,
          "unit": "Tb/s",
          "scope": "slide-reported chiplet architecture; direction convention unspecified"
        }
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/blog/OFC2026/#img_4056jpg",
          "section": "IMG_4056.JPG",
          "basis": "photographed_slide_visually_checked",
          "supports": "Marvell slide identifies TSMC4/5nm EIC and EAM-based photonic interposer/bridge",
          "image_url": "https://outside5sigma.com/assets/images/2026/OFC2026/IMG_4056.JPG"
        }
      ],
      "limits": [
        "Generation labels are not shipping-status claims. Rates lack direction, overhead and link-condition detail."
      ]
    },
    {
      "id": "lightx1",
      "record_type": "optical_io_engine_architecture",
      "vendor_or_presenter": "LightXcelerate",
      "name": "LightX-1 micro-VCSEL optical I/O engine",
      "architecture": "VCSEL/PD PIC on EIC with PHY, driver and TIA; TSV on EIC",
      "reported_metrics": [
        {
          "name": "transmit_channel_count",
          "value": 57,
          "unit": "channels",
          "scope": "slide-reported engine"
        },
        {
          "name": "receive_channel_count",
          "value": 57,
          "unit": "channels",
          "scope": "slide-reported engine"
        },
        {
          "name": "reported_footprint",
          "value": [
            1.5,
            1.6
          ],
          "unit": "mm",
          "scope": "engine footprint; not assigned to a single die"
        }
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/blog/OFC2026/#img_4178jpg",
          "section": "IMG_4178.JPG",
          "basis": "photographed_slide_visually_checked",
          "supports": "LightXcelerate slide reports channel count, footprint and PIC-on-EIC stack",
          "image_url": "https://outside5sigma.com/assets/images/2026/OFC2026/IMG_4178.JPG"
        }
      ],
      "limits": [
        "No lane rate, aggregate capacity, process node or power is stated on this slide."
      ]
    }
  ],
  "chips": [
    {
      "id": "intel100-txpic",
      "record_type": "chip_or_die",
      "vendor": "Intel",
      "device_or_model": "100G CWDM4 transmit PIC; part number unspecified",
      "type": "PIC",
      "assembly_id": "intel100",
      "architecture": "WDM with integrated InP source coupons, MZM modulation and echelle mux",
      "process": {
        "platform": "InP on SOI, as described by author",
        "node_nm": null
      },
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [
        "Four optical channels and echelle-grating mux",
        "Six visible InP coupons are described as four lasers plus two monitor photodiodes, based on an Intel acquaintance"
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/teardown/100G-200G-400G-800G/#intel",
          "section": "Intel, final 100G teardown paragraph",
          "basis": "author_identification",
          "supports": "PIC, driver/EIC, receiver detector die and TIA are identified in the Intel 100G example"
        },
        {
          "url": "https://outside5sigma.com/tutorial/silicon-photonics-and-co-packaged-optics/#modulation",
          "section": "Modulation",
          "basis": "author_identification",
          "supports": "MZM modulator type"
        }
      ],
      "limits": [
        "Coupon functions are second-hand identification, not independently validated."
      ]
    },
    {
      "id": "intel100-driver",
      "record_type": "chip_or_die",
      "vendor": null,
      "device_or_model": "Driver/EIC on Intel modulator section; part number unspecified",
      "type": "EIC / modulator driver",
      "assembly_id": "intel100",
      "architecture": "Electronic drive for MZM transmitters",
      "process": null,
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [],
      "evidence": [
        {
          "url": "https://outside5sigma.com/teardown/100G-200G-400G-800G/#intel",
          "section": "Intel, final 100G teardown paragraph",
          "basis": "author_identification",
          "supports": "PIC, driver/EIC, receiver detector die and TIA are identified in the Intel 100G example"
        }
      ],
      "limits": [
        "Assembly vendor Intel does not establish the EIC die vendor."
      ]
    },
    {
      "id": "intel100-rxpd",
      "record_type": "chip_or_die",
      "vendor": null,
      "device_or_model": "Photodetector receiver die in Intel 100G module; part number unspecified",
      "type": "photodetector die",
      "assembly_id": "intel100",
      "architecture": "Direct detection",
      "process": null,
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [
        "Photodetectors beneath fiber/planar-lightwave-circuit block with wirebonds to TIA"
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/teardown/100G-200G-400G-800G/#intel",
          "section": "Intel, final 100G teardown paragraph",
          "basis": "author_identification",
          "supports": "PIC, driver/EIC, receiver detector die and TIA are identified in the Intel 100G example"
        }
      ],
      "limits": [
        "The prose does not specify whether this should be treated as a separate waveguide PIC or only a detector array."
      ]
    },
    {
      "id": "intel100-tia",
      "record_type": "chip_or_die",
      "vendor": null,
      "device_or_model": "TIA in Intel 100G receiver; part number unspecified",
      "type": "EIC / TIA",
      "assembly_id": "intel100",
      "architecture": "Direct-detection receiver front end",
      "process": null,
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [],
      "evidence": [
        {
          "url": "https://outside5sigma.com/teardown/100G-200G-400G-800G/#intel",
          "section": "Intel, final 100G teardown paragraph",
          "basis": "author_identification",
          "supports": "PIC, driver/EIC, receiver detector die and TIA are identified in the Intel 100G example"
        }
      ],
      "limits": [
        "Vendor, bandwidth, gain, process and die power are unspecified."
      ]
    },
    {
      "id": "infinera-tr6a301",
      "record_type": "chip_or_die",
      "vendor": "Infinera",
      "device_or_model": "TR6A_301 silicon photonics PIC",
      "type": "PIC",
      "assembly_id": "infinera1600",
      "architecture": "Coherent DWDM transmitter plus receiver; two transmit lasers and two LO lasers",
      "process": {
        "platform": "Silicon photonics with bonded InP gain/SOA sections",
        "node_nm": null
      },
      "die_marking": {
        "text": "TR6A_301",
        "basis": "author_reading_in_audit"
      },
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [
        "Fast traveling-wave modulation comes before amplitude/thermal phase tuners in the audited topology",
        "WLL branch has one facet port, Y junction and two InP sections; direction is unresolved"
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/tutorial/infinera-DP-64QAM/",
          "section": "Lasers, Modulation, Monitoring, Receivers",
          "basis": "author_identification_and_inference",
          "supports": "PIC functional interpretation"
        },
        {
          "url": "https://outside5sigma.com/docs/RFD-009-infinera-pic-interactive-map/",
          "section": "Findings vs the post; 2026-10-21 DevLog",
          "basis": "author_audit",
          "supports": "TR6A_301 marking and updated topology; 489 components and 329 connections"
        },
        {
          "url": "https://outside5sigma.com/infinera-pic-map/data.js",
          "section": "PIC_DATA registry",
          "basis": "source_registry",
          "supports": "Per-component labels, descriptions, confidence and geometric traces"
        }
      ],
      "limits": [
        "WLL injection-locking and off-chip wavelength-locker interpretations both remain possible.",
        "On-chip polarization rotation is not established; do not assume a complete polarization combiner topology from this image.",
        "The confidence tag L includes identifications in the article, while I denotes inferred mapping. These are source confidence tags, not independent validation."
      ]
    },
    {
      "id": "cisco400-modulator-candidate",
      "record_type": "chip_or_die",
      "vendor": null,
      "device_or_model": "Possible modulator chip in Cisco/Finisar 400G DR4",
      "type": "PIC / modulator candidate",
      "assembly_id": "cisco400",
      "architecture": "PAM4 optical transmit path; source reading unresolved",
      "process": null,
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [],
      "evidence": [
        {
          "url": "https://outside5sigma.com/teardown/100G-200G-400G-800G/#cisco-finisar",
          "section": "Cisco Finisar",
          "basis": "author_inference",
          "supports": "CW sources feeding a modulator chip is the author's later interpretation"
        }
      ],
      "limits": [
        "The same section first calls the sources EMLs. Exact architecture and die identity remain unresolved."
      ]
    },
    {
      "id": "inteloci-pic",
      "record_type": "chip_or_die",
      "vendor": "Intel",
      "device_or_model": "OCI PIC; part number unspecified",
      "type": "PIC",
      "assembly_id": "inteloci",
      "architecture": "WDM optical compute interconnect",
      "process": null,
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [],
      "evidence": [
        {
          "url": "https://outside5sigma.com/tutorial/silicon-photonics-and-co-packaged-optics/#how-to-read-the-cpo-bandwidth-numbers",
          "section": "How to read the CPO bandwidth numbers, Intel OCI EIC/PIC figure",
          "basis": "cited_report_and_figure",
          "supports": "OCI figure separates electrical and photonic ICs"
        }
      ],
      "limits": [
        "Quoted 5pJ/bit is an engine-level figure; no allocation to this die is given."
      ]
    },
    {
      "id": "inteloci-eic",
      "record_type": "chip_or_die",
      "vendor": "Intel",
      "device_or_model": "OCI EIC; part number unspecified",
      "type": "EIC",
      "assembly_id": "inteloci",
      "architecture": "WDM optical compute interconnect",
      "process": null,
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [],
      "evidence": [
        {
          "url": "https://outside5sigma.com/tutorial/silicon-photonics-and-co-packaged-optics/#how-to-read-the-cpo-bandwidth-numbers",
          "section": "How to read the CPO bandwidth numbers, Intel OCI EIC/PIC figure",
          "basis": "cited_report_and_figure",
          "supports": "OCI figure separates electrical and photonic ICs"
        }
      ],
      "limits": [
        "Quoted 5pJ/bit is an engine-level figure; no allocation to this die is given."
      ]
    },
    {
      "id": "nvidia256-pic",
      "record_type": "chip_or_die",
      "vendor": "NVIDIA",
      "device_or_model": "ISSCC2026 clock-forwarded DWDM PIC",
      "type": "PIC",
      "assembly_id": "nvidia256",
      "architecture": "3D-stacked clock-forwarded DWDM",
      "process": {
        "platform": "SOI silicon photonics",
        "node_nm": 65
      },
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [],
      "evidence": [
        {
          "url": "https://outside5sigma.com/tutorial/silicon-photonics-and-co-packaged-optics/#energy",
          "section": "Energy, cited ISSCC2026 title",
          "basis": "cited_paper_title",
          "supports": "7nm EIC /65nm PIC"
        },
        {
          "url": "https://outside5sigma.com/blog/OFC2026/#img_4147jpg",
          "section": "IMG_4147.JPG",
          "basis": "photographed_slide_visually_checked",
          "supports": "Process table confirms 7nm FinFET EIC and 65nm SOI SiPh PIC",
          "image_url": "https://outside5sigma.com/assets/images/2026/OFC2026/IMG_4147.JPG"
        }
      ],
      "limits": [
        "Research test chip. Per-die dimensions and per-die power are not separately assigned."
      ]
    },
    {
      "id": "nvidia256-eic",
      "record_type": "chip_or_die",
      "vendor": "NVIDIA",
      "device_or_model": "ISSCC2026 clock-forwarded DWDM EIC",
      "type": "EIC",
      "assembly_id": "nvidia256",
      "architecture": "3D-stacked clock-forwarded DWDM",
      "process": {
        "platform": "FinFET",
        "node_nm": 7
      },
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [],
      "evidence": [
        {
          "url": "https://outside5sigma.com/tutorial/silicon-photonics-and-co-packaged-optics/#energy",
          "section": "Energy, cited ISSCC2026 title",
          "basis": "cited_paper_title",
          "supports": "7nm EIC /65nm PIC"
        },
        {
          "url": "https://outside5sigma.com/blog/OFC2026/#img_4147jpg",
          "section": "IMG_4147.JPG",
          "basis": "photographed_slide_visually_checked",
          "supports": "Process table confirms 7nm FinFET EIC and 65nm SOI SiPh PIC",
          "image_url": "https://outside5sigma.com/assets/images/2026/OFC2026/IMG_4147.JPG"
        }
      ],
      "limits": [
        "Research test chip. Per-die dimensions and per-die power are not separately assigned."
      ]
    },
    {
      "id": "marvellmrm-pic",
      "record_type": "chip_or_die",
      "vendor": "Marvell",
      "device_or_model": "COUPE MRM CPO PIC; part number unspecified",
      "type": "PIC",
      "assembly_id": "marvellmrm",
      "architecture": "MRM DWDM, hybrid bonded EIC-PIC",
      "process": {
        "platform": "TSMC COUPE silicon photonics",
        "node_nm": 65
      },
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [
        "PIC TSVs and vertical grating couplers"
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/blog/OFC2026/#img_4055jpg",
          "section": "IMG_4055.JPG",
          "basis": "photographed_slide_visually_checked",
          "supports": "N3P EIC and 65nm PIC plus hybrid bonding diagram",
          "image_url": "https://outside5sigma.com/assets/images/2026/OFC2026/IMG_4055.JPG"
        }
      ],
      "limits": []
    },
    {
      "id": "marvellmrm-eic",
      "record_type": "chip_or_die",
      "vendor": "Marvell",
      "device_or_model": "COUPE MRM CPO EIC; part number unspecified",
      "type": "EIC",
      "assembly_id": "marvellmrm",
      "architecture": "MRM DWDM, hybrid bonded EIC-PIC",
      "process": {
        "platform": "TSMC N3P",
        "node_nm": null
      },
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [
        "Driver and TIA blocks shown in EIC"
      ],
      "evidence": [
        {
          "url": "https://outside5sigma.com/blog/OFC2026/#img_4055jpg",
          "section": "IMG_4055.JPG",
          "basis": "photographed_slide_visually_checked",
          "supports": "N3P EIC and 65nm PIC plus hybrid bonding diagram",
          "image_url": "https://outside5sigma.com/assets/images/2026/OFC2026/IMG_4055.JPG"
        }
      ],
      "limits": [
        "N3P is retained as the exact process name; no numerical node is inferred."
      ]
    },
    {
      "id": "marvellfabric-pic",
      "record_type": "chip_or_die",
      "vendor": "Marvell",
      "device_or_model": "Photonic Fabric photonic interposer or bridge",
      "type": "PIC",
      "assembly_id": "marvellfabric",
      "architecture": "EAM, photodiodes, SiPh waveguides and grating couplers",
      "process": null,
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [],
      "evidence": [
        {
          "url": "https://outside5sigma.com/blog/OFC2026/#img_4056jpg",
          "section": "IMG_4056.JPG",
          "basis": "photographed_slide_visually_checked",
          "supports": "PIC/interposer/bridge functions listed in slide",
          "image_url": "https://outside5sigma.com/assets/images/2026/OFC2026/IMG_4056.JPG"
        }
      ],
      "limits": [
        "Photonic process node is not stated."
      ]
    },
    {
      "id": "marvellfabric-eic",
      "record_type": "chip_or_die",
      "vendor": "Marvell",
      "device_or_model": "Photonic Fabric electrical IC",
      "type": "EIC",
      "assembly_id": "marvellfabric",
      "architecture": "AMS driver/TIA/SerDes, link management, FEC and protocol adaptation",
      "process": {
        "platform": "TSMC 4/5nm, as shown on slide",
        "node_nm": null
      },
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [],
      "evidence": [
        {
          "url": "https://outside5sigma.com/blog/OFC2026/#img_4056jpg",
          "section": "IMG_4056.JPG",
          "basis": "photographed_slide_visually_checked",
          "supports": "Electrical IC labeled TSMC4/5nm; functions shown in table",
          "image_url": "https://outside5sigma.com/assets/images/2026/OFC2026/IMG_4056.JPG"
        }
      ],
      "limits": [
        "The slide presents 4/5nm alternatives. It does not establish one exact node or implementation for each generation."
      ]
    },
    {
      "id": "lightx1-pic",
      "record_type": "chip_or_die",
      "vendor": "LightXcelerate",
      "device_or_model": "LightX-1 VCSEL/PD photonic die",
      "type": "PIC, as labeled by vendor",
      "assembly_id": "lightx1",
      "architecture": "Micro-VCSEL and photodetector array on EIC",
      "process": null,
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [],
      "evidence": [
        {
          "url": "https://outside5sigma.com/blog/OFC2026/#img_4178jpg",
          "section": "IMG_4178.JPG",
          "basis": "photographed_slide_visually_checked",
          "supports": "PIC(VCSEL/PD) sits on EIC(PHY+DRV+TIA)",
          "image_url": "https://outside5sigma.com/assets/images/2026/OFC2026/IMG_4178.JPG"
        }
      ],
      "limits": [
        "Vendor calls the VCSEL/PD layer a PIC. Its material platform, process and individual die dimensions are not given."
      ]
    },
    {
      "id": "lightx1-eic",
      "record_type": "chip_or_die",
      "vendor": "LightXcelerate",
      "device_or_model": "LightX-1 electrical IC",
      "type": "EIC / PHY / driver / TIA",
      "assembly_id": "lightx1",
      "architecture": "PHY plus VCSEL driver and TIA; EIC TSVs",
      "process": null,
      "die_marking": null,
      "die_dimensions_mm": null,
      "die_rate_Gb_s": null,
      "die_power_W": null,
      "features": [],
      "evidence": [
        {
          "url": "https://outside5sigma.com/blog/OFC2026/#img_4178jpg",
          "section": "IMG_4178.JPG",
          "basis": "photographed_slide_visually_checked",
          "supports": "EIC functions and TSV explicitly listed",
          "image_url": "https://outside5sigma.com/assets/images/2026/OFC2026/IMG_4178.JPG"
        }
      ],
      "limits": [
        "The 1.5x1.6mm footprint applies to the engine statement, not necessarily the EIC die."
      ]
    }
  ],
  "infinera_map_summary": {
    "source_url": "https://outside5sigma.com/infinera-pic-map/data.js",
    "component_count": 489,
    "connection_count": 329,
    "source_confidence_counts": {
      "L": 132,
      "I": 357
    },
    "confidence_key": {
      "L": "Labeled on die or identified in article, per source convention",
      "I": "Inferred from layout, per source convention"
    },
    "category_counts": {
      "dbr": {
        "name": "DBR mirror",
        "count": 8
      },
      "gain": {
        "name": "Laser gain section",
        "count": 4
      },
      "laser_phase": {
        "name": "Laser phase section",
        "count": 4
      },
      "wg": {
        "name": "Waveguide route",
        "count": 143
      },
      "pad": {
        "name": "Pads",
        "count": 102
      },
      "splitter": {
        "name": "Splitter",
        "count": 28
      },
      "term": {
        "name": "Terminator",
        "count": 27
      },
      "mod_fast": {
        "name": "Fast modulator",
        "count": 16
      },
      "amp_tune": {
        "name": "Amplitude tuner",
        "count": 16
      },
      "phase_tune": {
        "name": "Phase tuner",
        "count": 16
      },
      "combiner": {
        "name": "Combiner",
        "count": 13
      },
      "mpd": {
        "name": "Monitor PD",
        "count": 14
      },
      "soa": {
        "name": "SOA",
        "count": 6
      },
      "port": {
        "name": "Facet port / SSC",
        "count": 9
      },
      "hybrid": {
        "name": "90-degree hybrid",
        "count": 12
      },
      "rx_pd": {
        "name": "Receiver PD",
        "count": 24
      },
      "test": {
        "name": "Test structure",
        "count": 29
      },
      "mark": {
        "name": "Marks and ID",
        "count": 16
      },
      "trench": {
        "name": "Isolation trench",
        "count": 2
      }
    },
    "warning": "Registry entries include routes, pads, test structures, markers and compound devices. The count is not a count of physical dies, independent active devices, or fabricated transistor equivalents."
  }
}