← Chip Atlas / Index

Published visual scope: actual die micrographs and local GDSII inspection only. The historical circuit, pad-drawing and extracted-layout research described below is retained in the private repository and is excluded from the public viewer.

Sources and attribution

Outside Five Sigma

The catalog and approximate image regions were prepared from material by Wentao / Outside Five Sigma. Sources include:

Every image record and annotation retains a source URL. The shared viewer loads original source images when a local cache is absent. It embeds or links the original Infinera map; that map is not copied into the repository.

Outside Five Sigma's terms state ownership of original content, describe personal non-commercial use, and require attribution for sharing or citation. This repository grants no additional rights to that material. Photos may have separate credits on their original pages.

Infinera micrograph

The original map credits siliconpr0n / evilmonkeyz for the die micrograph. See the original micrograph collection. Its 489-entry registry and interpretations belong to the source map's authors. They are not new industry mask data produced here.

Vendor slides and names

Conference photos show slides and diagrams attributed to Intel, NVIDIA, Marvell, LightXcelerate, and other presenters. Those slides, names, and marks retain their original ownership. The atlas records source claims without establishing endorsement or independent product validation.

Local source archive

The optional local collection contains papers, images, extracted text, and datasets with different licenses. It is ignored by Git. Download availability does not imply redistribution permission; check the original source and its license before reuse.

The MIT license covers this repository's original software, photonics annotations, summaries, and documentation. It does not cover third-party material referenced or downloaded by that software, or the image-derived annotations explicitly offered under a source image’s license below.

ZeptoBars source photographs

The expanded collection links photographs and device identifications published by ZeptoBars. Its reuse statement specifies CC BY 3.0. Each image retains the publisher credit, a publication link, and a license link. Images load from the original s.zeptobars.com host; they are not copied into this repository. Selected photographs have approximate interactive regions under CC BY 3.0. Their notes distinguish the author’s functional identifications from visible patterns, pads, and markings whose roles remain unspecified. The photographs are unchanged; no mask geometry is supplied.

The import checked public English index pages 1–47 and conservatively excluded anonymous, counterfeit, non-chip, and ambiguous identity records. Published device identities, historical specimens, and present vendor products can differ. Review corrections are retained in the source data.

Vendor product references and exact parts

Vendor product pages and documentation support named product identities and source-listed orderable codes. Summaries are original. Vendor marks and documentation retain their owners' rights. Linking a product reference does not imply endorsement, shipping availability, full family coverage, or access to proprietary masks. Package and lifecycle fields remain null unless verified for that exact part.

Processor model numbers are a separate code class from complete ordering codes. Intel ARK and AMD product/export tables support the collected model identifiers. AMD OPN tables, Lattice change-notice appendices, and manufacturer ordering tables support the separately labeled ordering codes. No suffix combinations are generated.

The Everspin MR0A08B, MR1A16A, MR2A16A, MR4A16B and MR25H128A, Atmel AT28HC256, ISSI IS42S16400J, and STMicroelectronics M27C1001 and M27C322 maps use facts from dated manufacturer datasheets. Each map retains the document link, reviewed pages and PDF hash. The graphs are original drawings; manufacturer artwork is not redistributed. Published control gates are distinguished from functional blocks described only by operation text. Numbered package contacts do not establish die-pad locations, repeated supply contacts do not establish internal metal connections, and logical storage capacity does not establish a cell-transistor count. The maps retain revision differences and unresolved source labels, including the ISSI diagram’s unexplained “256K (x16)” label. Cell, sense, programming, protection and power transistor circuits remain gaps wherever the sources omit them.

Wikimedia Commons die photographs and annotations

The reviewed image manifest links named commercial and historical semiconductor specimens published on Wikimedia Commons. Each image record preserves its individual creator, original file page, license name and URL, and dimensions. The importer accepts supported Creative Commons or public-domain licenses only. Images remain on Wikimedia’s host; the repository contains metadata and source links.

The original image is unchanged. On selected annotated images, this project adds approximate interactive hit regions that follow the source’s existing labels. Two sensor photographs also have approximate array regions, explicitly marked as inferences from visible structure and the source description. Those hit-region annotations use the corresponding source license:

Source authorship and licenses remain unchanged. Each map links its exact source-file and license pages. Some source overlays cover only part of a die. The record states that scope; unlabeled or damaged areas are not reconstructed. Close-up and opened-package photographs are identified in their image captions.

Additional reviewed map overlays retain the license on each source image, including CC BY 4.0 for John McMaster’s RP2040 photograph and Andrew Zonenberg’s Tesla MH7404 and TI CD4049 photographs, CC BY-SA 3.0 for the Intel 8086 photograph, and CC BY 3.0 for the ZeptoBars-sourced die photographs. Functional identifications from Raspberry Pi, John McMaster, Ken Shirriff, and ZeptoBars link to the relevant published analysis. Approximate locations transferred between corresponding source views remain source-author identifications; they are not independent circuit reconstructions. Physical-feature maps assign no function to an unlabeled region.

Published circuit labels and functional block identifications remain the source authors’ interpretations. The two sensor-array placements are this project’s qualified inferences, with their uncertainty stated per region. None supplies independently reconstructed device functions or fabrication geometry. The image record states the display changes and license; the source file page records specimen context and any earlier transformations. The ADC84KG-12 record includes a credited intact-package reference, an opened hybrid assembly, and individual component-die views; those internal dies are not separate commercial part numbers.

The Fairchild µA747 and µA714 circuit graphs transcribe component labels and terminal connections from the manufacturer’s 1973 and 1979 databooks. Each record retains its reviewed page and document hash. The graphs are original drawings; scanned manufacturer artwork is not redistributed. Unresolved source connections and package-contact assignments remain stated gaps. The µA714 trim-area image association follows ZeptoBars’ description of the aggregate area and does not identify individual resistor designators or fuse states.

The National DM5408/DM7476, TI 7413/54LS28, and Fairchild 7404/54LS20/74LS244 maps retain their dated manufacturer databook references, pages and document hashes. Original graph drawings preserve unnumbered source symbols without inventing printed component designators or unlabelled resistor values. The DM7476 output-stage trace is explicitly partial; its remaining published master/slave transistor network is an unresolved tracing task. Integral Schottky transistor clamps remain source-symbol features rather than additional separately drawn diode counts. Connections to existing Commons contact regions follow the source author’s external-contact labels only; they do not establish internal transistor positions or a mask-revision match. Existing photograph and annotation licenses remain applicable. Scanned manufacturer artwork is not redistributed.

Project 54/74 circuit drawings and traces

Five separate source circuit views reproduce single-page schematic drawings published by Robert.Baruch / Project 54/74 on Wikimedia Commons: the Motorola 74HC02 specimen dated 8302, Signetics 54S00 dated 8716, Signetics 74S11 dated 8150, TI 7413 dated 7348 and National 7476 dated B077. Each file is CC BY-SA 4.0. The registry in 05_Chip_Visualizations/data/source_schematic_views.json retains the exact source-file page, original PDF URL, document hash, author and license. The local SVGs in data/source_schematics/ convert the original PDF pages to vector images, retaining the diagram content and white page background. Approximate interactive hit regions locate source symbols in those drawings; they are not physical die coordinates. The SVG conversions and their annotation metadata use the same CC BY-SA 4.0 license.

The three graph transcriptions in functional_source_traces_goal_batch20.json also use CC BY-SA 4.0, with source designators, terminal connections, limits and changes recorded per model. Gate prefixes separate repeated source labels. The 74HC02 source explicitly marks its circuit ×4; the 74S11 sheet draws only gate 2. Unprinted resistor values remain unknown. Source schematic symbol links and matching labels on the author's die photographs use separate fields. The 1973 TI 7413 source tracing has a multi-emitter input stage and is retained separately from the later manufacturer reference using input diodes. The National 7476 drawing is also a separate source view; it is not merged into the older partial manufacturer-reference graph.

The software remains MIT licensed. The licensed source drawings, source traces and their annotations are excluded from that software license. Each source view retains its author credit, source-page link, license link and conversion notice.

Published pad coordinates

The fourteen pad plots are original SVG drawings of numerical facts published in Texas Instruments datasheets. Their source tables, page locators, document hashes, coordinate strings, and datum qualifications are retained in 05_Chip_Visualizations/data/pad_map_sources.json and pad_map_sources_expansion.json. The drawings and their hit regions are MIT licensed; vendor artwork is not copied. Each plot links its original datasheet. Point markers are symbolic. Rectangle plots use the manufacturer’s published minimum and maximum pad coordinates. Unknown physical origins and die-edge offsets remain unknown. No internal circuit geometry is supplied.

Published pad-figure references

Six additional original SVG drawings follow labelled pad arrangements in the 1980 RCA COS/MOS Integrated Circuits databook. Their reviewed pages, document hash, printed pad labels and manually estimated source-figure reference positions are retained in 05_Chip_Visualizations/data/figure_pad_sources.json. These are separate dated manufacturer reference views. Their positions are approximate readings of an illustration, not tabulated coordinates, measured pad centres, physical pad footprints or a geometric match to another photographed specimen. The drawings and hit regions are MIT licensed. The CD40163BH reference uses the book’s explicit statement that CD40160BH, CD40161BH, CD40162BH and CD40163BH have identical dimensions and pad layouts; its underlying photograph is captioned CD40160BH. Source artwork and internal circuit geometry are omitted; RCA's documentation retains its original rights.

Two further original drawings use pad-label facts from the Sierra Components reference library: its AMD AM27C64 sheet dated March 3, 2000, and Motorola MC14046B sheet dated May 22, 2000. The registry records Sierra as the supplier publisher and AMD or Motorola as the manufacturer named on the sheet. Each view retains its source link, original-file hash and approximate figure positions. The Motorola source is a legacy Word file; a separate PDF conversion hash documents the reading copy and is not represented as an original supplier PDF. These reference views do not establish the revision or geometry of the independently photographed dies. Supplier artwork, logos, scanned photographs and internal geometry are not redistributed. The new marker drawings and hit regions are MIT licensed; the original documents retain their owners’ rights and reference-only notice.

Published interactive simulations

Selected records link the author-published Visual 6502, Z80, and 2A03 remixes. These remain external applications. Their simulator software, extracted netlists, and chip geometry can have different licenses; the project’s file-specific notices apply. Except for the separately documented local Visual6502 6502 revD browser below, these external applications’ map geometry is not copied and no reuse license is implied. A generic simulated model need not match the revision of a photographed specimen.

Richi’s Lab photographs and image regions

The LH0042-family photographs linked from Richi’s Lab’s original analysis are credited to Richi’s Lab and retain the source site’s CC BY-NC 4.0 license. The photographs are unchanged. The two approximate die-boundary hit regions added to the assembly photograph are image-derived annotations and use the same license. These images and annotations are excluded from the project’s MIT license.

MC68000 published circuit extraction

The dedicated MC68000 connection browser transcribes component identities, terminal incidence, net identities and schematic coordinates from Olivier Galibert’s published extraction. Quietust traced the metal layer, and John McMaster supplied die photographs. The source viewer identifies MC68000P8, mask 3A72E. The reviewed schem.txt SHA-256 is 860ffebeaa0848c77677d435795297b95afff343d4350f3656144d19f576e5f8.

The conversion follows the documented reader format in dietools. No original program, scanned artwork or source die photograph is bundled with this browser. The interface and drawing code are original to this project. Source transistor classes, terminal order, component labels and net indices remain intact. Repeated supply drawing symbols are excluded from the component inventory; equally named nets are not merged.

The 35,033 imported component records comprise 34,869 transistor records, 102 capacitors and 62 pads. These are counts of the reviewed extraction, not an independently verified physical device inventory for all MC68000 masks. Coordinates describe the author’s schematic arrangement and are not die locations or GDS. The separately licensed Commons photograph remains unchanged and is not matched to this specimen. The main atlas includes a small exact CLK-pad neighborhood and links to the complete imported connection browser.

Visual6502 Motorola 6800 tracing

The 6800 transistor/layer browser derives its geometry from Ijor’s Visual6502 6800 data. The traced geometry and geometry-derived dataset retain CC BY-NC-SA 3.0, attributed to Ijor and www.visual6502.org. These data are not covered by the project’s MIT license. Node-name metadata retains the original MIT notice naming Ijor, Segher Boessenkool and Ed Spittles. The browser links its attribution and notices and the geometry license.

The importer parses pinned source arrays without executing their JavaScript. It retains every transistor ID, gate/c1/c2 connection, original node ID, alias, channel bounding box, polygon layer and weak flag. All 3,995 transistor records survive, including the 72 weak records skipped by the source simulator. The browser draws 9,805 source polygons across 2,012 distinct source node IDs; it does not run the source simulator. Changes include data conversion, new search/connection controls, new rendering colors and retained weak records.

Coordinates remain in original tracing units. Displayed boxes are source channel bounds, not exact transistor shapes. The separate Commons photograph is not registered to this source, and no coordinates are transferred to it. No calibrated micron dimensions, fabrication source/drain roles, device models or GDS are supplied. Source file hashes and the pinned revision are retained in the data and the import tool. The existing MC68000 browser continues to use schematic coordinates; these two coordinate systems remain distinct.

Visual6502 MOS6502 revD tracing

The local 6502 transistor/layer browser derives from the pinned Visual6502 revD data. Geometry and this geometry-derived dataset retain CC BY-NC-SA 3.0, attributed to Greg James, original material www.visual6502.org; the source geometry notice also names Brian and Barry Silverman. These data are excluded from the project MIT license. Alias metadata retains the original MIT notice naming Brian Silverman, Barry Silverman, Ed Spittles and Segher Boessenkool. See the full notices.

All 3,510 transistor records, 1,704 nonnegative source node IDs,832 assigned aliases and 8,233 polygons survive the conversion. The two names p5/Pout5 with value -1 are preserved separately as unassigned placeholders, not a physical net or status-bit storage node. The source has no weak/strong flag, so the imported flags are null. Every gate/c1/c2 connection, channel box, source geometry descriptor, polygon layer and pullup marker is retained without invented electrical models or parameters. The importer does not execute source JavaScript.

Original tracing coordinates are displayed with canvas y-down; viewport dimensions are editorial source-coordinate extents, not physical chip dimensions. The independent catalog photograph is not registered to this revD source. Boxes are channel bounds, not recovered mask outlines or GDS. Existing source-explained control/overflow nodes remain distinct from the newly added literal RESET and data-bus neighborhoods. The shared viewer continues to support MC68000 schematic coordinates and Motorola6800 traced geometry independently.

LM5050-1 manufacturer reference

The LM5050-1 mixed circuit map transcribes terminal connectivity and functional facts from Texas Instruments SNVS629F, December 2019, especially page12. It includes the drawn two NPNs, discharge NMOS and three diodes; current/voltage sources and undisclosed comparator, pump and bias interiors remain reference boundaries. The external power MOSFET and body diode are excluded. The source14V clamp label and12V operating prose, and illustrative offsets versus electrical thresholds, remain separately documented. The original conceptual drawing and labels are MIT licensed; vendor artwork is not copied. No physical layout correspondence or complete transistor inventory is claimed.

XC6206 and BQ29312A manufacturer references

The XC6206 conceptual reference follows Torex ETR03005-009, notably pages2–3. The archived reading copy is a manufacturer PDF retained by a distributor; its retrieval URL and hash are recorded separately. Three diode-symbol occurrences include a parasitic path, which is not claimed as an additional fabricated component. The unvalued divider, gate-control boundaries and package contact differences are preserved. No die-image positions are inferred.

The BQ29312A reference follows Texas Instruments SLUS629A, August2005. Its dashed internal-device boundary excludes cells, pass FETs, thermistor, shunt and filter parts. Register/protection and analog cell-translation facts are transcribed into original conceptual diagrams; undisclosed transistor interiors remain functional boundaries. Source differences involving watchdog units, XALERT pullup values, middle-cell polarity labels and the SLEEP bias symbol remain explicit. The graph drawings and annotations are MIT licensed; original vendor artwork is not redistributed, and no mask-specific netlist or physical placement is claimed.

National 54HC00 and Signetics 74LS09 references

The National 54HC00 reference combines the device logic/contact diagram in the 1983 National 74HC Databook, physical page 121, with the same manufacturer’s buffered-NAND family example in AN313 Figure1(b), physical page 40. The source explicitly distinguishes the four-MOS unbuffered core from an eight-MOS buffered example. Four-channel instantiation yields 32 reference MOS symbols; this is not a physical device count for the photographed mask. Input protection remains a boundary because the exact diode network is unshown.

The Signetics 74LS09 map uses the 1987 Signetics TTL Data Manual, physical pages 81–83, specification dated December 4, 1985. It transcribes four open-collector AND channel functions and source contact ordering. A high truth result means a released collector requiring external loading; no internal pullup or unsupported transistor circuit is added. Vendor artwork and scan images are not redistributed. The new conceptual diagrams are MIT licensed; existing die photographs retain their separate credited licenses.

Signetics NE558 and AD9361 references

The Signetics NE558 equivalent is checked against the 1982 Signetics Analog Data Manual, physical pages 179–180, printed 5-12–5-13. The representative circuit has twelve bipolar symbols, seven unvalued resistors, three diodes, six ideal-source boundaries and a reset-switch equivalent. It is expanded once; shared bias/reference structures are not multiplied into a physical quad-die inventory. The source lists F/N reference packages and does not verify the catalog D suffix or photographed mask. Unnumbered device labels are editorial.

The AD9361 functional map follows Analog Devices Rev. G, with the archived manufacturer-PDF reading copy and hash recorded in its evidence. It distinguishes two receive and two transmit chains from their selectable port alternatives, preserves separate RX/TX synthesizers and BB PLL, and records TDD-only TX-monitor reuse and mode-dependent CMOS/LVDS interfaces. Complex converter and control boundaries are not transistor or arithmetic-cell inventories. Selected BGA contacts are package functions, not die coordinates. The new conceptual graph transcriptions are MIT licensed; vendor scan/artwork is not redistributed, and the independently credited photographs retain their own licenses.

AD4130-8 and AD7124-8 sensor-converter references

The new references follow Analog Devices AD4130-8 Rev. A and AD7124-8 Rev. F. Archived manufacturer-PDF reading copies, hashes, page counts and canonical links are recorded per model. Each source draws protection pairs at AIN0, AIN1, AIN14 and AIN15; those eight diode occurrences are individually labeled. Middle-input ellipses remain unexpanded protection boundaries. These references do not claim a literal physical diode inventory or die registration.

The maps retain model-specific PGA/buffer bypass, single-core channel sequencing, register setups, current/bias routing, power clocks and package contacts. AD4130-8 FIFO storage headers, trailing DATA register status, FIFO-ready and redirectable interrupt signals remain distinct. Its dedicated INT is WLCSP-only. AD7124-8 does not inherit that FIFO, package pin, or obsolete gain-one capacitor figures removed in Rev. F. External sensors, filters, clocks, loads and decouplers are excluded from internal component counts. The original conceptual transcriptions are MIT licensed; manufacturer scan artwork is not redistributed.

RT8059 power-stage and AL8805 operating references

The RT8059 map follows Richtek DS8059-06, May 2016, pages 1–4. It transcribes two power MOSFET symbols, three unvalued resistor symbols and one unvalued compensation capacitor. Current, zero, PWM, driver, reference and UVLO interiors remain functional boundaries. The unusual UVLO connections in the source block drawing are preserved and flagged, rather than replaced by an assumed comparator circuit. MOSFET on-resistance specifications are not sense-resistor values. External application passives are excluded.

The AL8805 map follows Diodes Incorporated DS43562 Rev. 5-3, March 2021, pages 2–3, 9 and 11. This edition supplies an operating description rather than an internal transistor schematic. The current-sense, hysteretic comparator, dimming and MOSFET boundaries are explicitly prose-derived. Effective CTRL resistance is not expanded into an invented resistor; the external freewheel diode and optional soft-start capacitor remain external. Source hashes and page counts accompany each reference. These original conceptual graph transcriptions are MIT licensed; manufacturer scan/artwork is not redistributed. No physical die coordinates or mask inventories are claimed.

RT9078 and MP1584 pass, discharge, bootstrap and latch references

The RT9078 reference follows Richtek RT9078_DS-22, August 2026, especially pages 3–4 and 13–14. Two drawn MOSFETs and three unvalued internal resistors are individually labeled. Local-output and SNS feedback routes remain mutually exclusive family options, with SNS/NC and package differences recorded. The error-amplifier signs and the thermal-shutdown output-current condition follow the source. External application divider/capacitors and undisclosed bulk connections are excluded.

The MP1584 reference follows the manufacturer Rev. 1.0 PDF, August 8, 2011, pages 2 and 7–9. It transcribes the drawn power NMOS, bootstrap PMOS and series diode, two cross-coupled NAND gates, inverter and functional control boundaries. The ideal 5 V bootstrap reference is relative to SW. The prose-mentioned current-sense MOSFET has undisclosed terminals and is not added as a fabricated literal transistor. External bootstrap/catch components, inductor, compensation and frequency-setting passives remain outside the chip inventory. Ambiguous driver-UVLO wording and the source not-recommended-for-new-designs watermark are retained. Source hashes/page counts accompany both original conceptual graph transcriptions, which are MIT licensed. Manufacturer scan/artwork is not redistributed, and no physical die registration is claimed.

ADN2814 and ADN2815 CDR and LVDS references

The CDR maps follow Analog Devices ADN2814 Rev. C and ADN2815 Rev. C. The ADN2814 archived manufacturer reading copy is hashed. The primary ADN2815 Rev. C was inspected through the web PDF reader; direct download timed out, so no local Rev. C checksum is claimed. Its separately identified Rev. 0 reading aid is not treated as byte-identical or as authority for revised contacts 1/32, which are VCC in Rev. C.

Each map labels the two internal 50 Ω input terminations and 3 kΩ bias feed. The simplified LVDS equivalent is instantiated logically for clock and data: four source MOS switches, internal 100 Ω shunt and two ideal 5 mA current-source equivalents per interface. This does not establish physical replication. MOS polarity, source/drain assignment and gate wiring are unmarked, so neutral channel terminals and explicit functional gate-control boundaries are used. The external 100 Ω load, TIA/photodiode, capacitors and other board passives are excluded. Coarse frequency acquisition, phase/delay loops, optional reference, retiming, logical registers and squelch retain distinct paths. ADN2814 slice/LOS functions are not imported into ADN2815. These original conceptual transcriptions are MIT licensed; manufacturer scan/artwork is not redistributed, and physical die geometry remains unresolved.

ADN2891 and ADN2892 optical limiting-amplifier references

The maps follow the primary ADN2891 Rev. B, March 2017 and ADN2892 Rev. C, March 2017, especially Figure 1 and pages 3–6 and 10–11. Current PDFs were inspected through the web reader; no current-revision checksum is asserted. Separately hashed older reading aids include ADN2891 Rev. A and a preliminary ADN2892; they are not treated as current specification or package authority.

Each model includes two 50 Ω input terminations, its distinct 3 kΩ/3.5 kΩ bias feed, two separate 50 Ω output pull-up terminations, and documented 100 kΩ control pulls. Control-pull supply domains remain unresolved where the source does not identify microscopic AVCC/DRVCC or ground routing. ADN2891 CAZ contacts remain separate from ADN2892 BW_SEL/LOS_INV functions. Limiting/offset/filter, photodiode bias, RSSI current output, LOS and squelch internals are functional boundaries. Conflicting open-collector/open-drain terminology for LOS is preserved without inventing an NPN or NMOS. External photodiode/TIA, CAZ and coupling capacitors, threshold/load/pull-up resistors and optional LOS-to-SQUELCH wiring are excluded from internal counts. These original conceptual transcriptions are MIT licensed; manufacturer scan/artwork is not redistributed and no physical die registration is claimed.

FXAS21002C and FXOS8700CQ motion-sensor references

The gyro map follows Freescale/NXP FXAS21002 Rev. 2.1, May 2015 and FXAS21002CER Rev. 0.1. It labels six variable-capacitance pickup equivalents and the charge-pump capacitor glyph from Figure 1, plus the explicitly described conditional INT2/PWR_CTRL pull-up. These are source equivalents, not a MEMS finger inventory. Electrode boundaries, common ties and physical mass count remain unresolved. One drawn conversion path handles rate and temperature; FIFO capacity is 32 XYZ rate samples. The SPI MISO erratum, dated clean-code statement and external workaround scope are recorded without asserting a photographed specimen is fixed.

The six-axis map follows NXP FXOS8700CQ Rev. 8, April 2017 and FXOS8700CQER Rev. 1. Six named sensing functions and shared analog/conversion boundaries feed distinct 14-bit acceleration and 16-bit magnetic results. The FIFO is acceleration-only. Event, calibration, reset/interface and power functions remain conceptual. The SPI software-reset and I²C/magnetic-AFE coupling errata are explicit. AN4073, cited by the datasheet, supports configured pre/post-trigger FIFO behavior as family guidance. Source hashes and actual PDF page counts are recorded; early FXOS headers still say 113 although the file has 116 pages. External support capacitors, bus/IRQ pull-ups and erratum workaround buffers are excluded. These original transcriptions are MIT licensed; manufacturer artwork is not redistributed and no physical die coordinates or hidden transistor inventories are claimed.

MAX699 supervision and unnumbered topography references

The map follows Maxim Integrated MAX698/MAX699 Rev. 5, September 2014, available from Analog Devices, using the separately hashed archived reading copy. Pages 1–5 document the package interfaces, voltage/timing limits, POR/watchdog circuit, chip topography and WDI contact correction. One unvalued POR capacitor is individually labeled; the reference, current generator, comparator, watchdog, gate and timer remain source equivalents with undisclosed transistor internals. Blank timing-table cells are retained as unknown. SO-only outputs are not assigned PDIP contacts.

The separate original pad-reference drawing transcribes nine unnumbered function labels and rounded die dimensions. Marker positions are manual figure estimates, not measured centers, calibrated coordinates, package-contact assignments or registration to the existing credited die photograph. Unlabeled pads and manufacturer internal artwork are omitted. These original conceptual transcriptions are MIT licensed. A separate limited review of Sylvania's May 1966 SUHL source does not establish SG7460 correspondence and is retained as pending evidence, not a completed map.

TDA7496L stereo audio and feedback reference

The map follows STMicroelectronics TDA7496L, September 2003, pages 1–5, available through the manufacturer PDF and a hashed archived reading copy. The reading copy visibly says September 2003; search-result dates are not used as edition evidence. Both stereo paths label the 30 kΩ input resistors, four unvalued feedback resistors and 60 kΩ MUTE pull-down. The shared slanted-hatch reference symbol is associated with SVR and kept separate from package ground. Monitor buffers remain separate from the power outputs.

Volume stages, Class AB amplifiers, monitor buffers and mute/standby/protection remain functional blocks; no transistor inventory is inferred. External input/output/SVR capacitors, bypass capacitors, volume potentiometer, 300 kΩ and 10 kΩ application resistors and switches are excluded from internal counts. The source supply-range discrepancy, package NC contact and SVR sequencing are retained. This original conceptual graph is MIT licensed; manufacturer artwork is not redistributed and no physical die coordinates are claimed.

DAC8568 channels and independent circuit equivalents

The map follows Texas Instruments SBAS430F, April 2018, especially pages 3–4, 31–35 and 44–47. Eight 16-bit functional channel paths retain A/B gain-one versus C/D gain-two and zero/midscale-reset distinctions. Four independent source views transcribe Figure 122's basic two-NPN bandgap and four unvalued resistors; Figure 120's C/D normal-operation 62 kΩ feed and two 50 kΩ feedback resistors; Figure 121's four visible equal-R segments, RDIVIDER and six visible tap switches; and Figure 124's power-state switches and functional resistor network. Their symbol counts are not summed as a physical die inventory.

The bandgap amplifier output drives its upper bus; that bus is not relabeled AVDD. Q2 relative area N and the broken middle of the illustrative string remain unresolved. Effective 1 kΩ/100 kΩ power-down choices do not establish a pair of literal resistors. Serial-field and application-example inconsistencies are recorded; the map follows the 32-bit falling-edge interface and command-table field boundaries. External capacitors, loads, microcontrollers and OPA703 bipolar-output circuits are excluded. This original conceptual graph is MIT licensed. Manufacturer artwork is not redistributed; physical layout, transistor parameters and mask correspondence remain unverified.

DS1000Z and NXP 74AHC00 logic and timing references

The DS1000Z map follows the Dallas Semiconductor DS1000 111799 datasheet, pages 1–5, and the manufacturer Design Considerations for All-Silicon Delay Lines, Figures 4 and 12. The five serial delay sections and input/tap inversions are separate from the DS1000-labelled negative-ramp equivalent and the generic two-edge comparator/latch illustration. One unvalued capacitor glyph does not establish five physical capacitors. Switch control, comparator signs, trim state and transistor internals remain unresolved. The 2002 manufacturer article distinguishes old DS1000 from newer compensated VCDL designs; differing compensation descriptions are retained without importing the newer circuit.

The 74AHC00 map follows NXP 74AHC_AHCT00_3 Rev. 03, January 8, 2008, from a hashed archived manufacturer reading copy. The PDF's NXP copyright/revision is used despite the archive's Philips page title; separate Philips 1999 and Nexperia 2025 editions are not substituted. Four NAND functions, contacts and documented Schmitt input actions are transcribed. No textbook MOS network, separate Schmitt core count or ESD diode inventory is inferred. These original conceptual graphs are MIT licensed. Manufacturer artwork is not redistributed and physical die coordinates are unverified.

A4915 motor-driver input/output references

The map follows Allegro A4915-DS Rev. 9, October 16, 2024, especially pages 1, 3–9 and 14. Three-phase commutation, PWM, bootstrap, low-side drive, fault and reset paths remain functional. Seven independent I/O structure views transcribe ten neutral MOS symbols, twenty Zener glyphs, eight ordinary/body diode glyphs and five printed resistors. Logic/Hall/phase alternatives are representative views, not pins shorted together or a physical die inventory.

Unmarked MOS polarity, source/drain, bulk and gate-control continuations remain unresolved. Four drawn body diodes are separate glyphs. The CP1-to-CP2 diode and unvalued Zener retain their drawn same-direction orientation. Bootstrap and VREG/LSS/GND clamp paths remain distinct. The source's 30 kHz prose versus 20 kHz typical electrical-table discrepancy is recorded, as are the active-high released FAULT output, invalid-Hall exception, package differences and conditional sleep pull behavior. Six external bridge MOSFETs, Hall sensors, motor, capacitors, pullups, timing/gate/shunt resistors and TVS are excluded from internal counts. This original conceptual graph is MIT licensed; manufacturer artwork is not redistributed and physical placement is unverified.

TPS51120 standby and channel-one circuit reference

The map follows TI SLUS670C, January 2015, especially Figure 27 on page 16 and the pin/function descriptions on pages 3–4 and 17–21. Two standby LDO pass stages are PMOS by explicit prose; four other MOS glyphs retain neutral channel terminals. Ten unvalued resistors and three documented diodes are labeled. MOS on-resistances of 1.3 Ω and 10 Ω are not extra resistor components.

Seven selector poles, four signed PWM/OCP input paths, PGND current references, five NAND gates, two AND gates and the two distinct one-shot output wires follow the source. On-time sensing uses LL, not VIN; there is no dedicated oscillator. Channel two is kept as a functional boundary except its independently documented bootstrap PN diode. Figure/prose switchover thresholds, reference drive capability and an unusual VIN-diode connection are preserved as source discrepancies. VREG5/V5FILT, signal GND and power returns are not silently shorted. External power MOSFETs, inductors, capacitors and sense/compensation/filter components are excluded. This original conceptual graph is MIT licensed; manufacturer artwork is not redistributed and no physical die placement or recovered mask inventory is asserted.

ADN2841, ADN2847 and ADN2870 laser-control references

The maps follow manufacturer ADN2841 Rev. C, February 2017, ADN2847 Rev. B, March 2012 and ADN2870 Rev. D, September 2020. Separately hashed manufacturer reading copies identify the inspected editions; no byte identity with the primary host is asserted. The original conceptual graphs transcribe source NPN glyphs, input terminations, bias feeds, alarm pulls and documented control/monitor paths. They retain model-specific clock, dual-MPD, supervisory-tone, setpoint, phase-control and alarm differences. External laser/photodiodes, loop capacitors, current-set/load/matching resistors, ADC/DACs and optical filters are excluded from internal counts.

The ADN2847 archived reading copy, page 6 Table 4, supplies the independent numeric pad plot. All 48 source rows are retained, but only 46 are plotted: pads 4 ERSET and 8 IMPDMON both print (−996,+506) µm, so both positions are withheld without a sign correction or preferred row. The center origin is explicit; axis orientation relative to the photograph/package is unresolved. The Figure 5 dimension labels and Figure 6 rotation note are recorded without an inferred die outline or registration. No manufacturer artwork is copied. These original drawings and graph transcriptions are MIT licensed; they are not recovered mask netlists or physical transistor inventories.

ONET4251PA and ONET4201LD optical frontend references

The original conceptual graphs follow Texas Instruments ONET4251PA SLLS663A, November 2005, Figure 1 and pages 2–5/9, and ONET4201LD SLLS677A, September 2009, Figures 1–2 and pages 2–7. The hashed PDFs include later package addenda; those addenda do not change the stated edition of the main circuit diagrams. The receiver map retains three gain stages, input-buffer detector taps, offset feedback, four 50 Ω terminations and the drawn internal capacitor. The laser-driver map retains two NPN output symbols with distinct emitter-current branches, active termination, APC/current-monitor paths, and the drawn comparators, gates, selectors, counter and latch.

Unlabelled current-return rails, capacitor value, gate/reference/current-source transistor circuits, latch priority and physical die placements remain unresolved. Functional fault logic is not claimed as a literal transistor inventory. External lasers, photodiodes, coupling/filter capacitors, set/monitor resistors, matching components and optional squelch links are excluded from on-chip counts. No manufacturer artwork is copied; the original graph transcriptions are MIT licensed.

LM5146 voltage-mode controller references

The original graph follows Texas Instruments LM5146 SNVSBV0A, June 2021, the overall functional diagram on page 16 and the separate Figure 8-10 OCP explanation on page 24, qualified by the pin table and operating descriptions on pages 4–5 and 18–26. Five neutral MOS symbols, three diode symbols and one unvalued internal ramp capacitor are transcribed across those two views. Repeated amplifiers, comparators, drivers and latches are reference representations, not duplicate physical device inventories. Source Q versus Q-bar outputs, signed thresholds, active sampling, bootstrap interlock and distinct ground scopes are retained.

The auxiliary-supply Figure 8-2 contact callouts conflict with the pin table; the reference uses VIN contact 20 and VCC contact 14. Feedforward notation and nominal versus typical threshold wording are retained with their source scope. Unlabelled current-source rails, ground partition, MOS polarity/bulk, hidden fault overrides and physical placements remain unresolved. External Q1/Q2, power-stage parts, dividers, current-set/monitor resistors and capacitors are excluded from internal counts. No manufacturer artwork is copied; the original graph transcription is MIT licensed.

MP2307 and MP2451 buck-converter references

The original graphs follow MPS MP2307 Rev. 1.9, May 28, 2008, manufacturer reading copy, Figure 1 on page 6 and low-side body-diode description on page 7, and MP2451 Rev. 1.4, June 8, 2026, manufacturer-hosted reading copy, Figure 1 on page 7 and operating descriptions on pages 8–9. Hashes identify the inspected documents; no byte identity across hosts or photographed-mask correspondence is asserted.

MP2307 retains two power N-channel MOSFETs, three protection MOS glyphs, the PNP COMP clamp, sense-resistor equivalent, bootstrap/EN protection and documented intrinsic low-side body diode. The intrinsic diode belongs to M2 and is not an independent physical diode-cell count. MP2451 retains a single high-side switch, prose-documented VIN-to-BST PMOS, internal series compensation R/C and EN zener. Its current-sense MOSFET is identified without guessed terminals. External rectification, capacitors, inductors, dividers and compensation remain distinct. Source UVLO/PAUSE/timing wording gaps and unknown device values/placements are preserved. No manufacturer artwork is copied; the original graph transcriptions are MIT licensed.

Three unchanged photographs from Richard Kaußler / Richi’s Lab’s MP2307-associated module analysis show an independent specimen marked MP9924. The photographs and six approximate image-derived hit regions retain CC BY-NC 4.0, as stated by the source reuse policy, and are excluded from the project MIT license. Two power-device fields are not assigned individually to M1/M2. Bootstrap-pad and driver candidates remain source hypotheses; no exact manufacturer mask, pad number, electrical net or calibrated die placement is asserted.

Tesla MA7805 family circuit and independent die views

The original graph transcribes the undated Tesla MA7805/MA7812/MA7815/MA7824 catalog reading scan, physical page 1 printed 68, qualified by the higher-contrast Tesla schematic linked from Richi’s Lab’s MA7805 analysis. All 17 T-designators, 20 R-designators, two zeners and the 30 pF capacitor are retained. The fractional R11 marking is unresolved; R20 is a 0–25 kΩ family option, distinct from the source-author report that only the 5 kΩ pull-down is active in its MA7805 specimen. The schematic graph is original and MIT licensed; no manufacturer scan is copied into the atlas.

Eight unchanged photographs by Richard Kaußler / Richi’s Lab and fourteen approximate source-image regions retain CC BY-NC 4.0 and are excluded from the project MIT license. The existing ZeptoBars image remains a separate specimen/source. Markings, mask labels and source-described adjustment areas do not establish a mask date, calibrated geometry or individual manufacturer T/R/C placements.

PAM8403 and AY-3-8910 audio references

The original graphs follow Diodes PAM8403 DS36439 Rev. 2-3, September 2020, pages 2 and 7–8, and an undated General Instrument AY-3-8910 catalog extract, printed pages 5-18–5-25. The PAM8403 graph preserves eight resistor symbols, functional audio/protection paths and conflicting amplifier-sign artwork. The AY graph preserves 16 octal-labelled registers, sound/control paths and the I/O-label artwork conflict. Neither graph supplies undocumented transistor circuits or physical placement. No manufacturer artwork is copied; the original graph transcriptions are MIT licensed. The pre-existing AY die photograph retains its separate source license.

AD7606B circuit and independent bare-die pad reference

The original circuit graph follows Analog Devices AD7606B Rev. B, June 2025, using a hashed manufacturer reading copy, especially Figures 1, 43, 49 and 84. Eight analog front ends, functional conversion/control paths and independent reference/diagnostic views are transcribed. Forty resistor occurrences include repeated views; they do not assert forty distinct physical resistors. Conflicting REFCAPA/REFCAPB force/sense drawings, external bypass recommendations, unassigned ALDO/DLDO contact pairing and undisclosed transistor interiors remain explicit.

The original numerical pad plot follows the independent AD7606BBCHIPS Rev. 0, February 2022, manufacturer reading copy, Table 8 on printed pages 12–16. Its 95 literal pad rows retain the A/B/C suffixes across 64 numbered function groups. Published die/pad dimensions are separate facts; symbolic markers do not supply pad footprints, a die-edge origin, internal layout or identity with a packaged 2025 mask. The source PDF has 17 printed manufacturer pages and one distributor appendix page. No source artwork or full prose table is copied. These original graph/coordinate drawings are MIT licensed.

ADA4528 single/dual chopper and protection references

The original conceptual graphs follow Analog Devices AN-1114 Rev. B, April 2014, manufacturer application-note reading copy, Figure 1 on page 3. They retain CHOP1–CHOP3, Gm1–Gm5, NF, NULL+/NULL−, feedforward and the three named, unvalued capacitors. The ADA4528-1/-2 Rev. F, August 2017 reading copy, pages 7–8 and 19, supplies the different package contacts, input-to-rail protection description and explicit family cross-reference to AN-1114. The note labels its diagram ADA4528-1; applying the family reference to both dual channels does not establish a recovered dual mask or known sharing of clocks and bias.

Input-protection diode paths are described by manufacturer prose. Their polarity follows the stated normal reverse bias and over-rail forward bias; the paths are not source-drawn diode glyphs or an exact physical diode inventory. Chopping-network switches, notch-filter internal capacitors, device parameters and physical locations remain undisclosed. External feedback/noise-filter parts and optional exposed-pad wiring are excluded from internal counts. Hashes identify the archived reading copies, not verified byte identity with the primary host. No manufacturer artwork or full prose is copied; these original graph transcriptions are MIT licensed.

LTC2500-32 input-load and digital-filter references

The original conceptual graph follows Linear Technology / Analog Devices LTC2500-32 250032fb Rev. B, January 2018, using the hashed manufacturer reading copy. Figure 3, page 14, supplies the sampled-input switch, protection, RON and CIN equivalents; Figure 5, page 15, supplies a separate fully averaged input-load model. The approximate 40 Ω and 22 kΩ equivalents do not establish distinct physical passive resistors, and the 45 pF load model does not recover the CDAC capacitor inventory. Protection upper diodes return to REF. External driver/filter/reference circuitry is excluded.

The graph also follows the page 12 overview, Figure 26 filter bank, Figure 41 independent averaging detail and pages 33–45 control/output descriptions. Logical selector legs are not MOS gate inventories. It preserves the ordinary versus timing-controlled averaging downsamplers, power-of-two averaging normalization, optional 54-bit averaging read, and 32-bit composite frame with its 24-bit differential field. Control-word artwork/prose bit-order and DCE/DGE spelling discrepancies remain explicit. Source ground/bias and physical mask/device correspondence remain unresolved. The PDF has 54 manufacturer pages plus a distributor appendix; its hash does not assert primary-host byte identity. No manufacturer artwork or full prose is copied. The original graph transcription is MIT licensed.

AD7768 and AD7768-4 sampling and channel references

The original graphs follow Analog Devices AD7768/AD7768-4 Rev. C, August 2022, using a hashed manufacturer reading copy. Figure 84 on page 56 supplies the input-protection diodes, precharge bypasses, crossed PHI0/PHI1 sampling switches, CS1/CS2 and unvalued return-resistor glyphs. Per-channel references, filtering, offset-before-gain correction, status frames and variant-specific package/control relationships follow the associated source sections and tables. The 107-page reading copy contains 106 manufacturer pages and a distributor appendix. A newer primary Rev. D, April 2025, was observed; these maps retain the inspected C reference.

Unlettered clamp rails and sampling returns remain independent local references without guessed A/B supply or analog/digital ground assignments. Source switch and buffer symbols do not establish transistor polarity, count or hidden circuitry. Repeated input-template symbol occurrences are not a physical-device inventory. No manufacturer artwork is copied, no physical die placement is asserted, and the original graph transcriptions are MIT licensed.

AD580 and ATmega328P physical die photographs

Seven unchanged microscope photographs from Richard Kaußler / Richi’s Lab’s AD580 analysis and Atmel ATmega328P analysis are linked with36 approximate source-supported image regions. They retain CC BY-NC 4.0, under the source reuse policy, and are excluded from the project MIT license. Source-coloured memory photographs support the region identifications but are not copied into the viewer. Only actual intact-metal or deprocessed die micrographs enter these records.

The AD580 bandgap8:1 ratio and trim functions follow the source author; individual hidden terminals and device parameters remain unresolved. The source-identified Atmel ATmega328P specimen is grouped under the current Microchip model family without claiming every ordering suffix uses the photographed mask. SRAM block numbers are editorial, not addresses. The purposes of two additional physical Flash pages and possible configuration-register regions remain hypotheses. No GDS, circuit drawing, per-cell transistor netlist or calibrated mask geometry is generated.

Timer and Intel 80286 physical die photographs

Ten unchanged microscope photographs from Richard Kaußler / Richi’s Lab’s Texas Instruments NE555, National Semiconductor LMC555 and Intel 80286 analyses retain CC BY-NC 4.0, under the source reuse policy. They and their 36 source-supported approximate physical-region overlays are excluded from the project MIT license. No package images, source schematics or generated layouts are included.

555A,555B and NE555D remain literal markings of independent specimens. The changed D layout does not inherit older divider coordinates, and segmented emitter fields are not assigned unreported transistor designators or discharge roles. The LMC555 supply-potential perimeter is distinguished from ground. The Intel substrate-pump identification does not establish its individual transistor/capacitor topology, and the visible 1982 copyright mark is not a fabrication date. New photographs are not registered onto the existing Commons or ZeptoBars specimens.

NE558D and UD61256DC physical die photographs

Five unchanged microscope photographs from Richard Kaußler / Richi’s Lab’s Signetics NE558 analysis and UD61256 revision-4 analysis retain CC BY-NC 4.0, under the source reuse policy. The photographs and their 54 approximate physical-region overlays are excluded from the project MIT license. Package pictures, source schematics, coloured pad-reference pictures and mixed-device architecture figures are not added to the viewer.

The source packages identify NE558D 9318KK and UD61256DC 07 specimens, distinct from the existing Commons specimens. Timer-section and transistor-field numbers are editorial; no discharge/output role or terminal net is assigned to the eight visible power fields per timer photo. DRAM interface labels follow the author’s pad picture. Three proposed extra-pad functions retain question marks. Source prose and architecture artwork use different cell-count expressions; the map does not resolve them into a physical cell inventory. Two redundancy test pads are labelled without inventing fuse states, programming voltages or a repaired-column map.

ST UA741 and U1001 physical photo annotations

Five unchanged die micrographs from Richard Kaußler / Richi’s Lab’s ST UA741 analysis and twelve approximate marking regions retain CC BY-NC 4.0, under the source reuse policy. They are excluded from the project MIT license. The package photograph is excluded. Literal identifiers and mask-revision entries do not locate individual schematic transistors or establish specimen manufacturing dates.

The existing ZeptoBars U1001C photograph remains unchanged, with fourteen approximate regions under its CC BY 3.0 license. Selected physical identifications follow Richi’s Lab’s independent U1001 analysis. Regions are located independently on the ZeptoBars pixels using corresponding visible patterns and the literal U1001-3 identifier. Test-device interpretations remain tentative. No package-suffix identity, transistor netlist or calibrated mask registration is asserted. The overlays are excluded from MIT.

TI TL431 physical component photographs

Four unchanged microscope views from Richard Kaußler / Richi’s Lab’s TL431 analysis and thirty-eight approximate physical regions retain CC BY-NC 4.0, under the source reuse policy, and are excluded from the project MIT license. They include a photographic detail pair and a micrograph with the source’s original terminal arrows. Package pictures, schematic drawings and coloured component-reference figures are excluded. The existing ZeptoBars image remains a separate specimen with its own license.

T-designators are source-author labels. T4a and T4b are physical portions of one source transistor; the region total is not a transistor inventory. Three labelled emitter islands belong to the junction-capacitor structure. No unreported wiring or diode coordinates are supplied. The source’s unexplained contour remains unknown.

National LM710CH physical component regions

The unchanged ZeptoBars LM710CH micrograph has twenty-eight approximate component, contact and marking regions under CC BY 3.0. Component names follow Richard Kaußler / Richi’s Lab’s LM710 analysis, independently matched by the literal 4B3B identifier and corresponding visible device patterns. Circuit-function notes follow the source schematic; they are not recovered conductors or calibrated terminal coordinates.

Two unchanged earlier-revision CH microscope views and four physical-feature regions retain CC BY-NC 4.0, under the source reuse policy. Their package reads LM710CH / 816C. The later source package reads LM710H / H82AD; those pictures are not added to this exact-part record. The earlier A-marked die receives no Q/R/D transfer. Package and assembly photos, schematic drawings and source component-reference artwork are excluded. Photos and image-derived overlays are excluded from the project MIT license.

LH0042CH dual-JFET and bipolar-die micrographs

Two added ZeptoBars bare-die photographs retain CC BY 3.0. Their thirteen regions and two regions on the existing SEM micrograph use the same license. Thirteen regions on the existing Richi’s Lab JFET and bipolar micrographs retain CC BY-NC 4.0, under the reuse policy. Source photos remain unchanged; photos and image-derived annotations are excluded from the project MIT license.

The source package is explicitly LH0042CH. Gate, drain and source names follow National Semiconductor’s Process83 manufacturer reference, independently aligned to each photographed die. JFET numbering does not assign package pin numbers or input polarity. The bipolar cascode group follows the source comparison; individual Q3/Q4 positions and a complete circuit extraction remain unresolved. The reference drawing, nominal schematics, comparison artwork and optical package/assembly views are not published.

UltraSPARC T1 prototype photograph

The unchanged original UltraSPARC T1 prototype die photo by Fritzchens Fritz is released under CC0 1.0. The original file remains on Flickr’s image host. Thirty-six approximate functional regions are also dedicated under CC0. The previously excluded composite remains excluded.

All functional placements are inferences on an independent prototype. Macro names and tentative instance numbers follow the physical micrograph in James Laudon’s Sun Microsystems presentation, UltraSPARC T1: A 32-threaded CMP for Servers, printed page 31, 31 March 2006. Five example-core regions follow Figure 2-2, printed page 2-3, of Sun’s OpenSPARC T1 Microarchitecture Specification, April 2008. Both references retain their publisher links, page locators and PDF hashes in the source data. Source PDF artwork, hand-drawn floorplans, diagrams and masks are not redistributed. Prototype unit correspondence, precise boundaries, actual routing and transistor identities remain unverified.

Visual6502 revision D micrographs and photo annotations

The two linked revision D photographs retain the original Visual6502 credits and CC BY-NC-SA 3.0 license from their archived original wiki image descriptions. The stripped-die photo has 3,510 approximate hit regions derived from the pinned Visual6502 transistor bounds. Terminal node IDs and aliases are literal source metadata. The separate Commons revision A photograph has no transferred transistor coordinates. Source images are unchanged. Full credits, geometry license and alias MIT notice. Shared-node highlighting shows netlist membership on the photograph, without claiming a visible wire route, source/drain polarity, simulation or GDS.

LM308AH microscope photograph and component facts

The additional LM308AH view links Ken Shirriff’s original die photograph at its original publisher. The image remains unchanged and is credited to Ken Shirriff; no open photograph license is asserted. Atlas hit regions identify components documented in the source analysis. Selected input-stage terminal connections are read from the source’s full numbered circuit; A-node identifiers are assigned by the atlas. Source viewer code, prose notes, schematic artwork and package photographs are excluded from the public bundle. The separate ZeptoBars photograph keeps its original CC BY 3.0 attribution and receives no transferred coordinates.

AD741KH-marked specimen and AD741 family

The AD741 family record links Ken Shirriff’s original photograph of the die in the package marked AD / 741KH / 8147. The photograph remains unchanged at its original publisher and is credited to Ken Shirriff; no open photograph license is asserted. Component designators and circuit incidence follow the source analysis and numbered reference circuit. A-node identifiers and the two Q13 collector-branch labels are atlas references, without assigned contact coordinates. The 24 numbered transistor regions and two unconnected structures are source identification units. Package photographs, reference schematic artwork and source viewer code are excluded from the public bundle. Ten historical ordering models are transcribed literally from Analog Devices AD741 Rev. A, page 4; the photographed layout is not asserted for every order code.

ST-marked UA7805CK microscope photograph

The UA7805CK record links Ken Shirriff’s original die photograph and preserves his attribution, without asserting an open photograph license. Regions and B/E/C text-label positions follow the source’s die viewer and corrected analysis. Text anchors are not measured terminal-contact footprints. C2/C3 junction-capacitance implementations and Q9’s proposed role remain hypotheses. R22/R23 reference-circuit elements are unlocated on this photograph. Vout and Vsense are separate die pads with separate bonds to one external output terminal. The observed package model is classified as a vendor model number, not an independently verified ordering code. Source scripts, schematic artwork and package photographs are excluded from the published visual collection.

SN74181J original microscope photographs

The SN74181J record links Ken Shirriff’s original surface and metal-removed die photographs, credited to him without asserting an open photograph license. Nine local inverter hit regions follow his component identifications registered to the metal-removed original. Selected terminal links use atlas-assigned local node identifiers. The disputed external input assignment and Q3 collector connection remain unresolved. The source’s 7404 comparison does not supply a physical R4 or verified resistor values for this specimen. Combined photo/schematic figures, package photographs and source artwork are excluded from the published visual collection.

54AS04 and Motorola-attributed 2N2222A micrographs

The added microscope originals retain Richi’s Lab credit and CC BY-NC 4.0 terms. The 54AS04 analysis supplies model markings, two-layer construction and alignment-feature interpretation; its six repeated inverter fields are marked as inferred and receive no invented transistor terminals. The separate Commons image keeps its original license and receives no transferred coordinates. The 2N2222A analysis identifies the inner emitter contact and surrounding base structure. Atlas contact patches belong to one transistor; the unseen collector remains unlocated. Healthy die photographs are linked unchanged. Package/header photographs, breakdown images, damage illustrations, source diagrams and video remain outside the public visual collection.

NTE923 micrographs and circuit-reference facts

The three NTE923 microscope originals retain Richi’s Lab attribution and CC BY-NC 4.0 terms. Component labels and selected circuit relationships follow the source analysis. The original color photos remain unchanged; only approximate interactive regions and terminal incidence are added. Q3 collector branches and Q13 emitter branches remain distinct. The source’s two R7 usages are disambiguated without inventing missing resistor designators. Distributed C1/C2 photo patches represent two reference capacitors. The unlocated Q13 emitter resistor, uncertain D4/Q23/Q24 roles, and proposed wafer provenance remain explicit. Package photographs, circuit artwork and the monochrome labeled die reference are excluded from the public visual collection.

RCA CA3080 provisional photo correspondence

The original CA3080 die photograph retains Richi’s Lab credit and CC BY-NC 4.0 terms. The source analysis identifies the 6389 die marking and states that the die matches its AN6668 circuit. Individual component/pad locations in the atlas are provisional inferences from visible fields, routing and topology; the source supplies no component coordinate table. Reference terminal links do not claim a measured physical netlist or contact polarity. The original image remains unchanged. RCA application-note schematic artwork, block diagrams and the package photograph are excluded from the public visual collection.

A second CA3080 connection review corrects the provisional Q3/D1 and Q10/D6 field pairs and the IABC/VM lower-pad pair. All circuit/pad locations remain inferred. The original photograph and 51 reference-terminal incidences are unchanged. Private segmentation diagnostics are review aids only and are excluded from the published collection; they do not establish recovered masks, buried paths or contact polarity.

AMD AM685HL revision-specific microscope views

The two originals retain Richi’s Lab credit and CC BY-NC 4.0 terms. Contact and revision facts follow the AM685HL specimen analysis: Q3/Q4 have three emitters, D1/D2 lack the older cross-branch wiring, R9 is metal-bypassed, and substrate contacts were expanded. Q4’s contact crop and source comparison regions are separately registered to the unchanged originals. Individual emitter branch nodes remain unresolved; repeated views do not count new transistors. The independently photographed ZeptoBars AM685DL receives no transferred geometry or HL revision changes. Package views, cross sections, older printed metal artwork, comparison composites and circuit drawings are excluded from the public collection.

National LM741 U-step pad annotations

The existing ZeptoBars LM741CH micrograph retains its CC BY 3.0 attribution. New overlay labels compare its visible 741U identifier and seven-pad arrangement with the National Semiconductor LM741 MD8/MW8 die document hosted by TI, pages 1–2, dated October 9, 2006. Individual mappings remain inferred. Richi’s Lab supplies specimen context and bounded stage descriptions. No manufacturer pad drawing, schematic or package photo is republished.

National DM74LS14 die photographs

Two original Richi’s Lab DM74LS14N micrographs retain Richi / Richi’s Lab attribution and CC BY-NC 4.0 licensing. The unchanged originals receive approximate gate-field and identifier overlays. Extra input-device structures remain hypotheses. Package and TAB assembly photographs are excluded. Exact commercial codes come from National Semiconductor’s 1987 LS/S/TTL Logic Databook, printed 2-24 / PDF 108; the package diagram is not republished.

Philips TDA7000 microscope views

Five unchanged publisher-hosted microscope images from Ken Shirriff’s TDA7000 analysis receive physical hit regions and selected source-based electrical references. The source credits the original die photograph to the IEEE Microchips exhibit; analysis, crops and labels are credited to Ken Shirriff. Copyright is retained; no open photograph license is asserted. Cross-section drawings, circuit diagrams and package imagery are excluded. Atlas node numbers are editorial references, not package pins or a recovered whole-chip netlist.

TDA7000 source-numbered close-up

The additional publisher-hosted microscope image from Ken Shirriff retains the original component numbers and colored trace annotations over die pixels. Copyright is retained. Atlas markers locate those printed numbers and link selected connections from the author’s schematic. The schematic and diagnostic registration images are excluded from publication. Correspondence to other photo views remains unresolved; markers are not measured device footprints.

Intel 8008 microscope views

Four unchanged publisher-hosted microscope views from Ken Shirriff’s stack/interface analysis and ALU analysis receive approximate physical hit regions. Copyright is retained; no open photograph license is asserted. The source figure with transistor circuit symbols over a stack-cell photo is excluded from the public gallery. Metal-intact and metal-removed preparations remain separate; no device count or coordinate transform between views is claimed.

8085D microscopy and ACT register fields

The 8085 ALU analysis by Ken Shirriff credits the Visual6502 team for the chip microscopy. Two unchanged publisher-hosted images retain that credit and source labels. Interactive fields describe the observed 8085D die and eight ACT storage bits; they are not recovered transistor masks. No open photograph license is asserted. The existing Commons 8085A photo is a separate specimen and receives no transferred coordinates.

Intersil CA3096 transistor-array microscopy

Two original Richi’s Lab CA3096 die photos are retained under CC BY-NC 4.0. Approximate overlays infer five device identities and sixteen pad functions using the Intersil 1997 datasheet, pages 1 and 12. Seven historical ordering codes are listed literally. Fourteen parallel-element fields belong to two PNP transistors, not fourteen additional devices. Source circuit/metal drawings and package photos remain excluded.

Motorola 6800 source transistors on microscopy

The Visual6502 6800 photos, preserved gallery credit Greg James for microscopy and Christian Sattler for stitching. Two actual photographs are linked unchanged under CC BY-NC-SA 3.0. The etched view has approximate bounds for all 3,995 pinned Visual6502 transistor records, preserving the 72 weak flags, literal gate/c1/c2 nodes and published aliases. Tracing credit: Ijor; alias credit: Ijor, Segher Boessenkool and Ed Spittles. See the retained notice. The Commons C2-mask photo is separate and unregistered. Reconstructed mask imagery remains excluded.

Motorola MC68000 physical source components

The third-preparation microscope photograph and its publisher microscope tiles credit John McMaster, copyright 2013, CC BY-NC-SA with no version specified. No license version is inferred. Extraction/vectorization credit belongs to Olivier Galibert and Quietust; the source materials and pinned extractor establish the matching preparation. See the MC68000 notice.

Original publisher pixels remain unchanged and externally hosted. Approximate overlays retain 34,869 source transistor branches with literal T1/gate/T2 source indices, 102 capacitor extents and 62 symbolic one-pixel pad anchors. Shared gate bounds are not exact individual transistor or contact boundaries. Pad names do not establish package-pin or address-bit identities. The Commons specimen remains separate and unannotated. The 938 physical branches absent from the reviewed source graph and 47 source net indices without retained component incidence remain explicit exceptions. The author-defined virtual VCC link is not drawn as an observed conductor. Private microscopy captures, vector masks, extraction output and research archives are excluded from the deployed file list.

BC847BS separate single-transistor die photographs

The ZeptoBars BC847BS source documents two separate dies in the photographed package. Both original microscope photographs retain the publisher's CC BY 3.0 license. Whole-die identity fields identify one source-described NPN transistor per die; they do not locate the active transistor footprint. Visible bond-pad fields retain unresolved electrical roles. No package-device numbering, matching guarantee, terminal identity or internal wire path is inferred. The computed difference image is excluded.

ESP32-P4 source preparation photographs

The original electronupdate teardown, also available through its public Atom post, identifies two microscope views of the P4 SoC before and after source top-metal removal. Images remain unchanged on the original publisher host, credited to electronupdate. No open reuse license is asserted. Stacked PSRAM, companion C6, flash, module/PCB and oscillator images are separate and are not counted as P4 die photographs. Visible preparation damage is retained; no internal geometry, electrical terminal identity or signal path is inferred.

LM710 source circuit-terminal membership

The existing ZeptoBars LM710CH photograph retains CC BY3.0 and its unchanged approximate component fields. The Richi's Lab LM710 analysis supplies matching B-layout designators and the published equivalent schematic. Twenty component fields and six source-labelled contact fields now carry56 schematic terminal incidences on19 Atlas node references. Q6/Q10 retain their base–collector ties; D1/D2 retain their separate Zener polarity. Node highlighting represents published electrical membership, not measured contact coordinates, an observed wire route, a transistor extraction or complete die mapping. No terminal connections are transferred to the earlier A-marked specimen. Original author diagram pixels remain excluded from public microscopy.

TL431 selected source circuit connections

The existing Richi's Lab TL431 photographs retain CC BY-NC 4.0. Selected source schematic terminal relationships are attached to 22 unchanged fields on the matching clean photograph: 52 terminal incidences on 16 represented Atlas nodes. T4a/T4b remain physical portions of one source electrical T4. T2 retains generic bipolar-transistor identity with NPN/PNP polarity unassigned. The two 800-ohm resistor fields, interleaved network and unlocalized D1/D2 remain explicit gaps. The manufacturer detailed schematic, page 21, independently checks circuit junctions; it does not establish the photographed mask. Node highlighting does not draw an observed wire route or assign microscopic contacts, capacitor plates or package pins. No connections are transferred to the separate ZeptoBars specimen or other preparations.

AY-3-8910 source functional-block fields

The added unchanged microscope stitch is by Timm Reinisch / Dr. Stack van Hay, documented in the original article. Its matching functional-block view supplies the names for 33 approximate hit fields. The clean photo remains on the pinned source mirror, whose README identifies the original photographer. No reuse license for the microscopy or source annotation artwork is asserted. The labelled tile composite and deathsoft's separate GPL-3.0 schematic are not republished. R0–R17 identify source registers, not resistors or transistors. No labels are transferred to Sean Riddle's separate Commons photograph, and transistor terminals, electrical nets and wire paths remain unresolved.

Science Museum Group Intel 4004 photograph

The Intel 4004 die-only crop is from Science Museum Group object 2000-455. Image © The Board of Trustees of the Science Museum; Science Museum Group Collection; object credit Intel. The photograph and native crop are licensed under CC BY-NC-SA 4.0, separately from this repository’s software. Only a rectangular crop was applied. See the image notice for exact crop coordinates and source hashes. This low-resolution overview has no component annotations.

Science Museum Group ARM1 photograph

The ARM1 die-only crop comes from Science Museum Group object 2014-91/1. Image © The Board of Trustees of the Science Museum; Science Museum Group Collection; donated by ARM Limited. The photograph and native crop are licensed under CC BY-NC-SA 4.0, separately from repository software and the other ARM1 sources. Only a rectangular crop was applied; glare and low contrast are preserved. See the image notice for crop coordinates and hashes. No component annotations or CIF geometry were transferred.

YM3812 IKAOPL pad-label adaptation

The 20 source-identified pad labels, six signal text markers, 35 representative source cell rectangles, and their approximate positions on the YM3812 image are adapted from IKAOPL wires.svg. The source vector is not itself published as a micrograph; the visual registration and specimen identity are not independently verified. The image remains CC0 as credited separately.

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