Fundamental limits of information processing

Computing technologies convert information between two states. A computation encodes a problem into the state of a physical system, evolves that state through a controlled sequence of transformations, and reads the answer out of the final state. In an earlier post I treated computing as a single domain and gave it three bounds, the quantum speed limit on its rate, the Landauer limit on its energy, and the Bekenstein limit on its memory. The previous post took memory out of that list, since the Bekenstein bound sits far above the most that a kilogram of matter can hold and the bound a real medium reaches first is chemical. Here I want to run the same exercise on what is left, which is the transformation of information rather than its retention. It turns out that the quantum speed limit is a correct bound that no processor comes within thirty orders of magnitude of, because a dissipative switch spends its energy on its environment instead of on its logical state, and that the energy floor is set by reliability rather than by erasure, at about eighty times the Landauer limit. Underneath both of them is the removal of heat, which decides how much computing fits into a given volume.

The size of the gap

Processing has three figures of merit, and the distances to their bounds are very different.

Rate is the first, and it is the widest of the three in this series. A 1 kg, 1 L ultimate computer performs 5.4 × 10⁵⁰ operations per second (Lloyd, 2000; Margolus & Levitin, 1998), while a 2025 state-of-the-art computer of the same mass and volume performs ~10¹⁴ operations per second (NVIDIA, 2024). That is a gap of ~37 orders of magnitude, against 6 for communications and 16 for storage density. The two figures are not counted in the same unit, since Lloyd’s operations are elementary orthogonalizing steps while the machine’s are arithmetic operations on tens of bits each, and counting individual gate switchings instead puts a large processor near 10¹⁹ per second and the gap near 32 orders. I will argue below that almost none of it is addressable on either count.

Energy is the second. At the 45 nm node a 32-bit addition costs ~0.1 pJ (Horowitz, 2014), and newer nodes have pushed it lower. That addition maps 64 bits of input onto a sum whose entropy is 32.7 bits, so it discards 31.3 bits, and the Landauer minimum for it is 31.3 k_BT ln 2 = 90 zJ (Landauer, 1961). The gap is a factor of 1.1 × 10⁶, or ~6 orders of magnitude, which works out to 3.2 fJ per erased bit against 2.9 zJ. The section on reliability below raises that minimum by a factor of eighty and narrows the room to three or four orders.

Power density is the third, and it is the one already at its bound. A high-performance processor dissipates on the order of 100 W/cm², and monolithically integrated microfluidic cooling has removed 1.7 kW/cm² using 0.57 W/cm² of pumping power (van Erp et al., 2020), so about one order of magnitude is available with cooling that has already been demonstrated. A fully packed array of minimum-size switches running at full speed would dissipate ~4 × 10⁶ W/cm², which is three orders beyond that demonstration and more than four beyond current practice. Therefore energy per operation is the gap worth attacking, heat removal is the constraint that keeps the rate bound out of reach, and reliability sets the energy floor.

The hierarchy of bounds

Three different bounds are called the speed limit of computation, and they apply to different quantities.

The Margolus-Levitin bound gives the minimum time for a quantum state of mean energy E above its ground state to evolve into an orthogonal state, t ≥ πℏ/2E (Margolus & Levitin, 1998), so a system of energy E performs at most 2E/πℏ elementary operations per second. Levitin and Toffoli later showed that this bound and the Mandelstam-Tamm bound based on energy spread combine into a single limit that is tight, in the sense that a family of states approaches it arbitrarily closely, with exact attainment only when the energy spread equals the mean energy (Levitin & Toffoli, 2009). Bremermann’s earlier argument gave E/h, which is a factor of four lower (Bremermann, 1962). Lloyd applied the Margolus-Levitin form to the entire rest energy of a kilogram of matter and obtained the 5.4 × 10⁵⁰ operations per second quoted above (Lloyd, 2000).

However, the bound counts orthogonalizations of the whole state, and almost every one that a dissipative switch performs is a rearrangement of its environment rather than a change in the logical variable. The 3.2 fJ that a 45 nm datapath spends per erased bit is delivered to an enormous number of electronic and vibrational degrees of freedom instead of to the next logical state, and Margolus-Levitin counts the reshuffling of those degrees of freedom as evolution. Evaluated at that energy the bound gives 5.2 × 10⁻²⁰ s, against a gate delay near a picosecond, which is a factor of 2 × 10⁷. The bound is therefore correct and not restrictive, since a transistor could change its total state that fast and would compute nothing by doing so, and closing the distance would require every joule spent to move the logical variable rather than the bath. Markov’s survey separates bounds of this kind, which are correct but loose by construction, from the ones that govern engineering practice (Markov, 2014).

The Landauer limit is the second bound. Erasing a bit dissipates at least k_BT ln 2, which is 2.9 zJ at room temperature (Landauer, 1961), and the bound has been verified in a colloidal particle in a modulated double-well trap (Bérut et al., 2012) and in nanomagnetic bits (Hong et al., 2016). It applies per erased bit rather than per operation, and reversible computation carries no such floor (Bennett, 1973). Bennett located the unavoidable dissipation of any measurement-and-feedback machine in the clearing of its record rather than in the measurement itself (Bennett, 1982; Bennett, 2003), which is the same accounting the previous post applied to a refresh controller.

A real processor runs into a third requirement before either of these, and it comes from the same physics that set the retention barrier in the previous post.

The reliability floor

A logic state is a system held on one side of an energy barrier, and the bath knocks it over the barrier at the Kramers escape rate, τ₀⁻¹e^−ΔE/k_BT (Kramers, 1940). Requiring a per-operation error probability of at most ε gives the barrier requirement ΔE/k_BT = ln(1/ε), and a machine that performs N operations without an error needs ε ≲ 1/N, so ΔE ≥ k_BT ln N. Zhirnov and colleagues note that tunneling makes matters worse, since at a barrier of k_BT ln 2 the error probability of a nanometer-scale switch would exceed one half (Zhirnov et al., 2003). Keyes and Landauer examined the same trade in 1970 and pointed out that the reliability can also be bought with time rather than with energy, at a cost in speed (Keyes & Landauer, 1970), which is the exchange the section on reversibility below returns to.

A machine with 10¹⁰ gates switching at 1 GHz performs 10¹⁹ operations per second, or 8.6 × 10²³ in a day, and one error per day sets ln N = 55.1. In a dissipative switch the barrier is paid on every crossing, so the energy per operation is at least 55 k_BT, which is 0.23 aJ at room temperature and about eighty times k_BT ln 2. Extending the requirement is cheap for the same reason it was cheap in storage, since a year of error-free operation instead of a day costs 6 k_BT more. In storage the barrier requirement was k_BT ln(t/τ₀p) and grew logarithmically with the retention time, and here it is k_BT ln N and grows logarithmically with the number of operations. The same Kramers exponential sets both.

However, the move that worked in storage does not work here. There, relaxing the raw error rate and correcting the errors with a code bought barrier height at a cost in code rate, and the trade was favorable because a good code at a raw error rate of 10⁻³ costs about 1% of the capacity. Replicating a gate costs a factor of three. Triple modular redundancy with majority voting takes a raw error rate ε to roughly 3ε², so reaching the 1.2 × 10⁻²⁴ above from redundant gates needs a raw rate of 6.2 × 10⁻¹³ and a barrier of 28.1 k_BT, for 84.3 k_BT per useful operation against 55.1 uncoded. A second level of voting costs 131.4. Von Neumann’s construction synthesizes a reliable machine from unreliable components with a redundancy that grows logarithmically in the number of gates (von Neumann, 1956), which is the same scaling as the uncoded barrier with a worse constant in front of it. Redundancy therefore does not lower the energy per useful operation in logic, because the uncoded barrier is already logarithmic in the quantity that redundancy is trying to fix.

That difference shows up in how machines are actually built. Memories ship with error correction and logic datapaths do not, and the reason is visible in the numbers above. A 45 nm datapath spends 7.7 × 10⁵ k_BT per erased bit, and dividing that across the few hundred gate switchings an adder performs still leaves of order 10⁵ k_BT per switching, three to four orders of magnitude above the 55 k_BT requirement. Its thermal error rate is therefore far below anything a code would be built to catch, and the errors that do occur in logic come from particle strikes, supply droop, and device variation instead. A storage cell at 60 to 75 k_BT sits close to its own barrier requirement by design, because density is the quantity a memory is optimizing.

Therefore the energy floor of processing is set by reliability rather than by erasure, and the room above it is three to four orders of magnitude. At 100 W, a machine at 3.2 fJ per erased bit erases 3.1 × 10¹⁶ bits per second, against 4.4 × 10²⁰ at 55 k_BT per erased bit, and the second figure is itself a lower bound because a datapath switches more than once per bit it discards.

Reversibility and the cost of avoiding erasure

Both the Landauer term and the reliability term can be avoided, and the price is time and hardware. Bennett showed that any computation can be embedded in a reversible one (Bennett, 1973), and a reversible machine still needs a barrier to hold its state but does not have to dissipate that barrier on every crossing, in the same way that a passive memory pays for its barrier once at the write and nothing thereafter.

In a circuit this is done with adiabatic switching. Charging a node through a resistance R in a time τ dissipates approximately (RC/τ)CV² rather than the ½CV² of an abrupt transition, so the dissipation per operation falls as A/τ for a constant A set by the device (Athas et al., 1994). The consequences at a fixed total throughput R_tot follow directly. Each gate delivers 1/τ operations per second, so the machine needs N = R_totτ gates, and its total power is R_totA/τ. The product of power and gate count is then constant, so halving the power costs doubling the hardware and doubling the latency of every operation. The saving is therefore bought with area and time in fixed proportion, and reversible logic lowers power only as fast as it is allowed to grow the machine and slow it down.

Two costs sit on top of that. Bennett’s own space-time trade-off for reversible simulation means that running a computation reversibly requires either storing the intermediate history or recomputing it, and neither is free (Bennett, 1989). Leakage limits the τ that is worth using, since a gate that idles longer leaks longer. Energy-recovering logic was designed and fabricated in the 1990s and was not adopted, because at the operating points that mattered then the area and latency it asked for cost more than the energy it returned. It is being reconsidered now because the constraint on a processor has moved from the cost of the energy to the removal of the heat, and a machine limited by cooling can afford to buy area and latency in a way that a machine limited by its electricity bill cannot.

Heat removal

Dennard scaling held that shrinking a transistor and its supply voltage together keeps the power per unit area constant (Dennard et al., 1974), and it ended in the mid-2000s when the supply voltage stopped scaling, because the threshold voltage cannot fall without leakage rising. Power per unit area has grown with each node since. The consequence at the architecture level is that a growing fraction of a chip has to be left unpowered at any moment, projected to pass half at the 8 nm node, which leaves an average speedup of 7.9× across parallel workloads over five generations against the 32× that Moore’s law would suggest (Esmaeilzadeh et al., 2011).

The endpoint of that trend can be computed for a binary switch whose barrier is the Landauer energy. Localizing an electron well enough that the two states are distinguishable across a barrier of k_BT ln 2 requires x_min = ℏ/√(2m_ek_BT ln 2) = 1.5 nm, and the corresponding switching time is t_min = ℏ/(k_BT ln 2) = 0.04 ps (Zhirnov et al., 2003). Packing those switches at their own size gives 4.7 × 10¹³ devices/cm², and running all of them at full speed dissipates k_BT ln 2 per switch per t_min, or 3.7 × 10⁶ W/cm², with 5 to 10 MW/cm² quoted for the model in its original form. That figure is a lower bound rather than an estimate, since the barrier it assumes is the one the reliability section ruled out. Against the 1.7 kW/cm² that has been demonstrated (van Erp et al., 2020), the shortfall is already a factor of 2 × 10³. Zhirnov and colleagues drew the conclusion in 2003 that the density of computation is set by the rate at which heat can be carried away rather than by how small a switch can be made, and it has held since.

Cooling does not help the energy budget, for the reason the previous post worked through. A barrier of ln N k_BT_c dissipated at temperature T_c and removed to an environment at T_h costs at least ln N k_BT_h drawn from the room-temperature supply once the Carnot work is included, independent of T_c, and real refrigerators run one to three orders above Carnot. Lowering T_c buys density instead, since the minimum barrier and therefore the minimum device volume both fall with it.

The geometry is the same one that limited storage. Heat leaves through a surface while computation happens in a volume, so the ratio of removable power to installed logic falls as the linear dimension grows, and this is why stacking logic in three dimensions has been much harder than stacking memory. Memory can be stacked because most of it is idle at any moment, and logic cannot, for the same reason that produced dark silicon.

Data movement

A processor is full of communication links, and everything in the post on information transfer applies to them. At the same 45 nm node where a 32-bit addition costs 0.1 pJ, reading those 32 bits from an on-chip SRAM costs ~5 pJ and reading them from DRAM costs ~640 pJ (Horowitz, 2014). Moving the operands therefore costs between fifty and six thousand times the arithmetic performed on them, and the ratio has grown with every node because wire energy scales far worse than gate energy. Wulf and McKee named the growing distance between processor and memory speeds the memory wall in 1995 (Wulf & McKee, 1995), and its energy version is now the larger of the two problems.

The volume and surface argument that constrained a dense memory applies here as well. Bandwidth into a package scales with its boundary while the logic and memory scale with its volume, and there is a latency floor underneath that, since a signal crossing a 12 cm board travels at roughly half the vacuum speed and takes ~0.8 ns one way, before any addressing, serialization, or decoding. An interconnect between two chips is a communication link with a very short reach and a very tight energy budget, and as the energy per bit falls toward the femtojoule scale the photon budget per bit approaches the low mean photon number per mode where the choice between a Shannon-limited and a Holevo-limited receiver stops being academic. We are working through that accounting for interconnects in high-performance computing, and that work is in preparation (Gurses & others, 2026; Gurses, 2026).

Parallelism and serial depth

The 37 orders of magnitude above are a count of aggregate operations per second, and aggregate rate is available only to computations that parallelize. Lloyd’s ultimate computer makes the point at the bound itself. Spreading 5.4 × 10⁵⁰ operations per second over 2.1 × 10³¹ bits gives 2.5 × 10¹⁹ operations per bit per second, so one bit changes in 3.9 × 10⁻²⁰ s, while light crosses a 10 cm machine in 3.3 × 10⁻¹⁰ s. Each bit therefore undergoes ~10¹⁰ operations before any signal from it reaches the far side of the machine (Lloyd, 2000). The ultimate computer is a very wide parallel machine rather than a fast serial one, and it can be made serial only by compressing it until the light-crossing time matches the switching time, which is the condition that defines a black hole. Lloyd’s 1 kg black hole holds ~10¹⁶ bits and performs ~10³² operations over a lifetime of ~10⁻¹⁹ s (Lloyd, 2000). That lifetime is shorter than the ~10⁻¹⁶ s I quoted for the same object in the previous post, because the Hawking temperature of a 1 kg hole makes many particle species available to carry the radiation away, and the photon-only estimate is correspondingly slower (Hawking, 1975).

Amdahl’s argument then applies to everything below the bound (Amdahl, 1967). A workload with a serial fraction f cannot be sped up by more than 1/f however many processors are added, so the reachable part of a rate bound depends on the problem and not only on the machine. An honest accounting of processing rate has to separate the aggregate figure from the serial depth available, in the same way that the previous post separated a medium’s raw density from its usable density.

What quantum mechanics buys

The previous two posts found the quantum answer to be a bounded improvement in one case and nothing at all in the other. Allowing arbitrary quantum measurements raises the capacity of a communication channel above the Shannon limit by a factor that grows without bound as the photon number per mode falls, and Holevo’s bound forbids a quantum memory from holding more classical bits than a classical one of the same dimension. In processing the answer appears to differ in kind rather than in degree.

Feynman observed that simulating a general quantum system on a classical machine appears to need resources exponential in the number of degrees of freedom (Feynman, 1982), Deutsch reformulated the Church-Turing thesis as a claim about physical law and defined the universal quantum computer (Deutsch, 1985), and Shor showed that such a machine factors integers in polynomial time (Shor, 1997). Grover’s search gives a quadratic speedup for unstructured search, and that is provably the best any quantum algorithm can do on an unstructured black-box problem, although structured black-box problems admit exponential separations (Grover, 1996; Bennett et al., 1997). No proof rules out a fast classical factoring algorithm, so this is strong evidence rather than a theorem, and Aaronson’s survey of failed attempts to solve hard problems with physical systems is a useful reminder of how the other proposals went (Aaronson, 2005).

Everything else in this post survives the change of substrate. Unitary evolution obeys the Margolus-Levitin bound exactly as a transistor does, so the quantum speed limit is if anything more directly relevant to a quantum computer than to a classical one. Erasure still costs k_BT ln 2, and a quantum computer erases constantly, since initializing a register is an erasure and every round of syndrome extraction discards the syndrome once it has been used. However, that erasure is not where the energy of a quantum computation goes. The published resource estimate for factoring a 2048-bit RSA integer is fewer than a million noisy physical qubits running for less than a week at a 1 μs surface-code cycle and a 0.1% gate error rate, down from twenty million qubits and eight hours in the 2019 estimate (Gidney, 2025; Gidney & Ekerå, 2021). About half of those qubits carry syndrome measurements, so a week of cycling generates of order 3 × 10¹⁷ syndrome-bit erasures, which is 6 × 10⁻⁸ J at 20 mK and 9 × 10⁻⁴ J drawn from the wall once the Carnot work is included. A dilution refrigerator draws on the order of 10 kW continuously, or 6 × 10⁹ J over the same week, about thirteen orders of magnitude more. The thermodynamic cost of a quantum computation is therefore negligible against the cost of holding the machine cold.

The reliability requirement also reappears, and a quantum computer meets it differently. A classical gate buys its error rate with an energy barrier, and a qubit cannot rely on one, since whether a Hamiltonian protects a superposition at finite temperature in three dimensions is still open, as the previous post discussed (Haah, 2011; Brown et al., 2016). Quantum error correction buys the error rate with hardware instead, spending on the order of 2d² physical qubits per logical qubit at code distance d, and the logical error rate per cycle falls by a constant factor for every increase of two in distance, measured at Λ = 2.14 (Google Quantum AI and Collaborators, 2025). A quantum computer therefore spends hardware where a classical one spends energy, which is why quantum roadmaps are written in qubit counts rather than in watts.

Remaining obstacles

Heat removal is the first, and it is the reason the 37 orders above a real processor are not a development plan. Cooling that has been demonstrated in the laboratory is about one order of magnitude better than what a processor uses today, and a fully packed array of minimum switches would need three orders beyond that (Zhirnov et al., 2003; van Erp et al., 2020). Every proposal to raise computational density has to answer this before it answers anything else, and the answers that have worked so far have been architectural rather than thermal.

Data movement is the second, and it is now the larger part of the energy budget in most real workloads. The factor between 0.1 pJ of arithmetic and 640 pJ of DRAM access (Horowitz, 2014) is not a fundamental bound, since the previous post found that most of the cost of a memory access is interconnect and array overhead rather than the bit itself, and the transfer post found the same for a fiber link. It is a large amount of ordinary engineering standing between current practice and a minimum several orders of magnitude lower.

The third is that the reliability floor is close. Three to four orders of magnitude separate a 45 nm switching event from 55 k_BT, and there is no comparable room underneath that for irreversible logic at room temperature. Going further requires either reversible logic, which trades energy for area and latency in the fixed proportion above, or a lower ambient temperature, which the Carnot accounting shows does not pay unless density rather than energy is the objective. Both of those are known and neither is cheap.

The fourth is the same discontinuity the previous post found in storage. The 37 orders between a processor and the Margolus-Levitin bound are not made of engineering steps, because the configurations of matter between a room-temperature switch and Lloyd’s figure are not switches. Lloyd’s number is attained by a kilogram of matter at 5.9 × 10⁸ K, in which every field degree of freedom is treated as computational and nothing holds a state long enough to be read at leisure (Lloyd, 2000). An honest roadmap for processing therefore stops at the reliability floor and the thermal limit above it, and treats the quantum speed limit as a statement about physics rather than as a target.

How you can help

The three domains sit at very different distances from their bounds, and for different reasons. Communications is about six orders of magnitude away, and the payoff is concentrated at the low photon numbers where nobody currently operates. Storage is eleven orders from a bound that is chemical, and one medium is already within a factor of three of the limit of its own physics. Processing is the furthest of the three and has the least of it available, with three to four orders addressable at fixed reliability, a further stretch available only by trading energy against area and latency, and the rest blocked by heat removal and by the absence of any material configuration between a transistor and a plasma.

The three domains also turn out to share their physics more than the taxonomy suggests. A memory pays k_BT ln(t/τ₀p) to hold a state for a chosen time, a processor pays k_BT ln N to change a state a chosen number of times without an error, and both come from the same Kramers exponential. A communication link pays for distinguishing states that are not orthogonal, and a read head, a memory refresh, and a syndrome extraction are all measurements on the same footing. Writing the three bounds in the same units makes it possible to see which one a given technology is actually running into, and in computing it is neither of the two I assigned it in that earlier post.

This post took the computer as given and asked what limits it, where an earlier post asked the question underneath that one, which is what a physical system has to provide before it can compute at all. I recommend this tool if you want to move along these curves yourself and compare the ultimate and current versions of computing, communication, and sensing systems. If you think I have put a bound in the wrong place, or you know of work on reversible logic or on heat removal I should be reading, I would like to hear it, and comments are open below. Next I want to run the same exercise for information extraction.