{
  "schemaVersion": 1,
  "title": "Computing Systems Atlas",
  "edition": "Source-backed research edition",
  "asOf": "2026-11-02",
  "scope": "All computing paradigms and architectures are in scope. Coverage is partial and extensible; no finite complete inventory is asserted.",
  "taxonomy": {
    "paradigms": [
      {
        "id": "digital",
        "name": "Digital computing",
        "description": "Discrete encodings and operations; includes electronic, mechanical, and other realizations."
      },
      {
        "id": "analog",
        "name": "Analog computing",
        "description": "Continuous physical quantities represent variables in a computation."
      },
      {
        "id": "hybrid",
        "name": "Hybrid computing",
        "description": "Distinct computational models combined in one system; record the specific analog–digital, quantum–classical, or other combination."
      },
      {
        "id": "parallel",
        "name": "Parallel computing",
        "description": "Multiple operations or computational agents progress concurrently."
      },
      {
        "id": "dataflow",
        "name": "Dataflow & spatial computing",
        "description": "Dependencies and placement help determine when and where operations execute."
      },
      {
        "id": "neuromorphic",
        "name": "Neuromorphic computing",
        "description": "Neural dynamics, local state, and event communication as computational building blocks."
      },
      {
        "id": "quantum",
        "name": "Quantum computing",
        "description": "Computational models that use controlled quantum states, dynamics, and measurement."
      },
      {
        "id": "probabilistic",
        "name": "Probabilistic computing",
        "description": "Sampling and controlled randomness as computational resources."
      },
      {
        "id": "stochastic",
        "name": "Stochastic bitstream computing",
        "description": "Values encoded in statistical properties of streams; separate from general probabilistic inference."
      },
      {
        "id": "reversible",
        "name": "Reversible computing",
        "description": "Logically reversible transformations, with physical implementation tracked separately."
      },
      {
        "id": "optical",
        "name": "Optical & photonic computing",
        "description": "Light participates in the computation; optical communication alone is insufficient."
      },
      {
        "id": "molecular",
        "name": "Molecular & DNA computing",
        "description": "Molecular states, reactions, or assemblies implement computation."
      },
      {
        "id": "biological",
        "name": "Biological & cellular computing",
        "description": "Engineered living cells or biological networks perform computational functions."
      },
      {
        "id": "reservoir",
        "name": "Reservoir computing",
        "description": "A dynamical system transforms inputs; a readout is trained or configured."
      },
      {
        "id": "unconventional",
        "name": "Other physical computing",
        "description": "Mechanical, fluidic, acoustic, reaction–diffusion, and other physical approaches."
      }
    ],
    "models": [
      {
        "id": "turing",
        "name": "Turing machines",
        "description": "Tape, transition rules, and a computational head."
      },
      {
        "id": "register",
        "name": "Register machines",
        "description": "Programs operating on named storage locations."
      },
      {
        "id": "lambda",
        "name": "Lambda calculus / functional",
        "description": "Evaluation through function application and substitution."
      },
      {
        "id": "logic",
        "name": "Logic & relational",
        "description": "Computation expressed through relations, constraints, and proof search."
      },
      {
        "id": "actor",
        "name": "Actors & message passing",
        "description": "Independent agents communicate through messages."
      },
      {
        "id": "process",
        "name": "Communicating processes",
        "description": "Concurrent processes and explicit communication or synchronization."
      },
      {
        "id": "dataflow-model",
        "name": "Dataflow graphs",
        "description": "Operations connected by data dependencies."
      },
      {
        "id": "petri",
        "name": "Petri nets",
        "description": "Transitions, places, and token flow model concurrent activity."
      },
      {
        "id": "cellular",
        "name": "Cellular automata",
        "description": "Local state transitions over a neighborhood."
      },
      {
        "id": "continuous",
        "name": "Continuous dynamical systems",
        "description": "Differential equations, continuous state, and physical evolution."
      },
      {
        "id": "neural",
        "name": "Neural / spiking networks",
        "description": "Networks of stateful neurons, weighted interactions, and learning rules."
      },
      {
        "id": "quantum-circuit",
        "name": "Quantum circuits",
        "description": "State preparation, gates, and measurement."
      },
      {
        "id": "quantum-annealing",
        "name": "Quantum annealing / adiabatic",
        "description": "Controlled Hamiltonian evolution and an encoded objective."
      },
      {
        "id": "quantum-simulation",
        "name": "Analog quantum simulation",
        "description": "A controllable quantum system represents another quantum system."
      },
      {
        "id": "ising",
        "name": "Ising / QUBO optimization",
        "description": "An objective expressed through interacting variables."
      },
      {
        "id": "chemical",
        "name": "Chemical reaction networks",
        "description": "Species and reactions encode state and transformations."
      },
      {
        "id": "rewriting",
        "name": "Rewriting / membrane systems",
        "description": "Rules transform symbolic or compartmentalized structures."
      },
      {
        "id": "reversible-model",
        "name": "Reversible logical models",
        "description": "Transitions retain enough information to reverse the computation."
      }
    ],
    "architectures": [
      {
        "id": "configured",
        "name": "Externally configured arithmetic",
        "description": "Switches, patching, or wiring establish a computational procedure."
      },
      {
        "id": "stored-program",
        "name": "Stored-program organization",
        "description": "Instruction storage, sequencing, and execution."
      },
      {
        "id": "unified",
        "name": "Unified / von Neumann memory",
        "description": "A shared architectural memory space for instructions and data."
      },
      {
        "id": "harvard",
        "name": "Harvard / modified Harvard",
        "description": "Separate instruction and data storage or access paths; exact variant matters."
      },
      {
        "id": "accumulator",
        "name": "Accumulator machines",
        "description": "A distinguished arithmetic register or unit anchors operations."
      },
      {
        "id": "stack",
        "name": "Stack machines",
        "description": "A stack supplies implicit operands and results."
      },
      {
        "id": "register-memory",
        "name": "Register–memory machines",
        "description": "Operations and addressing combine registers and memory."
      },
      {
        "id": "load-store",
        "name": "Load–store machines",
        "description": "Memory transfers are distinguished from register arithmetic."
      },
      {
        "id": "risc",
        "name": "RISC design approaches",
        "description": "Instruction-set design choices; load–store organization alone is not a complete classification."
      },
      {
        "id": "cisc",
        "name": "CISC / rich instruction sets",
        "description": "Instruction-set complexity is distinct from the internal execution organization."
      },
      {
        "id": "microcoded",
        "name": "Microprogrammed control",
        "description": "A control store sequences lower-level operations."
      },
      {
        "id": "hardwired",
        "name": "Hardwired control",
        "description": "Control behavior implemented directly in logic."
      },
      {
        "id": "pipelined",
        "name": "Pipelined execution",
        "description": "Stages overlap work from different operations."
      },
      {
        "id": "scoreboard",
        "name": "Dynamic scheduling / scoreboarding",
        "description": "Dependencies and resource availability coordinate execution."
      },
      {
        "id": "superscalar",
        "name": "Superscalar / out-of-order",
        "description": "Multiple issue and dynamic execution ordering; classify specific implementations."
      },
      {
        "id": "vliw",
        "name": "VLIW / EPIC",
        "description": "An instruction format exposes multiple operations or explicit parallelism."
      },
      {
        "id": "scalar",
        "name": "SISD / scalar execution",
        "description": "A scalar execution stream; systems may combine scalar and parallel engines."
      },
      {
        "id": "misd",
        "name": "MISD classifications",
        "description": "Multiple instruction streams over one data stream; concrete classification requires careful system boundaries."
      },
      {
        "id": "transport",
        "name": "Transport-triggered architectures",
        "description": "Explicit data transport triggers operations in functional units."
      },
      {
        "id": "capability",
        "name": "Capability-based machines",
        "description": "Unforgeable authority shapes addressing, access, and protection."
      },
      {
        "id": "vector",
        "name": "Vector processors",
        "description": "Instructions operate over ordered collections of elements."
      },
      {
        "id": "simd",
        "name": "SIMD arrays",
        "description": "A shared instruction stream controls multiple processing elements."
      },
      {
        "id": "simt",
        "name": "SIMT GPUs",
        "description": "Groups of logical threads execute under a hardware scheduling model."
      },
      {
        "id": "mimd",
        "name": "MIMD multiprocessors",
        "description": "Multiple instruction and data streams."
      },
      {
        "id": "smp",
        "name": "Shared-memory multiprocessors",
        "description": "Processors communicate through an architectural shared memory."
      },
      {
        "id": "numa",
        "name": "ccNUMA / distributed shared memory",
        "description": "Shared addressability with nonuniform placement and access cost."
      },
      {
        "id": "distributed",
        "name": "Distributed-memory systems",
        "description": "Distinct memory domains exchange data through an interconnect."
      },
      {
        "id": "heterogeneous",
        "name": "Heterogeneous / accelerated systems",
        "description": "Different processing engines cooperate within a system."
      },
      {
        "id": "systolic",
        "name": "Systolic arrays",
        "description": "A regular network reuses data through scheduled local movement."
      },
      {
        "id": "dataflow-arch",
        "name": "Dataflow architectures",
        "description": "Execution mechanisms follow data readiness and dependencies."
      },
      {
        "id": "reconfigurable",
        "name": "FPGA / reconfigurable fabric",
        "description": "Configurable logic, routing, and state form spatial datapaths."
      },
      {
        "id": "cgra",
        "name": "Coarse-grained reconfigurable arrays",
        "description": "Configurable operations and interconnect among larger processing elements."
      },
      {
        "id": "in-memory",
        "name": "Compute in memory",
        "description": "Computation within memory arrays or closely integrated memory structures."
      },
      {
        "id": "near-memory",
        "name": "Near-memory processing",
        "description": "Processing placed near memory; distinguish from array-level computation."
      },
      {
        "id": "wafer-scale",
        "name": "Wafer-scale systems",
        "description": "Compute and communication organized across a wafer-scale device."
      },
      {
        "id": "analog-integrator",
        "name": "Analog integrator networks",
        "description": "Connected integrators and related operators implement equations."
      },
      {
        "id": "crossbar",
        "name": "Analog crossbar arrays",
        "description": "Physical array operations implement weighted aggregation or linear transforms."
      },
      {
        "id": "spiking",
        "name": "Event-driven spiking architectures",
        "description": "Local neuron state and routed spike events."
      },
      {
        "id": "gate-quantum",
        "name": "Gate-model quantum systems",
        "description": "Qubits, classical control, gates, and measurement."
      },
      {
        "id": "annealer",
        "name": "Quantum annealers",
        "description": "A programmable quantum annealing system and its classical environment."
      },
      {
        "id": "analog-quantum",
        "name": "Analog quantum simulators",
        "description": "Controlled quantum dynamics as a model of another system."
      },
      {
        "id": "optical-linear",
        "name": "Optical linear algebra",
        "description": "Interference, diffraction, or optical weighting computes transforms."
      },
      {
        "id": "ising-machine",
        "name": "Physical Ising machines",
        "description": "Coupled physical variables search an encoded energy landscape."
      },
      {
        "id": "pbit",
        "name": "p-bit / sampling machines",
        "description": "Controllable stochastic elements support sampling or optimization."
      },
      {
        "id": "bitstream",
        "name": "Stochastic bitstream datapaths",
        "description": "Stream operations implement arithmetic on statistical encodings."
      },
      {
        "id": "reversible-arch",
        "name": "Reversible / adiabatic circuits",
        "description": "Reversible logic and energy-recovery circuit approaches tracked independently."
      },
      {
        "id": "dna-reaction",
        "name": "DNA / reaction-network architectures",
        "description": "Molecular generation, transformation, selection, and readout."
      },
      {
        "id": "cellular-arch",
        "name": "Cellular / reaction–diffusion arrays",
        "description": "Local interactions, chemical patterns, or cellular rules."
      },
      {
        "id": "reservoir-arch",
        "name": "Physical reservoirs",
        "description": "A driven physical dynamical medium and a configurable readout."
      },
      {
        "id": "mechanical",
        "name": "Mechanical computing mechanisms",
        "description": "Gears, shafts, levers, or other mechanical state transformations."
      },
      {
        "id": "fluidic",
        "name": "Fluidic / pneumatic logic",
        "description": "Fluid flow and pressure implement information processing."
      },
      {
        "id": "fault-tolerant",
        "name": "Fault-tolerant / redundant systems",
        "description": "Redundancy, voting, checking, and recovery shape the organization."
      }
    ],
    "substrates": [
      {
        "id": "mechanical",
        "name": "Mechanical",
        "description": "Motion, position, or mechanical constraints."
      },
      {
        "id": "relay",
        "name": "Electromechanical relays",
        "description": "Electrically controlled mechanical switches."
      },
      {
        "id": "vacuum-tube",
        "name": "Vacuum tubes",
        "description": "Thermionic electronic devices."
      },
      {
        "id": "transistor",
        "name": "Discrete transistors",
        "description": "Individual semiconductor devices."
      },
      {
        "id": "integrated",
        "name": "Integrated electronics",
        "description": "Integrated logic, memory, and mixed-signal circuits."
      },
      {
        "id": "memristive",
        "name": "Memristive / resistive devices",
        "description": "Conductance states and device dynamics."
      },
      {
        "id": "magnetic",
        "name": "Magnetic / spintronic",
        "description": "Magnetic state or spin-dependent behavior."
      },
      {
        "id": "superconducting",
        "name": "Superconducting circuits",
        "description": "Superconducting electronic or quantum devices."
      },
      {
        "id": "photonic",
        "name": "Optical / photonic",
        "description": "Light and optical devices."
      },
      {
        "id": "atomic",
        "name": "Atomic / ionic",
        "description": "Trapped ions, neutral atoms, and related physical platforms."
      },
      {
        "id": "molecular-material",
        "name": "Molecular / chemical",
        "description": "Molecules, reactions, and chemical assemblies."
      },
      {
        "id": "living",
        "name": "Living systems",
        "description": "Cells and engineered biological networks."
      },
      {
        "id": "fluid",
        "name": "Fluidic / pneumatic",
        "description": "Fluid flow and pressure."
      },
      {
        "id": "acoustic",
        "name": "Acoustic / elastic",
        "description": "Waves and mechanical dynamics."
      }
    ]
  },
  "sources": [
    {
      "id": "ibm-history",
      "title": "The IBM System/360",
      "author": "IBM",
      "year": null,
      "type": "Manufacturer historical overview",
      "url": "https://www.ibm.com/history/system-360",
      "scope": "Announcement on 7 April 1964 and compatible family scope; article accessed 1 November 2026.",
      "accessed": "2026-11-01"
    },
    {
      "id": "ibm-architecture",
      "title": "Architecture of the IBM System/360",
      "author": "G. M. Amdahl, G. A. Blaauw, F. P. Brooks Jr.",
      "year": 1964,
      "type": "Designer paper · abstract only",
      "url": "https://doi.org/10.1147/rd.82.0087",
      "scope": "IBM Journal of Research and Development 8(2), pp. 87–101. Indexed abstract inspected; full text not reviewed.",
      "inspection": {
        "method": "Indexed abstract inspected; full paper not reviewed",
        "sections": "General-purpose architecture and family compatibility only"
      },
      "accessed": "2026-11-01"
    },
    {
      "id": "fugaku-spec",
      "title": "Supercomputer Fugaku — Specifications",
      "author": "Fujitsu",
      "year": null,
      "type": "Manufacturer specifications",
      "url": "https://global.fujitsu/en-global/technology/research/fugaku/specifications",
      "scope": "Node, memory, interconnect, storage, and system software sections; accessed 1 November 2026.",
      "accessed": "2026-11-01"
    },
    {
      "id": "fugaku-paper",
      "title": "Co-Design and System for the Supercomputer “Fugaku”",
      "author": "Fugaku design team",
      "year": 2022,
      "type": "System design paper · abstract",
      "url": "https://ieeexplore.ieee.org/document/9658212/",
      "scope": "Published design description; indexed abstract inspected. Full paper has not been reviewed.",
      "inspection": {
        "method": "Indexed abstract inspected; full paper not reviewed",
        "sections": "Scientific-system design and application scope only"
      },
      "accessed": "2026-11-01"
    },
    {
      "id": "loihi-brief",
      "title": "Taking Neuromorphic Computing to the Next Level with Loihi 2",
      "author": "Intel Labs",
      "year": 2021,
      "type": "Manufacturer technology brief",
      "url": "https://download.intel.com/newsroom/2021/new-technologies/neuromorphic-computing-loihi-2-brief.pdf",
      "scope": "Pages 5–7, especially the architecture overview and Table 2.",
      "inspection": {
        "method": "Public PDF retrieved and selected technical pages extracted; organization figure inspected in the seed upgrade",
        "sections": "pp. 5–7; chip organization, local memory, programmable dynamics and communication",
        "sha256": "13a07512031d9168076498f611fbb4bc1c8eb1e78891a5002315970b3cfc4472"
      },
      "accessed": "2026-11-01"
    },
    {
      "id": "optical-paper",
      "title": "All-Optical Machine Learning Using Diffractive Deep Neural Networks",
      "author": "X. Lin et al.",
      "year": 2018,
      "type": "Experimental paper · author preprint",
      "url": "https://arxiv.org/abs/1804.08711",
      "scope": "Physical diffractive network demonstrator; training and optical inference are distinct. Science DOI: 10.1126/science.aat8084.",
      "accessed": "2026-11-01"
    },
    {
      "id": "bennett-paper",
      "title": "Logical Reversibility of Computation",
      "author": "Charles H. Bennett",
      "year": 1973,
      "type": "Foundational paper · transcription",
      "url": "https://www.cs.princeton.edu/courses/archive/fall06/cos576/papers/bennett73.html",
      "scope": "Logical reversibility as a theoretical model, separate from a built energy-recovery implementation.",
      "accessed": "2026-11-01"
    },
    {
      "id": "kung-paper",
      "title": "Why Systolic Architectures?",
      "author": "H. T. Kung",
      "year": 1982,
      "type": "Foundational paper · author-hosted scan",
      "url": "https://www.eecs.harvard.edu/~htk/publication/1982-kung-why-systolic-architecture.pdf",
      "scope": "Regular arrays and data movement; a reading lead for the systolic architecture coverage track.",
      "accessed": "2026-11-01"
    },
    {
      "id": "seed-bush-1931-detailed",
      "title": "The Differential Analyzer: A New Machine for Solving Differential Equations",
      "author": "Vannevar Bush",
      "year": 1931,
      "url": "https://fab.cba.mit.edu/classes/862.22/notes/computation/Bush-1931.pdf",
      "scope": "Journal of the Franklin Institute 212 pp. 447–488. §§4–8, Figs. 2–7, 10–11 inspected; Fig. 7 falling-body setup visually inspected in private PDF page 11.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Primary document retrieval; selected cited sections inspected",
        "sections": "Journal of the Franklin Institute 212 pp. 447–488. §§4–8, Figs. 2–7, 10–11 inspected; Fig. 7 falling-body setup visually inspected in private PDF page 11.",
        "sha256": "f63c0ec83d7395b2c46f846b286ea09f7546a31e44a151a8729ca7d78d337aad",
        "limitations": "Original interpretive diagram, not a netlist or full equipment specification."
      }
    },
    {
      "id": "seed-adleman-1994-detailed",
      "title": "Molecular Computation of Solutions to Combinatorial Problems",
      "author": "Leonard M. Adleman",
      "year": 1994,
      "url": "https://computingbiology.github.io/docs/adleman1994.pdf",
      "scope": "Science 266 pp. 1021–1024; algorithm, Fig. 2 encoding, Fig. 3 gel readout, experimental notes 4–9 and scaling/error discussion inspected.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Primary document retrieval; selected cited sections inspected",
        "sections": "Science 266 pp. 1021–1024; algorithm, Fig. 2 encoding, Fig. 3 gel readout, experimental notes 4–9 and scaling/error discussion inspected.",
        "sha256": "06552d7e0fbbec3b303219bb26b290afe31d2c6c7c4a0aa9ea0f194eeb4b5c14",
        "limitations": "Original interpretive diagram, not a netlist or full equipment specification."
      }
    },
    {
      "id": "seed-loihi2-detailed",
      "title": "Taking Neuromorphic Computing to the Next Level with Loihi 2",
      "author": "Intel Labs",
      "year": 2021,
      "url": "https://download.intel.com/newsroom/2021/new-technologies/neuromorphic-computing-loihi-2-brief.pdf",
      "scope": "2021 brief pp. 3–7; Figs. 1–2 visually inspected; Table 1 neuron microcode, Table 2 flexible memory and event formats, I/O and learning text inspected. Performance footnotes mix measured and simulated results; no speedup claim transferred.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Primary document retrieval; selected cited sections inspected",
        "sections": "2021 brief pp. 3–7; Figs. 1–2 visually inspected; Table 1 neuron microcode, Table 2 flexible memory and event formats, I/O and learning text inspected. Performance footnotes mix measured and simulated results; no speedup claim transferred.",
        "sha256": "13a07512031d9168076498f611fbb4bc1c8eb1e78891a5002315970b3cfc4472",
        "limitations": "Original interpretive diagram, not a netlist or full equipment specification."
      }
    },
    {
      "id": "seed-ibm-system2-launch",
      "title": "IBM Debuts Next-Generation Quantum Processor & IBM Quantum System Two",
      "author": "IBM",
      "year": 2023,
      "url": "https://newsroom.ibm.com/2023-12-04-IBM-Debuts-Next-Generation-Quantum-Processor-IBM-Quantum-System-Two,-Extends-Roadmap-to-Advance-Era-of-Quantum-Utility",
      "scope": "4 December 2023 release: initial Yorktown system, Heron processor, System Two infrastructure and Qiskit Patterns sections inspected. Roadmap targets excluded; announced software workflow separated from evidence of specific job execution.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Primary document retrieval; selected cited sections inspected",
        "sections": "4 December 2023 release: initial Yorktown system, Heron processor, System Two infrastructure and Qiskit Patterns sections inspected. Roadmap targets excluded; announced software workflow separated from evidence of specific job execution.",
        "limitations": "Original interpretive diagram, not a netlist or full equipment specification."
      }
    },
    {
      "id": "seed-ibm-2023-letter",
      "title": "The 2023 IBM Research annual letter",
      "author": "IBM Research",
      "year": 2024,
      "url": "https://research.ibm.com/blog/research-annual-letter-2023",
      "scope": "2 February 2024 retrospective; New quantum processors, IBM Quantum System Two and Utility-scale software sections inspected. Explicitly states initial three-Heron configuration communicates classically to parallelize circuits.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Primary document retrieval; selected cited sections inspected",
        "sections": "2 February 2024 retrospective; New quantum processors, IBM Quantum System Two and Utility-scale software sections inspected. Explicitly states initial three-Heron configuration communicates classically to parallelize circuits.",
        "limitations": "Original interpretive diagram, not a netlist or full equipment specification."
      }
    },
    {
      "id": "alt-truenorth",
      "title": "A million spiking-neuron integrated circuit with a scalable communication network and interface",
      "author": "P. A. Merolla et al.",
      "year": 2014,
      "url": "https://nimam4.github.io/IBM_TrueNorth.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Science 345, pp. 668–673; Fig. 2G–J and pp. 669–671: core, scheduler, routing, memory, offline mapping. Author-hosted scan inspected.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Science 345, pp. 668–673; Fig. 2G–J and pp. 669–671: core, scheduler, routing, memory, offline mapping. Author-hosted scan inspected.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-northpole",
      "title": "A new chip architecture points to faster, more energy-efficient AI",
      "author": "IBM Research",
      "year": 2023,
      "url": "https://research.ibm.com/blog/northpole-ibm-ai-chip",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "19 October 2023; architecture and scope paragraphs: 256 cores, local memory, active-memory interface, PCIe card, scale-out, inference-only boundary.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "19 October 2023; architecture and scope paragraphs: 256 cores, local memory, active-memory interface, PCIe card, scale-out, inference-only boundary.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-northpole-paper",
      "title": "Neural inference at the frontier of energy, space, and time",
      "author": "D. S. Modha et al.",
      "year": 2023,
      "url": "https://research.ibm.com/publications/neural-inference-at-the-frontier-of-energy-space-and-time",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Science paper abstract on author institution site inspected; low-precision spatial inference and on-chip compute/memory. Full article not inspected.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Science paper abstract on author institution site inspected; low-precision spatial inference and on-chip compute/memory. Full article not inspected.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-spinnaker",
      "title": "sPyNNaker: A Software Package for Running PyNN Simulations on SpiNNaker",
      "author": "O. Rhodes et al.",
      "year": 2018,
      "url": "https://pmc.ncbi.nlm.nih.gov/articles/PMC6257411/",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Sections 2.1, 3 and Fig. 1: ARM cores, TCM, SDRAM, DMA, event callbacks, host mapping. Full-text primary developer paper inspected.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Sections 2.1, 3 and Fig. 1: ARM cores, TCM, SDRAM, DMA, event callbacks, host mapping. Full-text primary developer paper inspected.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-spinnaker2",
      "title": "The SpiNNaker2 chip: a many-core platform for flexible and scalable brain-inspired computing",
      "author": "S. Scholze et al.",
      "year": 2026,
      "url": "https://arxiv.org/html/2607.24396v1",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "27 July 2026 preprint; §§3.1–3.2.6, Figs. 2–5 and supplement event router: 152 PEs, DNoC/CNoC, MLA, LPDDR4, event links. Architecture sections inspected.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "27 July 2026 preprint; §§3.1–3.2.6, Figs. 2–5 and supplement event router: 152 PEs, DNoC/CNoC, MLA, LPDDR4, event links. Architecture sections inspected.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-brainscales1",
      "title": "Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System",
      "author": "S. Schmitt et al.",
      "year": 2017,
      "url": "https://arxiv.org/html/1703.01909v1",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Sections II-A–C and III-C; wafer module, HICANN arrays, host control/calibration, external FPGA communication, hardware-in-the-loop training.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Sections II-A–C and III-C; wafer module, HICANN arrays, host control/calibration, external FPGA communication, hardware-in-the-loop training.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-brainscales2",
      "title": "The BrainScaleS-2 accelerated neuromorphic system with hybrid plasticity",
      "author": "C. Pehle et al.",
      "year": 2022,
      "url": "https://arxiv.org/html/2201.11063v1",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "§§II.1–II.3 and Fig. 1 inspected: 512 neuron circuits, quadrant synaptic arrays, PPU/SIMD control, CADC traces, event router and FPGA support.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "§§II.1–II.3 and Fig. 1 inspected: 512 neuron circuits, quadrant synaptic arrays, PPU/SIMD control, CADC traces, event router and FPGA support.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-neurogrid",
      "title": "Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations",
      "author": "B. V. Benjamin et al.",
      "year": 2014,
      "url": "https://web.stanford.edu/group/brainsinsilicon/documents/BenjaminEtAlNeurogrid2014.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Sections III–V, Figs. 4–6 inspected: software/HAL, USB, CPLD, daughterboard branching, 16 Neurocores, binary-tree routing, analog neuron and synapse populations.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Sections III–V, Figs. 4–6 inspected: software/HAL, USB, CPLD, daughterboard branching, 16 Neurocores, binary-tree routing, analog neuron and synapse populations.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-dynapse",
      "title": "A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors",
      "author": "S. Moradi, N. Qiao, F. Stefanini, G. Indiveri",
      "year": 2017,
      "url": "https://arxiv.org/html/1708.04198v2",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "§§III–V, Figs. 4–9 inspected: four-core prototype, R1/R2/R3 routing, source SRAM/destination CAM, pulse processing, DPI synapses and adaptive I&F neuron.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "§§III–V, Figs. 4–9 inspected: four-core prototype, R1/R2/R3 routing, source SRAM/destination CAM, pulse processing, DPI synapses and adaptive I&F neuron.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-tianjic",
      "title": "Towards artificial general intelligence with hybrid Tianjic chip architecture",
      "author": "J. Pei et al.",
      "year": 2019,
      "url": "https://bpb-us-w1.wpmucdn.com/sites.usc.edu/dist/0/597/files/2020/12/Pei-ArtificialGeneralIntelligenceChip-Nature19.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Nature 572, pp. 106–111; Fig. 2 and Extended Data Fig. 1; Methods on shared dendrites, configurable axons/somas and unified routing inspected.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Nature 572, pp. 106–111; Fig. 2 and Extended Data Fig. 1; Methods on shared dendrites, configurable axons/somas and unified routing inspected.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-pohoiki",
      "title": "Neuromorphic Nearest-Neighbor Search Using Intel’s Pohoiki Springs",
      "author": "M. Davies et al. / Intel",
      "year": 2020,
      "url": "https://arxiv.org/html/2004.12691v1",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "§II and Fig. 1 give the 768-chip, 24-Nahuku, 12×64 mesh system, three Arria/ARM hosts, Ethernet switch, x86 super host; §§III–V describe the search mapping.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "§II and Fig. 1 give the 768-chip, 24-Nahuku, 12×64 mesh system, three Arria/ARM hosts, Ethernet switch, x86 super host; §§III–V describe the search mapping.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-memristor-perceptron",
      "title": "Training and Operation of an Integrated Neuromorphic Network Based on Metal-Oxide Memristors",
      "author": "M. Prezioso et al.",
      "year": 2014,
      "url": "https://arxiv.org/pdf/1412.0611",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "December 2014 author manuscript, published Nature 2015; Pattern Classification Experiment and Figs. 2–3 inspected: 10×6 subarray, differential weights, external sensing/activation, Manhattan training.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "December 2014 author manuscript, published Nature 2015; Pattern Classification Experiment and Figs. 2–3 inspected: 10×6 subarray, differential weights, external sensing/activation, Manhattan training.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-photonic-reservoir",
      "title": "Optoelectronic Reservoir Computing",
      "author": "Y. Paquot et al.",
      "year": 2011,
      "url": "https://arxiv.org/pdf/1111.7219",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "November 2011 manuscript, Scientific Reports 2012; §II.B–C, Fig. 1 and supplement inspected: masked input, MZ nonlinearity, fiber delay, photodiode feedback and offline readout.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "November 2011 manuscript, Scientific Reports 2012; §II.B–C, Fig. 1 and supplement inspected: masked input, MZ nonlinearity, fiber delay, photodiode feedback and offline readout.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-lighton-opu",
      "title": "LightOn Optical Processing Unit: Scaling-up AI and HPC with a Non von Neumann co-processor",
      "author": "C. Brossollet et al. / LightOn",
      "year": 2021,
      "url": "https://arxiv.org/html/2107.11814v1",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Sections II–III and Fig. 1 inspected: fixed scattering matrix, optical nonlinearity, laser/modulators/detectors, FPGA I/O, PCIe appliance and Python pipeline.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Sections II–III and Fig. 1 inspected: fixed scattering matrix, optical nonlinearity, laser/modulators/detectors, FPGA I/O, PCIe appliance and Python pipeline.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-universal-linear-optics",
      "title": "Universal linear optics",
      "author": "J. Carolan et al.",
      "year": 2015,
      "url": "https://jacquescarolan.github.io/publication/carolan-2015-universal/carolan-2015-universal.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Science 349, pp. 711–716, Fig. 1 and main device description inspected: six-mode cascade, SPDC input, phase control, coupling and 12-detector readout.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Science 349, pp. 711–716, Fig. 1 and main device description inspected: six-mode cascade, SPDC input, phase control, coupling and 12-detector readout.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-envise-announcement",
      "title": "Introducing Envise, Idiom and Passage — Next Generation AI Compute, Compile and Interconnect Platforms",
      "author": "Nicholas Harris / Lightmatter",
      "year": 2021,
      "url": "https://medium.com/lightmatter/introducing-envise-idiom-and-passage-next-generation-ai-compute-compile-and-interconnect-331878d6cea5",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "10 March 2021 founder announcement inspected: proposed 4U blade, 16 Envise chips, DDR4/SSD, scale-out interconnect, Idiom compilation and deployment. This is announcement evidence, not independent delivery verification.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "10 March 2021 founder announcement inspected: proposed 4U blade, 16 Envise chips, DDR4/SSD, scale-out interconnect, Idiom compilation and deployment. This is announcement evidence, not independent delivery verification.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-pace-2025",
      "title": "An integrated large-scale photonic accelerator with ultralow latency",
      "author": "S. Hua et al. / Lightelligence",
      "year": 2025,
      "url": "https://d-nb.info/1370053967/34",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Nature 640, pp. 361–367; pp. 362–364 and Figs. 1–2 inspected from primary PDF cached privately. SHA256 1c0b44ceeb79ad1a46d9855f23e0d77c21afcf534cfb3366f81c2f36a94626ab. PIC/EIC, SRAM, SPI/SOM, modulation, detection and threshold feedback.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Nature 640, pp. 361–367; pp. 362–364 and Figs. 1–2 inspected from primary PDF cached privately. SHA256 1c0b44ceeb79ad1a46d9855f23e0d77c21afcf534cfb3366f81c2f36a94626ab. PIC/EIC, SRAM, SPI/SOM, modulation, detection and threshold feedback.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-photonic-tensor",
      "title": "Parallel convolution processing using an integrated photonic tensor core",
      "author": "J. Feldmann et al.",
      "year": 2020,
      "url": "https://arxiv.org/pdf/2002.00281",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "2020 author manuscript, Nature publication 2021; photonic tensor-core section and Figs. 1–2 inspected: microcomb, WDM inputs, GST attenuation, directional-coupler fan-out/accumulation and detector outputs.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "2020 author manuscript, Nature publication 2021; photonic tensor-core section and Figs. 1–2 inspected: microcomb, WDM inputs, GST attenuation, directional-coupler fan-out/accumulation and detector outputs.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-ntt-cim",
      "title": "Coherent Ising Machine for Combinatorial Optimization Problems",
      "author": "T. Inagaki, K. Inaba, T. Honjo, H. Takesue / NTT",
      "year": 2016,
      "url": "https://www.rd.ntt/e/brl/result/activities/file/report16/report19E.html",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Primary laboratory report and Fig. 1 inspected; 2,048-node time-multiplexed DOPO system, homodyne measurement, FPGA feedback, optical injection and graph configuration.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Primary laboratory report and Fig. 1 inspected; 2,048-node time-multiplexed DOPO system, homodyne measurement, FPGA feedback, optical injection and graph configuration.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-bennett1973",
      "title": "Logical Reversibility of Computation",
      "author": "Charles H. Bennett",
      "year": 1973,
      "url": "https://worrydream.com/refs/Bennett_1973_-_Logical_Reversibility_of_Computation.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "IBM J. Res. Develop. 17, pp. 525–532; reversible Turing-machine theorem, Table 1 and proof inspected. Three tapes and compute/copy/retrace construction; this is a formal model.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "IBM J. Res. Develop. 17, pp. 525–532; reversible Turing-machine theorem, Table 1 and proof inspected. Three tapes and compute/copy/retrace construction; this is a formal model.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-billiard",
      "title": "Conservative Logic",
      "author": "Edward Fredkin and Tommaso Toffoli",
      "year": 1982,
      "url": "https://gwern.net/doc/cs/hardware/1982-fredkin.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "International Journal of Theoretical Physics 21, pp. 219–253; §§6.1–6.4, Figs. 12–18 inspected: elastic-ball encoding, interaction gate, mirrors, timing/crossover and Fredkin gate construction.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "International Journal of Theoretical Physics 21, pp. 219–253; §§6.1–6.4, Figs. 12–18 inspected: elastic-ball encoding, interaction gate, mirrors, timing/crossover and Fredkin gate construction.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-ibm-one",
      "title": "IBM Unveils World’s First Integrated Quantum Computing System for Commercial Use",
      "author": "IBM",
      "year": 2019,
      "url": "https://uk.newsroom.ibm.com/ibm-unveils-worlds-first-integrated-quantum-computing-system-for-commercial-use",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "8 January 2019 announcement; component list and Designing a First section inspected. System integration only; CES display was a replica.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "8 January 2019 announcement; component list and Designing a First section inspected. System integration only; CES display was a replica.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-ibm-one-ghz",
      "title": "Verifying Multipartite Entangled GHZ States via Multiple Quantum Coherences",
      "author": "K. X. Wei et al.",
      "year": 2019,
      "url": "https://arxiv.org/html/1905.05720v1",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "2019 manuscript; main text, Figs. 1–2 and Readout Calibration supplement inspected. The HTML rendering displays a spurious later date; submission/version date is 14 May 2019.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "2019 manuscript; main text, Figs. 1–2 and Readout Calibration supplement inspected. The HTML rendering displays a spurious later date; submission/version date is 14 May 2019.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-sycamore",
      "title": "Quantum supremacy using a programmable superconducting processor",
      "author": "F. Arute et al.",
      "year": 2019,
      "url": "https://cs.fit.edu/~dmitra/Algorithms/QuantumComp-Google-Nature2019.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Nature 574, pp. 505–510; Building a high-fidelity processor, Figs. 1–3 and readout paragraphs inspected in institutional PDF copy.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Nature 574, pp. 505–510; Building a high-fidelity processor, Figs. 1–3 and readout paragraphs inspected in institutional PDF copy.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-willow-qec",
      "title": "Quantum error correction below the surface code threshold",
      "author": "R. Acharya et al. / Google Quantum AI",
      "year": 2024,
      "url": "https://arxiv.org/html/2408.13687v1",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "24 August 2024 manuscript; §§II and V, Fig. 1 and decoding discussion inspected. Explicitly distinguishes 105-qubit distance-7 offline decoding from 72-qubit distance-5 real-time decoding.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "24 August 2024 manuscript; §§II and V, Fig. 1 and decoding discussion inspected. Explicitly distinguishes 105-qubit distance-7 offline decoding from 72-qubit distance-5 real-time decoding.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-willow-name",
      "title": "Meet Willow, our state-of-the-art quantum chip",
      "author": "H. Neven / Google Quantum AI",
      "year": 2024,
      "url": "https://blog.google/innovation-and-ai/technology/research/google-willow-quantum-chip/",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "9 December 2024 announcement, Exponential quantum error correction and State-of-the-art performance sections inspected to connect the Willow name and 105-qubit chip.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "9 December 2024 announcement, Exponential quantum error correction and State-of-the-art performance sections inspected to connect the Willow name and 105-qubit chip.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-ionq-forte",
      "title": "IonQ Forte: The First Software-Configurable Quantum Computer",
      "author": "IonQ Staff",
      "year": 2023,
      "url": "https://www.ionq.com/resources/ionq-forte-first-configurable-quantum-computer",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "3 March 2023 page; Software-Configurable Quantum Computer, AOD Technology and First Configuration sections, Figs. 2–4 inspected. Manufacturer characterization, not independent validation.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "3 March 2023 page; Software-Configurable Quantum Computer, AOD Technology and First Configuration sections, Figs. 2–4 inspected. Manufacturer characterization, not independent validation.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-quantinuum-h2",
      "title": "A Race Track Trapped-Ion Quantum Processor",
      "author": "S. A. Moses et al.",
      "year": 2023,
      "url": "https://arxiv.org/html/2305.03828v1",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "5 May 2023 manuscript; §§II.1–II.6, Figs. 1–2 and repetition-code scope inspected. Only four DG zones perform quantum operations in this configuration.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "5 May 2023 manuscript; §§II.1–II.6, Figs. 1–2 and repetition-code scope inspected. Only four DG zones perform quantum operations in this configuration.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-atom-phoenix",
      "title": "Assembly and coherent control of a register of nuclear spin qubits",
      "author": "K. Barnes et al. / Atom Computing",
      "year": 2021,
      "url": "https://arxiv.org/html/2108.04790v1",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "10 August 2021 manuscript; Fig. 1, register assembly, shelving readout and site-selective manipulation inspected. Phoenix has 21 computational qubits in this experiment; large loading images are not the computational count.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "10 August 2021 manuscript; Fig. 1, register assembly, shelving readout and site-selective manipulation inspected. Phoenix has 21 computational qubits in this experiment; large loading images are not the computational count.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-aspen-announcement",
      "title": "Rigetti Computing Announces Commercial Availability of 80-Qubit Aspen-M System",
      "author": "Rigetti",
      "year": 2022,
      "url": "https://investors.rigetti.com/news-releases/news-release-details/rigetti-computing-announces-commercial-availability-80-qubit",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "15 February 2022 release inspected; commercial Aspen-M availability and two-chip architecture. Performance claims are manufacturer reports.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "15 February 2022 release inspected; commercial Aspen-M availability and two-chip architecture. Performance claims are manufacturer reports.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-rigetti-stack",
      "title": "Building scalable, innovative quantum systems",
      "author": "Rigetti",
      "year": 2026,
      "url": "https://www.rigetti.com/what-we-build",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Technology Stack, Superconducting Quantum Processors, Control Systems and historical Aspen-M-1 table inspected 1 November 2026. General stack descriptions do not establish an Aspen-specific cable or resonator netlist.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Technology Stack, Superconducting Quantum Processors, Control Systems and historical Aspen-M-1 table inspected 1 November 2026. General stack descriptions do not establish an Aspen-specific cable or resonator netlist.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-quantinuum-h1",
      "title": "With 20 Qubits, the H1-1 Quantum Runs More Complex Algorithm",
      "author": "Quantinuum / Brian Neyenhuis",
      "year": 2022,
      "url": "https://www.quantinuum.com/blog/with-20-qubits-the-h1-1-quantum-runs-more-complex-algorithm",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "14 June 2022 technical interview; upgrade, five-zone optics, ion transport, compiler and mid-circuit measurement paragraphs inspected.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "14 June 2022 technical interview; upgrade, five-zone optics, ion transport, compiler and mid-circuit measurement paragraphs inspected.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-aquila",
      "title": "Aquila: QuEra’s 256-qubit neutral-atom quantum computer",
      "author": "J. Wurtz et al. / QuEra",
      "year": 2023,
      "url": "https://arxiv.org/pdf/2306.11727",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Version 1.0, 20 June 2023; §§1.2–1.3, Figs. 1.1–1.5 and §6 inspected. Published example data taken 9 June 2023.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Version 1.0, 20 June 2023; §§1.2–1.3, Figs. 1.1–1.5 and §6 inspected. Published example data taken 9 June 2023.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-pasqal-orion",
      "title": "Pasqal Cloud Services: Orion Alpha QPU specifications",
      "author": "Pasqal",
      "year": 2025,
      "url": "https://www.pasqal.com/wp-content/uploads/2025/06/Pasqal_Cloud_Brochure.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "2025 cloud brochure, pp. 4, 9 and 25 inspected; Orion Alpha (formerly Fresnel), analog operation, cloud limits and pulse specifications.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "2025 cloud brochure, pp. 4, 9 and 25 inspected; Orion Alpha (formerly Fresnel), analog operation, cloud limits and pulse specifications.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-pulser",
      "title": "Pulser: An open-source package for the design of pulse sequences in programmable neutral-atom arrays",
      "author": "H. Silvério et al.",
      "year": 2022,
      "url": "https://arxiv.org/pdf/2104.15044",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Published Quantum 2022; §§2.1–2.4 and 3.1, Fig. 5 inspected. General Pasqal pulse/register model; digital-gate examples are not transferred to Orion Alpha analog hardware.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Published Quantum 2022; §§2.1–2.4 and 3.1, Fig. 5 inspected. General Pasqal pulse/register model; digital-gate examples are not transferred to Orion Alpha analog hardware.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-dwave-2021",
      "title": "The Advantage System: Performance Update",
      "author": "C. McGeoch and P. Farré / D-Wave",
      "year": 2021,
      "url": "https://www.dwavesys.com/media/kjtlcemb/14-1054a-a_advantage_system_performance_update.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "1 October 2021 technical report 14-1054A-A; §§2.1–3.2, Fig. 3 and p. 16 footnote 3 inspected. Distinguishes 2000Q LN and Advantage 4.1 from ideal graph capacity.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "1 October 2021 technical report 14-1054A-A; §§2.1–3.2, Fig. 3 and p. 16 footnote 3 inspected. Distinguishes 2000Q LN and Advantage 4.1 from ideal graph capacity.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-dwave-topology",
      "title": "Topologies",
      "author": "D-Wave documentation",
      "year": 2026,
      "url": "https://docs.dwavequantum.com/en/latest/quantum_research/topologies.html",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Chimera unit cells/structure and Pegasus coupler sections inspected 1 November 2026; graph definitions, not an operational yield certificate.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Chimera unit cells/structure and Pegasus coupler sections inspected 1 November 2026; graph definitions, not an operational yield certificate.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-dwave-workflow",
      "title": "Practical Quantum Computing: An Update",
      "author": "D-Wave",
      "year": 2020,
      "url": "https://www.dwavesys.com/media/doaarwgt/14-1047a-a_practical_quantum_computing_an_update.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "25 September 2020 whitepaper 14-1047A-A; §§2.1–2.3 and Figs. 3–4 inspected: Ising/QUBO translation, embedding, QMI and returned samples.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "25 September 2020 whitepaper 14-1047A-A; §§2.1–2.3 and Figs. 3–4 inspected: Ising/QUBO translation, embedding, QMI and returned samples.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-dwave-anneal",
      "title": "Annealing Implementation and Controls",
      "author": "D-Wave documentation",
      "year": 2026,
      "url": "https://docs.dwavequantum.com/en/latest/quantum_research/annealing.html",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "QA Implementation section and Hamiltonian equation inspected 1 November 2026; on-QPU DACs, h/J controls and A(s)/B(s) evolution. Optional newer controls are not asserted for older QPUs.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "QA Implementation section and Hamiltonian equation inspected 1 November 2026; on-QPU DACs, h/J controls and A(s)/B(s) evolution. Optional newer controls are not asserted for older QPUs.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-borealis",
      "title": "Quantum computational advantage with a programmable photonic processor",
      "author": "L. S. Madsen et al.",
      "year": 2022,
      "url": "https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=933674",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Nature 606 pp. 75–81 plus Methods; Experiment section and Fig. 1 inspected in NIST-hosted publication copy.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Nature 606 pp. 75–81 plus Methods; Experiment section and Fig. 1 inspected in NIST-hosted publication copy.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-jiuzhang",
      "title": "Quantum computational advantage using photons",
      "author": "H.-S. Zhong et al.",
      "year": 2020,
      "url": "https://arxiv.org/pdf/2012.01625v1",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Submitted version; source-design and phase-locking main text plus Figs. 1–4 inspected. Full 80-page separate supplement not inspected.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Submitted version; source-design and phase-locking main text plus Figs. 1–4 inspected. Full 80-page separate supplement not inspected.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-zuchongzhi",
      "title": "Strong quantum computational advantage using a superconducting quantum processor",
      "author": "Y. Wu et al.",
      "year": 2021,
      "url": "https://arxiv.org/pdf/2106.14734",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "June 2021 manuscript; §II and Fig. 1 inspected: 66 qubits, 110 couplers, flip-chip control/readout die, Purcell-filter groups and 56-qubit sampling subset.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "June 2021 manuscript; §II and Fig. 1 inspected: 66 qubits, 110 couplers, flip-chip control/readout die, Purcell-filter groups and 56-qubit sampling subset.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-silicon-six",
      "title": "Universal control of a six-qubit quantum processor in silicon",
      "author": "S. G. J. Philips et al.",
      "year": 2022,
      "url": "https://arxiv.org/html/2202.09252v1",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Main text, Figs. 1–4, Methods control/setup and parity readout sections inspected. Six-spin linear 28Si/SiGe device with conditional initialization and nearest-neighbor exchange.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Main text, Figs. 1–4, Methods control/setup and parity readout sections inspected. Six-spin linear 28Si/SiGe device with conditional initialization and nearest-neighbor exchange.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-kitaev",
      "title": "Fault-tolerant quantum computation by anyons",
      "author": "A. Yu. Kitaev",
      "year": 1997,
      "url": "https://arxiv.org/pdf/quant-ph/9707021",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "1997 preprint, later Annals of Physics publication 2003; introduction, §§1 and 7 inspected. PDF contains a regenerated date; version submission is 9 July 1997.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "1997 preprint, later Annals of Physics publication 2003; introduction, §§1 and 7 inspected. PDF contains a regenerated date; version submission is 9 July 1997.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-eai231rv",
      "title": "Information Manual for the EAI 231R-V Analog Computing System",
      "author": "Electronic Associates, Inc.",
      "year": 1964,
      "url": "https://bitsavers.org/pdf/eai/16-231R-V/Information_Manual_for_the_EAI_231R-V_Analog_Computing_System_Aug64.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "August 1964 manual; pp. 6–8, 13–17, 21–24 inspected from private cached PDF. Preface excludes operating/performance specifications. SHA256 4a7724a63dbe112aaef7f5a16ede4e9d7fb04917192cf7e2cdcd368cab30b7c5.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "August 1964 manual; pp. 6–8, 13–17, 21–24 inspected from private cached PDF. Preface excludes operating/performance specifications. SHA256 4a7724a63dbe112aaef7f5a16ede4e9d7fb04917192cf7e2cdcd368cab30b7c5.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-eai680",
      "title": "680 Scientific Computing System Reference Handbook",
      "author": "Electronic Associates, Inc.",
      "year": 1966,
      "url": "https://www.analogmuseum.org/library/eai_680_ref_handbook_small.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "October 1966 publication 00 800.2048-0; chapters 2–6, 11, 13 and 20 excerpts inspected in cached primary scan. Standard configurations may differ by customer, as manual notice states. SHA256 a29228e67a96cb2e2f5c63bda96f8cdfb47d1b120c1ffc81c02d46e691a22874.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "October 1966 publication 00 800.2048-0; chapters 2–6, 11, 13 and 20 excerpts inspected in cached primary scan. Standard configurations may differ by customer, as manual notice states. SHA256 a29228e67a96cb2e2f5c63bda96f8cdfb47d1b120c1ffc81c02d46e691a22874.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-heath-ec1",
      "title": "Operational Manual for the Heath Educational Analog Computer Model EC-1",
      "author": "Heath Company",
      "year": 1965,
      "url": "https://archive.computerhistory.org/resources/access/text/2009/09/102649920.05.01.acc.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Manual dated 14 May 1965; printed pp. 13, 15–16, 24–25, 32 visually inspected from rendered scan. No extractable OCR text. SHA256 ce1c6a98c2c1b223795caa44de17cf26c9bdd563979345ae11ed05e798a7dcc7.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Manual dated 14 May 1965; printed pp. 13, 15–16, 24–25, 32 visually inspected from rendered scan. No extractable OCR text. SHA256 ce1c6a98c2c1b223795caa44de17cf26c9bdd563979345ae11ed05e798a7dcc7.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-rockefeller-kopal",
      "title": "Nonradial Oscillations of the Standard Model",
      "author": "Z. Kopal",
      "year": 1949,
      "url": "https://adsabs.harvard.edu/pdf/1949ApJ...109..509K",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Astrophysical Journal 109 pp. 509–527; §II pp. 514–517 and Fig. 1 inspected, including rendered setup diagram. Exact nine-integrator application on the 18-integrator Rockefeller analyzer; not its full electromechanical control schematic.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Astrophysical Journal 109 pp. 509–527; §II pp. 514–517 and Fig. 1 inspected, including rendered setup diagram. Exact nine-integrator application on the 18-integrator Rockefeller analyzer; not its full electromechanical control schematic.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-pace-tr10",
      "title": "PACE TR-10 Analog Computer",
      "author": "Electronic Associates, Inc.",
      "year": null,
      "url": "https://www.analogmuseum.org/library/eai_tr-10.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Undated manufacturer brochure; printed pp. 2, 4 and 6 and final page visually inspected from rendered primary scan. Brochure date not verified. SHA256 480580ad6ef5504a0cd32223d85af71070c4cb92036f8d93f33b4f82a75bee4b.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Undated manufacturer brochure; printed pp. 2, 4 and 6 and final page visually inspected from rendered primary scan. Brochure date not verified. SHA256 480580ad6ef5504a0cd32223d85af71070c4cb92036f8d93f33b4f82a75bee4b.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-hydac2400",
      "title": "Seminar on Hybrid Computation as Applied to the Aerospace Field",
      "author": "Electronic Associates, Inc.",
      "year": 1964,
      "url": "https://bitsavers.org/pdf/eai/Seminar_on_Hybrid_Computation_as_applied_to_the_Aerospace_Field_1964.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "1964 seminar; chapter 2 §IV pp. 24–27 and Fig. 11, chapter 3 partitioning and chapter 5 software status inspected in cached scan. SHA256 7f5452f7ea60e7f91a1471fb0c2a6b2f54e3d1b59d5015446e731e4804d73026.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "1964 seminar; chapter 2 §IV pp. 24–27 and Fig. 11, chapter 3 partitioning and chapter 5 software status inspected in cached scan. SHA256 7f5452f7ea60e7f91a1471fb0c2a6b2f54e3d1b59d5015446e731e4804d73026.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-phillips1950",
      "title": "Mechanical Models in Economic Dynamics",
      "author": "A. W. Phillips",
      "year": 1950,
      "url": "https://www.econ.puc-rio.br/mgarcia/outrosmatmacroII_arquivos/Mechanical%20Models%20in%20Economic%20Dynamics.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Economica 17 pp. 283–305; printed pp. 283, 287, 290–292 and Fig. 3 visually inspected from primary scan. No source image republished. SHA256 9f4d154b3d926cddd2edc9d4d4c7378d0b6691cab0a022ddc59c0bb3d40f1984.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Economica 17 pp. 283–305; printed pp. 283, 287, 290–292 and Fig. 3 visually inspected from primary scan. No source image republished. SHA256 9f4d154b3d926cddd2edc9d4d4c7378d0b6691cab0a022ddc59c0bb3d40f1984.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-lukyanov-museum",
      "title": "Водяные вычислительные машины [Water Computing Machines]",
      "author": "O. Solovyova / Polytechnic Museum collection account",
      "year": 2000,
      "url": "https://www.nkj.ru/archive/articles/7033/",
      "type": "Museum collection technical account",
      "accessed": "2026-11-01",
      "scope": "Nauka i Zhizn no. 4 (2000), abridged museum collection article; apparatus, four-step setup, run/readout and detailed illustration description inspected in Russian. Custodial technical account, not the original designer manual; no performance claims imported.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Nauka i Zhizn no. 4 (2000), abridged museum collection article; apparatus, four-step setup, run/readout and detailed illustration description inspected in Russian. Custodial technical account, not the original designer manual; no performance claims imported.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-an231e04",
      "title": "AN231E04 Datasheet Revision 1.5",
      "author": "Anadigm",
      "year": 2021,
      "url": "https://static6.arrow.com/aropdfconversion/adf76f1039541d600d359bc514b557f129b30245/ds231000-u001.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "DS231000-U001i, copyright 2007/2021; pp. 2–4 and Fig. 1 inspected, including rendered architecture diagram, in distributor-hosted primary PDF. SHA256 54a11602660bf00988521f7df5179ee99d09514fa8445d5c6ad0ec12a0417c99.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "DS231000-U001i, copyright 2007/2021; pp. 2–4 and Fig. 1 inspected, including rendered architecture diagram, in distributor-hosted primary PDF. SHA256 54a11602660bf00988521f7df5179ee99d09514fa8445d5c6ad0ec12a0417c99.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-wang-oim",
      "title": "OIM: Oscillator-Based Ising Machines for Solving Combinatorial Optimisation Problems",
      "author": "T. Wang and J. Roychowdhury",
      "year": 2019,
      "url": "https://jaijeet.github.io/research/PDFs/2019-06--UCNC-LNCS-Wang-Roychowdhury-chapter-on-OIM.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "§4.1, Figs. 8–9 and SHIL discussion inspected. The 32-oscillator hardware, eight-node demonstration and larger numerical simulations are explicitly separate.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "§4.1, Figs. 8–9 and SHIL discussion inspected. The 32-oscillator hardware, eight-node demonstration and larger numerical simulations are explicitly separate.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-phonon-magnon",
      "title": "On-chip phonon-magnon reservoir for neuromorphic computing",
      "author": "D. D. Yaremkevich et al.",
      "year": 2023,
      "url": "https://www.nature.com/articles/s41467-023-43891-y",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Results, Figs. 1–3, Summary and Methods optical writing/reading inspected. Acoustic reservoir has optical transduction and PC-based ANN readout; nonlinear contribution is only indirect in this experiment.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Results, Figs. 1–3, Summary and Methods optical writing/reading inspected. Acoustic reservoir has optical transduction and PC-based ANN readout; nonlinear contribution is only indirect in this experiment.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-chemical-wave-gates",
      "title": "Chemical Wave Logic Gates",
      "author": "O. Steinbock, P. Kettunen and K. Showalter",
      "year": 1996,
      "url": "https://www.chem.fsu.edu/~steinbock/papers/jpc96a.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "J. Phys. Chem. 100 pp. 18970–18975; Experimental Procedures, Experimental Results and Figs. 1–5 inspected. Cascaded circuitry in Modeling Results is numerical, not transferred to built gate claims.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "J. Phys. Chem. 100 pp. 18970–18975; Experimental Procedures, Experimental Results and Figs. 1–5 inspected. Cascaded circuitry in Modeling Results is numerical, not transferred to built gate claims.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-benenson-2001",
      "title": "Programmable and autonomous computing machine made of biomolecules: laboratory technical explanation",
      "author": "Y. Benenson et al. / Weizmann Institute",
      "year": 2001,
      "url": "https://www.wisdom.weizmann.ac.il/~lbn/new_pages/Biological_nano.html",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Laboratory account of Nature 414 pp. 430–434; paragraphs on hardware, sticky ends, hybridization, cleavage and output display inspected. Original Nature full article not retrieved; performance/solution-volume claims on this legacy HTML page are excluded.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Laboratory account of Nature 414 pp. 430–434; paragraphs on hardware, sticky ends, hybridization, cleavage and output display inspected. Original Nature full article not retrieved; performance/solution-volume claims on this legacy HTML page are excluded.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-seesaw-2011",
      "title": "Scaling Up Digital Circuit Computation with DNA Strand Displacement Cascades",
      "author": "L. Qian and E. Winfree",
      "year": 2011,
      "url": "https://www.dna.caltech.edu/~lulu/seesaw_digital_circuits2011.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Science 332 pp. 1196–1201; Figs. 1–4, especially Fig. 4 square-root circuit and dual-rail discussion inspected. Original factual graph; no article text or figure reproduced.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Science 332 pp. 1196–1201; Figs. 1–4, especially Fig. 4 square-root circuit and dual-rail discussion inspected. Original factual graph; no article text or figure reproduced.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-dna-sierpinski",
      "title": "Algorithmic Self-Assembly of DNA Sierpinski Triangles",
      "author": "P. W. K. Rothemund, N. Papadakis and E. Winfree",
      "year": 2004,
      "url": "https://journals.plos.org/plosbiology/article?id=10.1371/journal.pbio.0020424",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Full primary article inspected: Figs. 1, 4A, 5; Molecular Implementation, Self-Assembly and Methods. DAE-E physical experiment separated from aTAM idealization and DAO-E alternative.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Full primary article inspected: Figs. 1, 4A, 5; Molecular Implementation, Self-Assembly and Methods. DAE-E physical experiment separated from aTAM idealization and DAO-E alternative.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-cello-2016",
      "title": "Genetic circuit design automation",
      "author": "A. A. K. Nielsen et al.",
      "year": 2016,
      "url": "https://search.iczhiku.com/paper/9pf43Li5PrxHTzJw.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Original Science 352 aac7341 paper privately cached (SHA256 3fb440209c20e11e0fafd7892e8dcea6f2711536d07b1d4d1514716a9b42d042); extracted PDF pp. 3–5 and 9, Figs. 1–4 inspected. Publisher copy hosted by a third party; original paper is the evidence.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Original Science 352 aac7341 paper privately cached (SHA256 3fb440209c20e11e0fafd7892e8dcea6f2711536d07b1d4d1514716a9b42d042); extracted PDF pp. 3–5 and 9, Figs. 1–4 inspected. Publisher copy hosted by a third party; original paper is the evidence.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-bacterial-xor",
      "title": "Robust multicellular computing using genetically encoded NOR gates and chemical wires: Supplementary Information",
      "author": "A. Tamsir, J. J. Tabor and C. A. Voigt",
      "year": 2011,
      "url": "https://media.springernature.com/original/springer-static/esm/art%3A10.1038%2Fnature09565/MediaObjects/41586_2011_BFnature09565_MOESM225_ESM.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Primary 19-page supplement opened and inspected: §§1.1–1.3 gate mechanism, §4 timing, §5 four-strain XOR assay, §6 and Supplementary Table 5 strain definitions; Supplementary Figs. 6, 11 and 12 readouts. Main paper HTML was subscription-limited; architecture is corroborated by this accessible primary supplement.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Primary 19-page supplement opened and inspected: §§1.1–1.3 gate mechanism, §4 timing, §5 four-strain XOR assay, §6 and Supplementary Table 5 strain definitions; Supplementary Figs. 6, 11 and 12 readouts. Main paper HTML was subscription-limited; architecture is corroborated by this accessible primary supplement.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-crn-compiler",
      "title": "DNA as a universal substrate for chemical kinetics",
      "author": "D. Soloveichik, G. Seelig and E. Winfree",
      "year": 2010,
      "url": "https://dna.caltech.edu/Papers/DNA_for_CRNs_2010_PNAS.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Primary PNAS paper inspected: Molecular Primitive, Implementing Networks, Unimolecular Reactions, Fig. 2, buffering/scaling and Figs. 5–6. Domain-level proposal and numerical demonstrations; no wet-lab realization reported here.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Primary PNAS paper inspected: Molecular Primitive, Implementing Networks, Unimolecular Reactions, Fig. 2, buffering/scaling and Figs. 5–6. Domain-level proposal and numerical demonstrations; no wet-lab realization reported here.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-marex-lite",
      "title": "MAREX: A general purpose hardware architecture for membrane computing",
      "author": "D. Cascado-Caballero et al.",
      "year": 2022,
      "url": "https://idus.us.es/server/api/core/bitstreams/3700df9c-c1c6-44ce-9ac1-e7f7b85a75cb/content",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Institutional manuscript PDF privately cached, SHA256 6982a2440eb55d9c6ad1e4a2a25a57b5f3fa71992df8cf1e23cffceaccaff1ae. §§4–5, 6.1, 6.3 and 7, Figs. 1–2, Table 3 inspected. Evidence describes synthesis and behavioral agreement, not independently measured hardware timing.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Institutional manuscript PDF privately cached, SHA256 6982a2440eb55d9c6ad1e4a2a25a57b5f3fa71992df8cf1e23cffceaccaff1ae. §§4–5, 6.1, 6.3 and 7, Figs. 1–2, Table 3 inspected. Evidence describes synthesis and behavioral agreement, not independently measured hardware timing.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-scald-multiplier",
      "title": "A True Single-Phase Energy-Recovery Multiplier",
      "author": "S. Kim, C. H. Ziesler and M. C. Papaefthymiou",
      "year": 2003,
      "url": "https://www.researchgate.net/publication/220525351_A_true_single-phase_energy-recovery_multiplier",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Author-uploaded original IEEE TVLSI 11 pp. 194–207, DOI 10.1109/TVLSI.2003.810795. Full-text §§II, IV, VII, Figs. 4–10 and 13–21 inspected. Article hosted on ResearchGate; no secondary description used.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Author-uploaded original IEEE TVLSI 11 pp. 194–207, DOI 10.1109/TVLSI.2003.810795. Full-text §§II, IV, VII, Figs. 4–10 and 13–21 inspected. Article hosted on ResearchGate; no secondary description used.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-rqfp-2014",
      "title": "Reversible logic gate using adiabatic superconducting devices",
      "author": "N. Takeuchi, Y. Yamanashi and N. Yoshikawa",
      "year": 2014,
      "url": "https://www.nature.com/articles/srep06354",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Scientific Reports 4, 6354; full Results, Fig. 1 gate construction, Fig. 2 experiments and Fig. 3 simulated energy inspected. Physical demonstrations at 4.2 K and 100 kHz; energy below the measurement threshold is a simulation result.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Scientific Reports 4, 6354; full Results, Fig. 1 gate construction, Fig. 2 experiments and Fig. 3 simulated energy inspected. Physical demonstrations at 4.2 K and 100 kHz; energy below the measurement threshold is a simulation result.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-magnetic-pbits-2019",
      "title": "Integer factorization using stochastic magnetic tunnel junctions",
      "author": "W. A. Borders et al.",
      "year": 2019,
      "url": "https://www.nature.com/articles/s41586-019-1557-9",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Public primary abstract and Extended Data Figs. 1–4, 6–10 captions inspected, including microcontroller/DAC loop. Main article body is subscription-limited; exact transistor-level p-bit schematic and full algorithm derivation not inspected.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Public primary abstract and Extended Data Figs. 1–4, 6–10 captions inspected, including microcontroller/DAC loop. Main article body is subscription-limited; exact transistor-level p-bit schematic and full algorithm derivation not inspected.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-stochastic-bayesian-fpga",
      "title": "Bayesian Inference implemented on FPGA with Stochastic Bitstreams for an Autonomous Robot",
      "author": "H. Fernandes et al.",
      "year": 2016,
      "url": "https://irep.ntu.ac.uk/id/eprint/33177/1/10582_Ferreira.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Primary FPL 2016 manuscript; §§II–IV, Figs. 1–3, Tables I–III inspected. Hardware implementation on Cyclone IV; power figures are vendor-tool estimates. Robot application model does not by itself establish a deployed closed-loop robot trial.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Primary FPL 2016 manuscript; §§II–IV, Figs. 1–3, Tables I–III inspected. Hardware implementation on Cyclone IV; power figures are vendor-tool estimates. Robot application model does not by itself establish a deployed closed-loop robot trial.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-bubble-logic",
      "title": "Microfluidic Bubble Logic",
      "author": "M. Prakash and N. Gershenfeld",
      "year": 2007,
      "url": "https://web.stanford.edu/group/prakash-lab/docs/Prakash_Science_2007.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Science 315 pp. 832–835; fluid medium and fabrication paragraphs; Fig. 1 AND/OR geometry, arrival window, Fig. 2 bistability and Fig. 3 interfaces inspected. Detailed graph limits itself to Fig. 1 top-row gate.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Science 315 pp. 832–835; fluid medium and fabrication paragraphs; Fig. 1 AND/OR geometry, arrival window, Fig. 2 bistability and Fig. 3 interfaces inspected. Detailed graph limits itself to Fig. 1 top-row gate.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-soft-pneumatic",
      "title": "Digital logic for soft devices",
      "author": "D. J. Preston et al.",
      "year": 2019,
      "url": "https://www.gmwgroup.harvard.edu/sites/g/files/omnuum10006/files/gmwgroup/files/1318.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "PNAS 116 pp. 7750–7759; Figs. 1–5 and Shift Register section inspected, including electronic pressure-regulator clock used in the experiment. Alternative autonomous clock sources are proposals, not transferred into this configuration.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "PNAS 116 pp. 7750–7759; Figs. 1–5 and Shift Register section inspected, including electronic pressure-regulator clock used in the experiment. Alternative autonomous clock sources are proposals, not transferred into this configuration.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-conductive-metamaterial",
      "title": "Digital logic gates in soft, conductive mechanical metamaterials",
      "author": "C. El Helou, P. R. Buskohl, C. E. Tabor and R. L. Harne",
      "year": 2021,
      "url": "https://bpb-us-e1.wpmucdn.com/sites.psu.edu/dist/1/118779/files/2021/04/El_Helou_digital_logic_gates_soft_conductive_mechanical_metamaterials.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Primary Nature Communications 12, 1633 author-hosted PDF plus supplement; Figs. 3–5 and Experimental characterization inspected. Manual mode selection and electronic readout explicitly retained.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Primary Nature Communications 12, 1633 author-hosted PDF plus supplement; Figs. 3–5 and Experimental characterization inspected. Manual mode selection and electronic readout explicitly retained.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-cam8",
      "title": "CAM-8: a computer architecture based on cellular automata",
      "author": "N. Margolus",
      "year": 1995,
      "url": "https://arxiv.org/pdf/comp-gas/9509001",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Report dated 15 December 1993, arXiv posted September 1995. §§2.1–2.2, Fig. 1 and §3.1/§3.4 inspected. Eight-module built prototype distinguished from indefinitely extensible architectural proposal.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Report dated 15 December 1993, arXiv posted September 1995. §§2.1–2.2, Fig. 1 and §3.1/§3.4 inspected. Eight-module built prototype distinguished from indefinitely extensible architectural proposal.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "alt-qca-1993",
      "title": "Quantum cellular automata",
      "author": "C. S. Lent, P. D. Tougaw, W. Porod and G. H. Bernstein",
      "year": 1993,
      "url": "https://academicweb.nd.edu/~lent/pdf/nd/Quantum_cellular_automata.pdf",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "scope": "Nanotechnology 4 pp. 49–57; §§2–5, Figs. 1, 4–8 inspected. Proposed five-dot/two-electron cells and self-consistent ground-state calculations, not a fabricated processor. Later four-dot clocked QCA not substituted.",
      "inspection": {
        "method": "Web retrieval of primary source",
        "sections": "Nanotechnology 4 pp. 49–57; §§2–5, Figs. 1, 4–8 inspected. Proposed five-dot/two-electron cells and self-consistent ground-state calculations, not a fabricated processor. Later four-dot clocked QCA not substituted.",
        "limitations": "Selected architecture sections inspected; no independent replication or performance certification."
      }
    },
    {
      "id": "gap-morello-trm",
      "title": "Arm Morello System Development Platform Technical Reference Manual, 102278_0001_04_en",
      "author": "Arm",
      "year": 2022,
      "url": "https://documentation-service.arm.com/static/62a735d731ea212bb6623405",
      "scope": "Issue 04; pp. 19, 30–36, Figures 3-1/3-2. Board/SoC hierarchy and alternative tag-storage implementations.",
      "type": "Primary technical publication",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Cited PDF sections extracted and relevant organization figures visually inspected",
        "sections": "Issue 04; pp. 19, 30–36, Figures 3-1/3-2. Board/SoC hierarchy and alternative tag-storage implementations.",
        "sha256": "7548e22fbc0a3fb2ef8418f975657fdea0e615243a5270df9d46178433efde0c"
      }
    },
    {
      "id": "gap-morello-software",
      "title": "CHERI software for the Arm Morello board",
      "author": "University of Cambridge CHERI team",
      "year": 2022,
      "url": "https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-morello-software.html",
      "type": "Implementer software documentation",
      "scope": "CHERI software stack and Spring 2022 board-support release; no claim of present release currency.",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Technical web sections opened and read",
        "sections": "Software stack; Spring 2022 release"
      }
    },
    {
      "id": "gap-plasticine-paper",
      "title": "Plasticine: A Reconfigurable Architecture for Parallel Patterns",
      "author": "R. Prabhakar et al.",
      "year": 2017,
      "url": "https://mast.stanford.edu/pubs/plasticine_a_reconfigurable_accelerator_for_parallel_patterns/paper.pdf",
      "scope": "ISCA 2017; §§3.1–3.7 and 4.2; Figures 3–6; Tables 3/5. Synthesized design and cycle-accurate evaluation, not fabricated-silicon measurements.",
      "type": "Primary technical publication",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Cited PDF sections extracted and relevant organization figures visually inspected",
        "sections": "ISCA 2017; §§3.1–3.7 and 4.2; Figures 3–6; Tables 3/5. Synthesized design and cycle-accurate evaluation, not fabricated-silicon measurements.",
        "sha256": "f5eef0521d18d9ca3661c3ba498f731ad7b3919d1660b9575fb2e49fe6698bbf"
      }
    },
    {
      "id": "gap-actor-hewitt",
      "title": "Actor Model of Computation: Scalable Robust Information Systems, v38",
      "author": "Carl Hewitt",
      "year": 2015,
      "url": "https://arxiv.org/pdf/1008.1459v38",
      "scope": "21 January 2015 revision; pp. 1–4, Fundamental concepts and Direct communication/asynchrony. Explicit model-level roles.",
      "type": "Primary technical publication",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Cited PDF sections extracted and relevant organization figures visually inspected",
        "sections": "21 January 2015 revision; pp. 1–4, Fundamental concepts and Direct communication/asynchrony. Explicit model-level roles.",
        "sha256": "8fe4bdaa3badb9bedefa0fead87f006c7867c5a59e4e0a6e890974cec8afe85e"
      }
    },
    {
      "id": "gap-petri-bakery",
      "title": "Essentials of Petri nets, v1",
      "author": "Wolfgang Reisig / Peter Fettke",
      "year": 2024,
      "url": "https://arxiv.org/pdf/2408.15042v1",
      "scope": "pp. 3–4, Figures 2–4: four bakery events, their distributed run and global-marking alternative.",
      "type": "Primary technical publication",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Cited PDF sections extracted and relevant organization figures visually inspected",
        "sections": "pp. 3–4, Figures 2–4: four bakery events, their distributed run and global-marking alternative.",
        "sha256": "f67569bbe482ad002b07116466adf863a34674315ad0cc0e5bf6f1154c74a21c"
      }
    },
    {
      "id": "gap-flynn-1972",
      "title": "Some Computer Organizations and Their Effectiveness",
      "author": "Michael J. Flynn",
      "year": 1972,
      "url": "https://users.cs.utah.edu/~hari/teaching/paralg/Flynn72.pdf",
      "scope": "IEEE Transactions on Computers C-21(9), pp. 948–951; original paper, particularly p. 949’s MISD definition and request/service hierarchy.",
      "type": "Primary technical publication",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Cited PDF sections extracted and relevant organization figures visually inspected",
        "sections": "IEEE Transactions on Computers C-21(9), pp. 948–951; original paper, particularly p. 949’s MISD definition and request/service hierarchy.",
        "sha256": "7a7b318f56fc5b9f708504a91b477123a9c30aacbd167e69b2597f6960c93bb7"
      }
    },
    {
      "id": "gap-lispkit-manual",
      "title": "The LispKit Manual, Volume 1 — PRG-32(1)",
      "author": "Peter Henderson / Geraint A. Jones / Simon B. Jones",
      "year": 1983,
      "url": "https://www.cs.ox.ac.uk/files/3299/PRG32%20vol%201.pdf",
      "scope": "Printed pp. 1, 5, 107–113 (PDF 3, 5, 104–110): portable SECD implementation, lazy recipe instructions and closure loading.",
      "type": "Primary technical publication",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Cited PDF sections extracted and relevant organization figures visually inspected",
        "sections": "Printed pp. 1, 5, 107–113 (PDF 3, 5, 104–110): portable SECD implementation, lazy recipe instructions and closure loading.",
        "sha256": "97bbf957fdc9fcd0edd883c93ad35196e9833c38c894f928dcaef0063c10d46e"
      }
    },
    {
      "id": "hist-seed-eniac-burks-inspected",
      "title": "Electronic Computing Circuits of the ENIAC",
      "author": "Arthur W. Burks",
      "year": 1947,
      "url": "https://archive.computerhistory.org/resources/text/Knuth_Don_X4100/PDF_index/k-8-pdf/k-8-r5367-1-ENIAC-circuits.pdf",
      "scope": "Proceedings of the IRE 35(8), pp. 756–767; original programming organization: §§V,VI pp. 760–766, including master/local controls, digit trunks, accumulator decade/program circuits, specialized arithmetic, constant/card input and printer/card output.",
      "type": "Primary technical source",
      "accessed": "2026-11-02",
      "inspection": {
        "method": "Private designer-paper scan; pp. 756–758 and 761–767 rendered and read visually; original Figs. 2,3,6 and arithmetic explanation inspected",
        "sections": "Proceedings of the IRE 35(8), pp. 756–767; original programming organization: §§V,VI pp. 760–766, including master/local controls, digit trunks, accumulator decade/program circuits, specialized arithmetic, constant/card input and printer/card output."
      },
      "sha256": "420f875f27022d5ed2a513299ddd6b79e2cc83eaad453c3c7a1af007434734f4"
    },
    {
      "id": "hist-seed-pdp1120-handbook-inspected",
      "title": "PDP-11 Handbook, Second Edition",
      "author": "Digital Equipment Corporation",
      "year": 1970,
      "url": "https://www.bitsavers.org/pdf/dec/pdp11/1120/PDP-11_Handbook_Second_Edition_1970.pdf",
      "scope": "pp. 1–3 basic PDP-11/20 configuration and software; pp. 5–10 UNIBUS, KA11 registers, PSW, NPR and vectored nested interrupts; Chapter 8 pp. 59–64 bus transactions/arbitration. Figure 2-2 nested-device servicing inspected.",
      "type": "Primary technical source",
      "accessed": "2026-11-02",
      "inspection": {
        "method": "Private manufacturer PDF; extracted architecture and bus sections read; original nested-stack figure rendered and visually inspected",
        "sections": "pp. 1–3 basic PDP-11/20 configuration and software; pp. 5–10 UNIBUS, KA11 registers, PSW, NPR and vectored nested interrupts; Chapter 8 pp. 59–64 bus transactions/arbitration. Figure 2-2 nested-device servicing inspected."
      },
      "sha256": "2bfae0f0215286adf5497dc074ea8afea35cc4668a289db75358831b57929275"
    },
    {
      "id": "hist-seed-alto-originalscan",
      "title": "Alto: A Personal Computer, CSL-79-11",
      "author": "C. P. Thacker, E. M. McCreight, B. W. Lampson, R. F. Sproull and D. R. Boggs / Xerox PARC",
      "year": 1979,
      "url": "https://bwlampson.site/25-Alto/25-Alto.pdf",
      "scope": "7 August 1979, reprinted February 1984. §§1–2; printed pp. 3–5 and Fig. 2 explicitly identify the original 1973 64K parity, 1K PROM and 32-R-register baseline. §§2.2–2.4 explain task wakeups, buses and controller-driven processing. Later S-register banks/control RAM/ECC rows excluded.",
      "type": "Primary technical source",
      "accessed": "2026-11-02",
      "inspection": {
        "method": "Author-hosted original PDF scan; revision table and original technical pages rendered/read visually; author OCR used as search aid, not sole figure evidence",
        "sections": "7 August 1979, reprinted February 1984. §§1–2; printed pp. 3–5 and Fig. 2 explicitly identify the original 1973 64K parity, 1K PROM and 32-R-register baseline. §§2.2–2.4 explain task wakeups, buses and controller-driven processing. Later S-register banks/control RAM/ECC rows excluded."
      },
      "sha256": "e1c12866aa3d08f40bc89d00dfc48235580b364ecc1ba35160cefcbd8bfb98de"
    },
    {
      "id": "hist-menabrea-1843",
      "title": "Sketch of the Analytical Engine",
      "author": "L. F. Menabrea; translated by Ada Lovelace",
      "year": 1843,
      "url": "https://www.yorku.ca/pclassic/Lovelace/menabrea.htm",
      "scope": "Mill/store description; operation, variable and number cards; contingent sequencing and printing. Contemporary design account, not evidence of a completed engine.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Mill/store description; operation, variable and number cards; contingent sequencing and printing. Contemporary design account, not evidence of a completed engine."
      }
    },
    {
      "id": "hist-lovelace-1843",
      "title": "Notes by the Translator on the Analytical Engine",
      "author": "Ada Lovelace",
      "year": 1843,
      "url": "https://psychclassics.yorku.ca/Lovelace/lovelace.htm",
      "scope": "Notes A, B and G; distinction between operations and variables, supplying/receiving cards, and a worked program.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Notes A, B and G; distinction between operations and variables, supplying/receiving cards, and a worked program."
      }
    },
    {
      "id": "hist-z3-architecture",
      "title": "Architektur der Z3",
      "author": "Konrad Zuse Internet Archive / ZIB engineering simulation project",
      "year": null,
      "url": "https://zuse-z1.zib.de/simulations/z3/entire/architektur.html",
      "scope": "Architecture, clocking, instructions, operand registers and load/store behavior; engineering reconstruction explanation, not original wiring documentation.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Architecture, clocking, instructions, operand registers and load/store behavior; engineering reconstruction explanation, not original wiring documentation."
      }
    },
    {
      "id": "hist-mark1-function",
      "title": "Harvard IBM Mark I — Function",
      "author": "Harvard Collection of Historical Scientific Instruments",
      "year": null,
      "url": "https://chsi.harvard.edu/harvard-ibm-mark-1-function",
      "scope": "Functional components: constant switches, storage counters, sequence control/interpolators, drive shaft, card equipment. Institution-held machine explanation.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Functional components: constant switches, storage counters, sequence control/interpolators, drive shaft, card equipment. Institution-held machine explanation."
      }
    },
    {
      "id": "hist-mark1-manual",
      "title": "A Manual of Operation for the Automatic Sequence Controlled Calculator — selected passages",
      "author": "Harvard Computation Laboratory",
      "year": 1946,
      "url": "https://chsi.harvard.edu/harvard-ibm-mark-1-manual",
      "scope": "Harvard’s indexed manual sections: pp. 11, 48, 59, 99, 109, 185, 195, 247, 290. Full archive scan timed out; institution’s selected-section descriptions inspected.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Institutional manual index and component description; full scan not retrieved",
        "sections": "Harvard’s indexed manual sections: pp. 11, 48, 59, 99, 109, 185, 195, 247, 290. Full archive scan timed out; institution’s selected-section descriptions inspected."
      }
    },
    {
      "id": "hist-abc-manual",
      "title": "Atanasoff–Berry Computer manual",
      "author": "Clifford Berry",
      "year": null,
      "url": "https://jva.cs.iastate.edu/img/ABC%20%20manual.pdf",
      "scope": "Counters, computer circuit, holding/shifting, input/output and switching. Original manuscript scan hosted by Iowa State; OCR checked for terminology.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Counters, computer circuit, holding/shifting, input/output and switching. Original manuscript scan hosted by Iowa State; OCR checked for terminology."
      }
    },
    {
      "id": "hist-abc-reconstruction",
      "title": "Reconstruction of the Atanasoff–Berry Computer",
      "author": "John Gustafson / Iowa State University and Ames Laboratory",
      "year": null,
      "url": "https://agimcami.wordpress.com/wp-content/uploads/2012/11/abcpaper.pdf",
      "scope": "§2 Figure 1; §3 Figure 2; §6 scratch cards; §7 operator instructions. Reconstruction team’s primary engineering account; replica changes explicitly separated.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "§2 Figure 1; §3 Figure 2; §6 scratch cards; §7 operator instructions. Reconstruction team’s primary engineering account; replica changes explicitly separated."
      }
    },
    {
      "id": "hist-tunny-colossus",
      "title": "General Report on Tunny — Chapter 53: Colossus",
      "author": "I. J. Good, Donald Michie, Geoffrey Timms and Newmanry contributors",
      "year": 1945,
      "url": "https://www.codesandciphers.org.uk/documents/newman/newman.pdf",
      "scope": "Original report pp. 333–351, §§53A–N: streams, stepping, differencing, counters, score recording, Q/plug panels, multiple tests. Tony Sale’s 2001 OCR transcription; variants are documented in the report.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Original report pp. 333–351, §§53A–N: streams, stepping, differencing, counters, score recording, Q/plug panels, multiple tests. Tony Sale’s 2001 OCR transcription; variants are documented in the report."
      }
    },
    {
      "id": "hist-tunny-colossus-intro",
      "title": "General Report on Tunny — Colossus introduction and Z stream",
      "author": "Newmanry contributors",
      "year": 1945,
      "url": "https://www.codesandciphers.org.uk/documents/newman/PAGE333.HTM",
      "scope": "§53A and beginning §53B: tape timing, generated streams, conditions and limited memory. Original report transcription.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "§53A and beginning §53B: tape timing, generated streams, conditions and limited memory. Original report transcription."
      }
    },
    {
      "id": "hist-baby-iee",
      "title": "Universal High-Speed Digital Computers: A Small-Scale Experimental Machine",
      "author": "F. C. Williams, T. Kilburn, G. C. Tootill",
      "year": 1951,
      "url": "https://www.curation.cs.manchester.ac.uk/computer50/www.computer50.org/kgill/mark1/ssem.html",
      "scope": "§§3.1–3.5, 4.1–4.3, 7.7; Figures 3, 5, 6, 8, 9 and 22. Designer paper transcribed with IEE permission; description concerns the June 1948 machine.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "§§3.1–3.5, 4.1–4.3, 7.7; Figures 3, 5, 6, 8, 9 and 22. Designer paper transcribed with IEE permission; description concerns the June 1948 machine."
      }
    },
    {
      "id": "hist-baby-manchester",
      "title": "Manchester Small Scale Experimental Machine — specification",
      "author": "University of Manchester Computer50 project",
      "year": null,
      "url": "https://www.curation.cs.manchester.ac.uk/computer50/www.computer50.org/mark1/new.baby.html",
      "scope": "Background and specification; 21 June 1948 event, 32-word store, CRT registers and manual input.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Background and specification; 21 June 1948 event, 32-word store, CRT registers and manual input."
      }
    },
    {
      "id": "hist-z4-eth-manual",
      "title": "Bedienungsanweisung Z4",
      "author": "ETH Zürich, Institut für angewandte Mathematik; attributed to Heinz Rutishauser",
      "year": 1952,
      "url": "https://www.e-manuscripta.ch/zuthsa/download/pdf/2856520",
      "scope": "Original ETH manual, Hs 1517:1, printed pp. 1–3 (PDF 3–5): organization diagram, arithmetic, storage, operating modes, readers/punch, keyboard, display and printing.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original PDF; rendered pages visually inspected (German); no OCR text was available",
        "sections": "Original ETH manual, Hs 1517:1, printed pp. 1–3 (PDF 3–5): organization diagram, arithmetic, storage, operating modes, readers/punch, keyboard, display and printing."
      },
      "sha256": "be06170cef6dccb6df724d31a8a285da3c937de63391c0dacb2f560a51e53860"
    },
    {
      "id": "hist-manchester-series",
      "title": "The University of Manchester Computing Machine",
      "author": "F. C. Williams and T. Kilburn",
      "year": 1951,
      "url": "https://www.curation.cs.manchester.ac.uk/computer50/www.computer50.org/kgill/mark1/conf.html",
      "scope": "“An Improved Machine”, “A Large-scale Machine”, magnetic storage, B tube, auxiliary staticisor and programmed teleprinter I/O. Designer conference paper, transcribed.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "“An Improved Machine”, “A Large-scale Machine”, magnetic storage, B tube, auxiliary staticisor and programmed teleprinter I/O. Designer conference paper, transcribed."
      }
    },
    {
      "id": "hist-manchester-mark1",
      "title": "Manchester Mark 1 — staged specifications",
      "author": "University of Manchester Computer50 project",
      "year": null,
      "url": "https://www.curation.cs.manchester.ac.uk/computer50/www.computer50.org/mark1/MM1.html",
      "scope": "Intermediary April 1949 specification and final autumn 1949 version; memory and auxiliary CRT roles.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Intermediary April 1949 specification and final autumn 1949 version; memory and auxiliary CRT roles."
      }
    },
    {
      "id": "hist-ias-estrin",
      "title": "A Description of the Electronic Computer at the Institute for Advanced Studies",
      "author": "Gerald Estrin / Institute for Advanced Study",
      "year": 1952,
      "url": "https://www.cs.unh.edu/~pjh/courses/cs520/05fall/p95-estrin.pdf",
      "scope": "Designer report pp. 95–103; Figures 3–14: actual registers, memory/control organs, asynchronous sequences and arithmetic. Proposed 1946 requirements are explicitly separated from the built machine.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Designer report pp. 95–103; Figures 3–14: actual registers, memory/control organs, asynchronous sequences and arithmetic. Proposed 1946 requirements are explicitly separated from the built machine."
      }
    },
    {
      "id": "hist-univac-1954",
      "title": "Manual of Operation for UNIVAC System",
      "author": "Remington Rand",
      "year": 1954,
      "url": "https://bitsavers.org/pdf/univac/univac1/UNIVAC1_Operating_Manual_1954.pdf",
      "scope": "Chapter I memory/registers; Chapter III actual central-computer instructions; Chapter IV §§1–8 tape buffers, interlocks and console I/O. Chapter II’s illustrative simple computer is not treated as the real UNIVAC.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded PDF; extracted selected chapters and checked register-transfer text",
        "sections": "Chapter I memory/registers; Chapter III actual central-computer instructions; Chapter IV §§1–8 tape buffers, interlocks and console I/O. Chapter II’s illustrative simple computer is not treated as the real UNIVAC."
      },
      "sha256": "0cdd7e10fa467fb690a61eeea616dec89e78635398aaf422201746c5ffa5744c"
    },
    {
      "id": "hist-ibm701-principles",
      "title": "Principles of Operation: Type 701 and Associated Equipment, 24-6042-1",
      "author": "IBM",
      "year": 1953,
      "url": "https://www.bitsavers.org/pdf/ibm/701/24-6042-1_701_PrincOps.pdf",
      "scope": "Installation list; pp. 11–18 and 23: general organization, CRT storage, arithmetic registers, Figure 3 data flow, stored program and sequencing.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded scan; selected original pages rendered and visually inspected",
        "sections": "Installation list; pp. 11–18 and 23: general organization, CRT storage, arithmetic registers, Figure 3 data flow, stored program and sequencing."
      },
      "sha256": "53494e5cfa439767db44ebce14a1a6b6e6e55ce0e12199aa5bc1196adfb09b72"
    },
    {
      "id": "hist-ibm650-engineering",
      "title": "IBM 650 Customer Engineering Manual of Instruction, 22-6284-1",
      "author": "IBM",
      "year": null,
      "url": "https://bitsavers.org/pdf/ibm/650/22-6284-1_650_CE_Manual_of_Instruction.pdf",
      "scope": "Section I pp. I-1 and I-3–I-9: decimal representation, instruction addresses, drum geometry/timing, and read/punch buffer operation.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded scan; original technical pages and drum diagrams rendered and visually inspected",
        "sections": "Section I pp. I-1 and I-3–I-9: decimal representation, instruction addresses, drum geometry/timing, and read/punch buffer operation."
      },
      "sha256": "224d7de95f95f49793c22c5c06341f8c8eb045fd86abc016c557cf5d09b89c44"
    },
    {
      "id": "hist-edsac-engineering",
      "title": "Edsac Simulator Tutorial Guide — original EDSAC organization",
      "author": "Martin Campbell-Kelly",
      "year": 2021,
      "url": "https://www.dcs.warwick.ac.uk/~edsac/Software/EdsacTG.pdf",
      "scope": "Original-machine discussion pp. 5–6, 13–15, Figure 4, Appendix instruction table. Primary simulator engineering documentation, explicitly distinguished from original hardware evidence.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web PDF text; architecture, register descriptions and instruction semantics inspected",
        "sections": "Original-machine discussion pp. 5–6, 13–15, Figure 4, Appendix instruction table. Primary simulator engineering documentation, explicitly distinguished from original hardware evidence."
      }
    },
    {
      "id": "hist-edsac-log",
      "title": "The start of the EDSAC log",
      "author": "William S. Renwick; transcription David Wheeler / Cambridge Computer Laboratory",
      "year": 1949,
      "url": "https://www.cl.cam.ac.uk/relics/elog.html",
      "scope": "May 6–June 24 entries and notation: first operation, incomplete initial store, multiplier, transfer unit, input/output end pulses.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "May 6–June 24 entries and notation: first operation, incomplete initial store, multiplier, transfer unit, input/output end pulses."
      }
    },
    {
      "id": "hist-edvac-brl1961",
      "title": "A Third Survey of Domestic Electronic Digital Computing Systems — EDVAC",
      "author": "Martin H. Weik / Ballistic Research Laboratories",
      "year": 1961,
      "url": "https://www.ed-thelen.org/comp-hist/BRL61-e.html",
      "scope": "EDVAC pp. 236–239: four-address format, serial arithmetic, stores, input/output, diagnostic features and future plans. Official operational survey in Ed Thelen’s imperfect OCR transcription.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "EDVAC pp. 236–239: four-address format, serial arithmetic, stores, input/output, diagnostic features and future plans. Official operational survey in Ed Thelen’s imperfect OCR transcription."
      }
    },
    {
      "id": "hist-ferranti-designers",
      "title": "Universal High-Speed Digital Computers — The Present Machine",
      "author": "F. C. Williams and T. Kilburn / University of Manchester",
      "year": 1951,
      "url": "https://www.curation.cs.manchester.ac.uk/computer50/www.computer50.org/kgill/mark1/conf.html",
      "scope": "Present Machine; Storage; Rhythm; Accumulator; B Tube; Input and Output. Designer conference account: eight CRTs, initial drum capacity and extensions distinguished.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Present Machine; Storage; Rhythm; Accumulator; B Tube; Input and Output. Designer conference account: eight CRTs, initial drum capacity and extensions distinguished."
      }
    },
    {
      "id": "hist-ferranti-turing-b",
      "title": "Programmers’ Handbook for Manchester Electronic Computer — B tube",
      "author": "Alan M. Turing",
      "year": 1951,
      "url": "https://www.curation.cs.manchester.ac.uk/computer50/www.computer50.org/kgill/mark1/RobertTau/node10.html",
      "scope": "B-normal and B-exceptional instruction formation; eight B-lines and sign flag. Transcription by Robert S. Thau.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "B-normal and B-exceptional instruction formation; eight B-lines and sign flag. Transcription by Robert S. Thau."
      }
    },
    {
      "id": "hist-whirlwind-r221",
      "title": "Whirlwind I Operational Logic, R-221",
      "author": "MIT Digital Computer Laboratory; edited by William N. Papian",
      "year": 1954,
      "url": "https://www.bitsavers.org/pdf/mit/whirlwind/R-series/R-221_Whirlwind_I_Operational_Logic_May54.pdf",
      "scope": "§§1.1–1.4; 2.11; 2.21–2.24; Figure 2. Core-memory organization, parity register, shared bus, control matrix and arithmetic.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original report; selected technical text and rendered PDF page 20 / printed 2-1 visually inspected",
        "sections": "§§1.1–1.4; 2.11; 2.21–2.24; Figure 2. Core-memory organization, parity register, shared bus, control matrix and arithmetic."
      },
      "sha256": "ccb3174f135a8c0ebec1828d6e6ad7968266894124bf035a32cd8f351158ca70"
    },
    {
      "id": "hist-besm6-institution",
      "title": "BESM-6 Computer",
      "author": "Russian Virtual Computer Museum / ITM and VT development record",
      "year": null,
      "url": "https://www.computer-museum.ru/english/besm6.htm",
      "scope": "Items 9–14: asynchronous overlap, instruction/data buffers, address unit, index memory, associative operands, memory banks, translation/protection, seven external-storage buses. Institutional technical record; author not identified.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Items 9–14: asynchronous overlap, instruction/data buffers, address unit, index memory, associative operands, memory banks, translation/protection, seven external-storage buses. Institutional technical record; author not identified."
      }
    },
    {
      "id": "hist-setun-designers",
      "title": "Ternary Computers: The Setun and the Setun 70",
      "author": "Nikolay P. Brusentsov and José Ramil Alvarez",
      "year": 2011,
      "url": "https://dl.ifip.org/db/conf/ifip9/sorucom2006/BrusentsovA06.pdf",
      "scope": "§§2–3, especially PDF pp. 2–4: original Setun, registers S/R/F/C/omega, 162-cell paged store, drum options, interpretive systems. Designer retrospective; Setun 70 treated separately.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "§§2–3, especially PDF pp. 2–4: original Setun, registers S/R/F/C/omega, 162-cell paged store, drum options, interpretive systems. Designer retrospective; Setun 70 treated separately."
      }
    },
    {
      "id": "hist-mesm-technical",
      "title": "Computers created under S. A. Lebedev — MESM technical characteristics",
      "author": "Institute of Cybernetics / Ukrainian computing-history museum",
      "year": null,
      "url": "https://www.icfcst.kiev.ua/MUSEUM/LEBEDEV/L_computers_r.html",
      "scope": "MESM section, numbered parameters 1–14. Institutional technical summary; Russian original inspected. Distinguishes number and command stores, fixed functional store, parallel arithmetic and serial input.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "MESM section, numbered parameters 1–14. Institutional technical summary; Russian original inspected. Distinguishes number and command stores, fixed functional store, parallel arithmetic and serial input."
      }
    },
    {
      "id": "hist-mesm-makers",
      "title": "How It Began — creation and operation of MESM",
      "author": "Lev Dashevsky and Ekaterina Shkabara",
      "year": 1981,
      "url": "https://www.icfcst.kiev.ua/MUSEUM/DIFFERENT/DSbook2_r.html",
      "scope": "Commissioning and operation sections: acceptance on 25 December 1951, machine-code programming, statistical and power-system workloads. Makers’ retrospective, Russian text.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Commissioning and operation sections: acceptance on 25 December 1951, machine-code programming, statistical and power-system workloads. Makers’ retrospective, Russian text."
      }
    },
    {
      "id": "hist-mesm-minutes",
      "title": "Minutes of Scientific Council session, 8 January 1951",
      "author": "ASU Institute of Electronic Technology and Heat-Power Engineering",
      "year": 1951,
      "url": "https://www.icfcst.kiev.ua/MUSEUM/LEBEDEV/TXT/protocol.html",
      "scope": "Lebedev report and replies: prototype arithmetic, trigger cells, missing automatic I/O and planned magnetic recording. English translation; prototype limitations kept distinct from later service configuration.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Lebedev report and replies: prototype arithmetic, trigger cells, missing automatic I/O and planned magnetic recording. English translation; prototype limitations kept distinct from later service configuration."
      }
    },
    {
      "id": "hist-mir-glushkov",
      "title": "Fundamentals of Paperless Informatics — §2.4.3 Intelligent Processors",
      "author": "Viktor M. Glushkov",
      "year": 1987,
      "url": "https://djvu.online/file/xHvPOAsJMYw6g",
      "scope": "Printed pp. 53–54, §2.4.3; hierarchical microprogram organization referenced to §1.9.2. Designer’s book, OCR transcription; MIR-1 and MIR-2 features distinguished.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Printed pp. 53–54, §2.4.3; hierarchical microprogram organization referenced to §1.9.2. Designer’s book, OCR transcription; MIR-1 and MIR-2 features distinguished."
      }
    },
    {
      "id": "hist-mir-institute",
      "title": "MIR computers — forerunners of personal computers",
      "author": "Institute of Cybernetics / Ukrainian computing-history museum",
      "year": null,
      "url": "https://www.icfcst.kiev.ua/MUSEUM/GL_HALL2/COMPUTERS/MIRS.html",
      "scope": "MIR-2 paragraphs and caption: 1969 machine, analytic transformations, light-pen dialogue and Analitik interpretation. Institutional record contains a repeated MIR-2 typographical error; no inferred MIR-3 specification used.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "MIR-2 paragraphs and caption: 1969 machine, analytic transformations, light-pen dialogue and Analitik interpretation. Institutional record contains a repeated MIR-2 typographical error; no inferred MIR-3 specification used."
      }
    },
    {
      "id": "hist-csirac-manual",
      "title": "Programming Manual for the Automatic Electronic Computer CSIRAC",
      "author": "University of Melbourne Computation Laboratory; based on T. Pearcey and G. W. Hill",
      "year": 1959,
      "url": "https://cis.unimelb.edu.au/__data/assets/pdf_file/0010/5407966/Computation-Laboratory-Programming-Manual-for-CSIRAC.pdf",
      "scope": "§§1.3–1.5; 2.1–2.4; 2.12; 3.6; Appendices 2–3. August 1959 original, reformatted by Bill Purvis February 2021. Source/destination gates, multiplication, command modification and external I/O inspected.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "§§1.3–1.5; 2.1–2.4; 2.12; 3.6; Appendices 2–3. August 1959 original, reformatted by Bill Purvis February 2021. Source/destination gates, multiplication, command modification and external I/O inspected."
      }
    },
    {
      "id": "hist-zebra-stc",
      "title": "Stantec Zebra — electronic digital computer",
      "author": "Standard Telephones and Cables Limited",
      "year": 1961,
      "url": "https://archive.computerhistory.org/resources/text/Standard/Stantec.Zebra.1961.102646082.pdf",
      "scope": "PDF pp. 6–11: basic equipment, drum, Normal Code, Simple Code, 33-bit specification, 12 immediate stores and two add/subtract accumulators. Optional ferrite/tape extensions excluded.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "PDF pp. 6–11: basic equipment, drum, Normal Code, Simple Code, 33-bit specification, 12 immediate stores and two add/subtract accumulators. Optional ferrite/tape extensions excluded."
      }
    },
    {
      "id": "hist-zebra-designer",
      "title": "The Simple Code for ZEBRA",
      "author": "W. L. van der Poel",
      "year": 1959,
      "url": "https://www.bitsavers.org/pdf/stantec/W.L_van_der_Poel_-_The_Simple_Code_for_Zebra_195908.pdf",
      "scope": "Introduction and closing implementation discussion. Designer explicitly distinguishes the interpreted Simple Code from the real machine; multiply is programmed.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original paper; OCR text of introduction and implementation sections inspected",
        "sections": "Introduction and closing implementation discussion. Designer explicitly distinguishes the interpreted Simple Code from the real machine; multiply is programmed."
      },
      "sha256": "716f112d1cba8e92a2eed3125b54f44d032858a7f83ca12bd926aa4f658b4366"
    },
    {
      "id": "hist-lgp30-manual",
      "title": "LGP-30 Programming Manual",
      "author": "Royal McBee Corporation",
      "year": 1957,
      "url": "https://www.bitsavers.org/pdf/royalPrecision/LGP-30/LGP-30_Programming_Manual_Apr57.pdf",
      "scope": "Printed pp. 8–12, 27–28, 32–34 and final specifications: drum/registers, four execution phases, number format, print/input orders.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded scan; original diagrams and technical pages rendered and visually read",
        "sections": "Printed pp. 8–12, 27–28, 32–34 and final specifications: drum/registers, four execution phases, number format, print/input orders."
      },
      "sha256": "f65fb85e07a51e4f11121718c8ec8c356640f53b9299b0bf03e6b7d373040eb0"
    },
    {
      "id": "hist-stretch-designers",
      "title": "Planning a Computer System: Project Stretch — Chapter 3",
      "author": "Werner Buchholz, editor and Chapter 3 author / IBM development team",
      "year": 1962,
      "url": "https://archive.computerhistory.org/resources/text/IBM/Stretch/pdfs/Buchholz_102636426.pdf",
      "scope": "Chapter 3 §§3.1–3.11 (printed pp. 17–23), especially system organization, memory bus, index core, exchange, look-ahead and arithmetic. Designer engineering monograph.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original book; selected Chapter 3 extracted text and figure labels inspected",
        "sections": "Chapter 3 §§3.1–3.11 (printed pp. 17–23), especially system organization, memory bus, index core, exchange, look-ahead and arithmetic. Designer engineering monograph."
      },
      "sha256": "1a675cc8b81f24c8455463cb30433b01f1c89491d67f5332720710b8ed9efc6d"
    },
    {
      "id": "hist-ibm7090-manual",
      "title": "IBM 709–7090 General Information Manual, D22-6508-2",
      "author": "IBM",
      "year": 1960,
      "url": "https://www.bitsavers.org/pdf/ibm/7090/D22-6508-2_709_7090_General_Information_Manual_Aug1960.pdf",
      "scope": "Printed pp. 12–20, 35–37, 42 and 44–46. Registers, instruction/address paths, 7090-specific multiplexor and channels, comparison table and software. 709-only drum/CRT equipment excluded.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original manual; extracted technical text and figure labels inspected",
        "sections": "Printed pp. 12–20, 35–37, 42 and 44–46. Registers, instruction/address paths, 7090-specific multiplexor and channels, comparison table and software. 709-only drum/CRT equipment excluded."
      },
      "sha256": "9f679316681b9e90ec78c61b1ebc92418c02f4458376ce85aa6cefc081e13006"
    },
    {
      "id": "hist-36030-engineering",
      "title": "IBM 2030 Field Engineering Theory of Operation, Y24-3360-1",
      "author": "IBM",
      "year": 1967,
      "url": "https://bitsavers.org/pdf/ibm/360/fe/2030/Y24-3360-1_2030_FE_Theory_Opns_Jun67.pdf",
      "scope": "Chapter 1 pp. 1-1–1-4, Figures 1-2–1-4; read-only-storage control, ALU A/B inputs, auxiliary core storage, channels and model sizes.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original engineering manual; selected text and data-flow figure labels inspected",
        "sections": "Chapter 1 pp. 1-1–1-4, Figures 1-2–1-4; read-only-storage control, ALU A/B inputs, auxiliary core storage, channels and model sizes."
      },
      "sha256": "e5d0c2d7a399ddb434a0c0a50876b2b859457a75acc37155505e1dce8bfbf8b6"
    },
    {
      "id": "hist-36067-functional",
      "title": "IBM System/360 Model 67 Functional Characteristics, GA27-2719-2",
      "author": "IBM",
      "year": 1972,
      "url": "https://bitsavers.org/pdf/ibm/360/functional_characteristics/GA27-2719-2_360-67_funcChar.pdf",
      "scope": "Third edition February 1972, pp. 6–15: paging, DAT, system units, bus control, associative translations, prefixing, channel bypass. 67-1 and duplex 67-2 distinctions inspected.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original manual; technical text and DAT figure labels inspected",
        "sections": "Third edition February 1972, pp. 6–15: paging, DAT, system units, bus control, associative translations, prefixing, channel bypass. 67-1 and duplex 67-2 distinctions inspected."
      },
      "sha256": "f9a52693633610aaed09932aa638ebdbabf437591455bbd82b337f6cc4108cd2"
    },
    {
      "id": "hist-36091-designers",
      "title": "The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling",
      "author": "D. W. Anderson, F. J. Sparacio and R. M. Tomasulo",
      "year": 1967,
      "url": "https://american.cs.ucdavis.edu/academic/readings/papers/ibm360-91.pdf",
      "scope": "IBM Journal January 1967 pp. 8–13, Figure 5 and instruction handling sections: independent execution, fetch/history, operand/operation buffers, store buffers and conflict addresses.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original designer paper; text and Figure 5 on PDF p. 4 visually inspected",
        "sections": "IBM Journal January 1967 pp. 8–13, Figure 5 and instruction handling sections: independent execution, fetch/history, operand/operation buffers, store buffers and conflict addresses."
      },
      "sha256": "bc7f0f5920721a437cbf723569d563f91c01c2807b15a5198cb09709ffb873e2"
    },
    {
      "id": "hist-370168-functional",
      "title": "IBM System/370 Model 168 Functional Characteristics, GA22-7010-4",
      "author": "IBM",
      "year": 1976,
      "url": "https://bitsavers.org/pdf/ibm/370/funcChar/GA22-7010-4_370-168_funcChar_Jul76.pdf",
      "scope": "Fifth edition January 1976 with June TNL; pp. 10–16, Figure 5, buffer/TLB operation. Model 1 versus Model 3 and attached processor extensions distinguished.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original manual; selected technical text and figure labels inspected",
        "sections": "Fifth edition January 1976 with June TNL; pp. 10–16, Figure 5, buffer/TLB operation. Model 1 versus Model 3 and attached processor extensions distinguished."
      },
      "sha256": "da4e7942cb07a0435a94a00c0283339224e56490d9c79920db2afb7f43827c4e"
    },
    {
      "id": "hist-icl1904a-training",
      "title": "1904A Training Module 4, BB006, Issue B",
      "author": "International Computers Limited, Engineering Training Division",
      "year": 1972,
      "url": "https://www.bitsavers.org/pdf/ict_icl/1900/BB006_1904A_Training_Module_4_Sep72.pdf",
      "scope": "Sheets 1.1–1.7: system diagram, program layout, Executive, configurations, data flow, register uses. Original 1969 sheets in September 1972 training issue.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded scan; PDF pp. 2–4, 9–10, 12, 14–15 rendered and visually inspected",
        "sections": "Sheets 1.1–1.7: system diagram, program layout, Executive, configurations, data flow, register uses. Original 1969 sheets in September 1972 training issue."
      },
      "sha256": "3d9bc782f5f3b9e0f0c3db488fe26fe7db4546df0ef2c94b95b27396535ec9f4"
    },
    {
      "id": "hist-b5000-operational",
      "title": "The Operational Characteristics of the Processors for the Burroughs B5000, 5000-21005, Revision A",
      "author": "Burroughs Corporation",
      "year": 1963,
      "url": "https://bitsavers.org/pdf/burroughs/LargeSystems/B5000_5500_5700/5000-21005_B5000_operChar_1963.pdf",
      "scope": "Sections 1–3: modular exchange, word/character modes, PRT descriptors, program and stack/source registers, interrupts and parallel/serial arithmetic.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original manual; selected technical text and register diagram labels inspected",
        "sections": "Sections 1–3: modular exchange, word/character modes, PRT descriptors, program and stack/source registers, interrupts and parallel/serial arithmetic."
      },
      "sha256": "2ca00ef3f3d767808d23a24f7d21e5735a095ddd5748763678af35214deb89c7"
    },
    {
      "id": "hist-b6500-reference",
      "title": "B6500 Information Processing Systems Reference Manual, 1043676",
      "author": "Burroughs Corporation",
      "year": 1969,
      "url": "https://bitsavers.org/pdf/burroughs/LargeSystems/B6500/1043676_B6500_Reference_Manual_196909.pdf",
      "scope": "September 1969: §1 system organization, processor states, memory words, I/O multiplexor; §3 stack registers, bounds, descriptors and presence-bit handling.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original manual; selected technical text and figures 1-4 / 3-1 labels inspected",
        "sections": "September 1969: §1 system organization, processor states, memory words, I/O multiplexor; §3 stack registers, bounds, descriptors and presence-bit handling."
      },
      "sha256": "46fe0f95380881b2c0cb92760c1a0bbd8cb0ff7808560971be74faf3bea3502b"
    },
    {
      "id": "hist-kdf9-programming",
      "title": "KDF9 Programming Manual",
      "author": "English Electric / English Electric Leo",
      "year": null,
      "url": "https://www.gtoal.com/history.dcs.ed.ac.uk/archive/bfoley/kdf9pm/kdf9pm.html",
      "scope": "§3.1–3.8, pp. 15–20: core modules, autonomous buffers, nesting store, Q-stores, control and return-address nest; §11 subroutines. Original-manual transcription; edition date not stated on inspected page.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "§3.1–3.8, pp. 15–20: core modules, autonomous buffers, nesting store, Q-stores, control and return-address nest; §11 subroutines. Original-manual transcription; edition date not stated on inspected page."
      }
    },
    {
      "id": "hist-z16-redbook",
      "title": "IBM z16 Technical Introduction, SG24-8950-01",
      "author": "Ewerson Palacio, Bill White and Octavian Lascu / IBM",
      "year": 2023,
      "url": "https://www.redbooks.ibm.com/redbooks/pdfs/sg248950.pdf",
      "scope": "Second edition April 2023, Chapter 2 §§2.3–2.3.2, Figures 2-4–2-5: A01 drawer, DCMs, links, physical caches versus virtual victim-cache roles, DIMMs and I/O fanouts.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded official Redbook; technical text and PDF p. 36 cache diagram visually inspected",
        "sections": "Second edition April 2023, Chapter 2 §§2.3–2.3.2, Figures 2-4–2-5: A01 drawer, DCMs, links, physical caches versus virtual victim-cache roles, DIMMs and I/O fanouts."
      },
      "sha256": "b14ea3c02609e08b9b6ebcd396b9dbe2eff71b2763eba0d84bf897d1bd59c17a"
    },
    {
      "id": "hist-ge645-manual",
      "title": "GE-645 System Manual, LSB0468",
      "author": "General Electric Information Systems Equipment Division",
      "year": 1968,
      "url": "https://bitsavers.org/pdf/ge/GE-645/LSB0468_GE-645_System_Manual_Jan1968.pdf",
      "scope": "January 1968, Chapters 4–6: controller/memory modularity, processor registers, segmentation/paging, descriptor tables, 16-entry associative store and interrupts. Preface identifies then-planned Multics features.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original manual; selected technical text and figure labels inspected",
        "sections": "January 1968, Chapters 4–6: controller/memory modularity, processor registers, segmentation/paging, descriptor tables, 16-entry associative store and interrupts. Preface identifies then-planned Multics features."
      },
      "sha256": "71db680517d0721c4dfddc97a85b48fd7daf85950cbe142c30811320cd21bc01"
    },
    {
      "id": "hist-multics-saltzer",
      "title": "Initial MIT Multics configuration, 1967–1972",
      "author": "Jerome H. Saltzer / MIT",
      "year": 2004,
      "url": "https://www.mit.edu/~Saltzer/multics.html",
      "scope": "Initial equipment list and Spring 1970 service paragraph; assembled by a Multics designer from personal files. Distinct from later upgrades and retrospective feature list.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Initial equipment list and Spring 1970 service paragraph; assembled by a Multics designer from personal files. Distinct from later upgrades and retrospective feature list."
      }
    },
    {
      "id": "hist-tandem16-katzman",
      "title": "The Tandem 16: A Fault-Tolerant Computing System",
      "author": "James A. Katzman / Tandem Computers",
      "year": 1978,
      "url": "https://gordonbell.azurewebsites.net/computer_structures_principles_and_examples/csp0487.htm",
      "scope": "System organization and packaging, reprinted in Computer Structures Chapter 29 pp. 471–472; processor-local memory, dual Dynabus, dual-ported controllers and independent power.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "System organization and packaging, reprinted in Computer Structures Chapter 29 pp. 471–472; processor-local memory, dual Dynabus, dual-ported controllers and independent power."
      }
    },
    {
      "id": "hist-tandem16-processor",
      "title": "The Tandem 16 — power distribution and processor organization",
      "author": "James A. Katzman / Tandem Computers",
      "year": 1978,
      "url": "https://gordonbell.azurewebsites.net/computer_structures_principles_and_examples/csp0488.htm",
      "scope": "Reprinted p. 472: dual-power I/O, Dynabus and local interconnects, 16-bit microprogrammed CPU, eight registers, private memory and paging.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded HTML; original reprint text inspected after web cache miss",
        "sections": "Reprinted p. 472: dual-power I/O, Dynabus and local interconnects, 16-bit microprogrammed CPU, eight registers, private memory and paging."
      }
    },
    {
      "id": "hist-tandem-kernel",
      "title": "A NonStop Kernel, TR81-04",
      "author": "Joel F. Bartlett / Tandem Computers",
      "year": 1981,
      "url": "https://bitsavers.org/pdf/tandem/technical_reports/TR81-04_A_NonStop_Kernel_Jun81.pdf",
      "scope": "Abstract and publication identity: kernel processes/messages and process-pair mechanism. Later software account supplements rather than dates the 1978 hardware.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original reprint; PDF pp. 3 and 5 visually inspected",
        "sections": "Abstract and publication identity: kernel processes/messages and process-pair mechanism. Later software account supplements rather than dates the 1978 hardware."
      },
      "sha256": "5e7807360666585718365342c086d098d87b24e28c8c1fbe0a6e719f87877cbf"
    },
    {
      "id": "hist-stratus-v2404",
      "title": "Stratus ftServer V2404, V4408 and V6408 Site Planning Guide, R645-03B",
      "author": "Stratus Technologies",
      "year": 2019,
      "url": "https://stratadoc.stratus.com/vos/19.1.0/r645-03b/wwhelp/wwhimpl/common/html/r645-03b.pdf",
      "scope": "December 2019 revision for OpenVOS 19.1.0; pp. 1-2–1-3, 3-2, 5-4, A-5–A-6. V2404 enclosure, lockstep, paired I/O, direct Fibre Channel and processor/memory inventory.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "December 2019 revision for OpenVOS 19.1.0; pp. 1-2–1-3, 3-2, 5-4, A-5–A-6. V2404 enclosure, lockstep, paired I/O, direct Fibre Channel and processor/memory inventory."
      },
      "sha256": "323fd8debc6c7809261bbf539b0adfc98a0311f61a3ee0c51fc1771a2c4fa104"
    },
    {
      "id": "hist-elbrus-institution",
      "title": "History of Computing — Elbrus section",
      "author": "Vasily Kotov / Nizhny Novgorod branch of ITM and VT",
      "year": null,
      "url": "https://www.nfitmivt.ru/hist/pdf/hist_comp_Kotov.pdf",
      "scope": "Printed pp. 18–19: first two Elbrus generations, shared-memory switch, processor classes, stack model and El-76. Institutional history; common principles explicitly apply to both generations.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "Printed pp. 18–19: first two Elbrus generations, shared-memory switch, processor classes, stack model and El-76. Institutional history; common principles explicitly apply to both generations."
      }
    },
    {
      "id": "hist-elbrus-babayan",
      "title": "Oral History of Boris Babayan, X6507.2012",
      "author": "Boris Babayan; interviewer Alex Bochannek / Computer History Museum",
      "year": 2012,
      "url": "https://archive.computerhistory.org/resources/access/text/2013/10/102746429-05-01-acc.pdf",
      "scope": "pp. 10–13: first-generation delivery claim, tagged type safety, references/descriptors, multiprogrammed OS and two-issue out-of-order execution. Designer recollections; historical priority claims not adopted.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open text; selected technical sections inspected",
        "sections": "pp. 10–13: first-generation delivery claim, tagged type safety, references/descriptors, multiprogrammed OS and two-issue out-of-order execution. Designer recollections; historical priority claims not adopted."
      }
    },
    {
      "id": "hist-pdp1-1963",
      "title": "PDP-1 Handbook, F-15D",
      "author": "Digital Equipment Corporation",
      "year": 1963,
      "url": "https://bitsavers.org/pdf/dec/pdp1/F15D_PDP1_Handbook_Oct63.pdf",
      "scope": "October 1963; pp. 3–8: processor registers, core, standard equipment, I/O and sequence break; pp. 4–5 system diagram visually inspected. This is the handbook-era configuration, including automatic multiply/divide shown as standard.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private PDF retrieval; extracted text and rendered original system diagram inspected",
        "sections": "October 1963; pp. 3–8: processor registers, core, standard equipment, I/O and sequence break; pp. 4–5 system diagram visually inspected. This is the handbook-era configuration, including automatic multiply/divide shown as standard."
      },
      "sha256": "8490b72962584f30c9dc7f3a9684ba3eeb79c7d5530b78ee371a6efe098a8f21"
    },
    {
      "id": "hist-pdp8-1966",
      "title": "PDP-8 User’s Handbook",
      "author": "Digital Equipment Corporation",
      "year": 1966,
      "url": "https://bitsavers.org/pdf/dec/pdp8/handbooks/1966_PDP8_UsersHandbook.pdf",
      "scope": "System Introduction pp. xiii–xiv; functional summary and timing/control pp. 6–7 (PDF 20–21); Figure 2 system block diagram and scan pages 14,20–23 visually inspected. Scan has limited extractable text.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private scan; selected original pages and block diagram rendered and read visually",
        "sections": "System Introduction pp. xiii–xiv; functional summary and timing/control pp. 6–7 (PDF 20–21); Figure 2 system block diagram and scan pages 14,20–23 visually inspected. Scan has limited extractable text."
      },
      "sha256": "28e9f5405600ced8c9b379105f6406c168843564ec30e8b575920f8e4948bc24"
    },
    {
      "id": "hist-ka10-1968",
      "title": "KA10 Maintenance Manual, DEC-10-HMAA-D",
      "author": "Digital Equipment Corporation",
      "year": 1968,
      "url": "https://www.bitsavers.org/pdf/dec/pdp10/KA10/DEC-10-HMAA_D_KA10_Maint_Dec68.pdf",
      "scope": "December 1968; pp. 2-1–2-2 system buses/options; pp. 4-1–4-2 register organization and five major cycles; rendered scan pages 13,36–39 inspected.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private scanned PDF; original diagrams and register descriptions read visually",
        "sections": "December 1968; pp. 2-1–2-2 system buses/options; pp. 4-1–4-2 register organization and five major cycles; rendered scan pages 13,36–39 inspected."
      },
      "sha256": "77edbe1cca0c93179514ea5621699b24efed9d3230fcafbec8ad681a10c38807"
    },
    {
      "id": "hist-pdp1145-1973",
      "title": "PDP-11/45 Handbook",
      "author": "Digital Equipment Corporation",
      "year": 1973,
      "url": "https://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP-1145_Handbook_1973.pdf",
      "scope": "pp. 1–5 system/UNIBUS; pp. 11–16 registers, modes, direct solid-state memory path, dual-port controllers and second UNIBUS.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private PDF; extracted technical sections inspected",
        "sections": "pp. 1–5 system/UNIBUS; pp. 11–16 registers, modes, direct solid-state memory path, dual-port controllers and second UNIBUS."
      },
      "sha256": "0c400f91863df3777fba004f3a7eedb7b33133e86180e04d235740eda547ed64"
    },
    {
      "id": "hist-pdp1170-1977",
      "title": "PDP-11/70 Handbook, 1977–78",
      "author": "Digital Equipment Corporation",
      "year": 1977,
      "url": "https://bitsavers.org/pdf/dec/pdp11/1170/PDP-11_70_Handbook_1977-78.pdf",
      "scope": "pp. 1-1–1-7 and Fig. 1-1: 2KiB cache, 22-bit mapping, separate 32-bit memory path, high-speed channels and write-through operation. Fig. 1-1 visually inspected.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private PDF; extracted technical text and rendered system diagram inspected",
        "sections": "pp. 1-1–1-7 and Fig. 1-1: 2KiB cache, 22-bit mapping, separate 32-bit memory path, high-speed channels and write-through operation. Fig. 1-1 visually inspected."
      },
      "sha256": "8b6ce6229fccf49b4089ac4f4cb883aed94d7f7bc3352f3f9bf4fef2508368ad"
    },
    {
      "id": "hist-vax780-1983",
      "title": "VAX Maintenance Handbook, VAX-11/780, EK-VAXV2-HB-002",
      "author": "Digital Equipment Corporation",
      "year": 1983,
      "url": "https://bitsavers.org/pdf/dec/vax/780/EK-VAXV2-HB-002_VAX_Maintenance_Handbook_VAX-11_780_1983_Edition_198303.pdf",
      "scope": "March 1983; pp. 7–9 system and KA780 CPU block diagrams, instruction facilities, ECC MOS memory, SBI/UNIBUS/MASSBUS, optional FPA/WCS and LSI-11 console. KA780 original diagram visually inspected.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private PDF; extracted text and rendered CPU diagram inspected",
        "sections": "March 1983; pp. 7–9 system and KA780 CPU block diagrams, instruction facilities, ECC MOS memory, SBI/UNIBUS/MASSBUS, optional FPA/WCS and LSI-11 console. KA780 original diagram visually inspected."
      },
      "sha256": "bd373d164683c09ac6cc0dcefbaea36b0e2cbb6fd9515d1a06ce70dd97bae601"
    },
    {
      "id": "hist-nova-1969",
      "title": "How to Maintain Nova",
      "author": "Data General Corporation",
      "year": 1969,
      "url": "https://bitsavers.org/pdf/dg/NovaMaint_1969.pdf",
      "scope": "pp. 1–4: physical organization, four-bit sliced arithmetic, MA/MB/PC/AC registers, processor data flow and programmed/data-channel I/O. Original diagram and scanned prose read visually.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private scanned PDF; selected original pages rendered and visually inspected",
        "sections": "pp. 1–4: physical organization, four-bit sliced arithmetic, MA/MB/PC/AC registers, processor data flow and programmed/data-channel I/O. Original diagram and scanned prose read visually."
      },
      "sha256": "a651fdf2bec95daf9f75213930fb4ad1d4630ad9b4a778a873396607d9d32ac9"
    },
    {
      "id": "hist-hp3000-series2-1976",
      "title": "Series II General-Purpose Computer Systems; All-Semiconductor Memory with Fault Detection, Correction, and Logging",
      "author": "Leonard E. Shar; Elio A. Toschi and Tak Watanabe / Hewlett-Packard Journal",
      "year": 1976,
      "url": "https://vtda.org/pubs/HP_Journal/HP_Journal_1976-08.pdf",
      "scope": "August 1976, pp. 2–7 processor/memory segmentation, bank registers, MPE and Model 9 configuration; pp. 8–10 ECC data path and error logging. Manufacturer designer articles; ordinary copyright notice.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private manufacturer-journal PDF; extracted articles and figure descriptions inspected",
        "sections": "August 1976, pp. 2–7 processor/memory segmentation, bank registers, MPE and Model 9 configuration; pp. 8–10 ECC data path and error logging. Manufacturer designer articles; ordinary copyright notice."
      },
      "sha256": "2c42e6678f057e3fca3ccc3d039965d41a641df2654ee13c329f7b2d83061d2c"
    },
    {
      "id": "hist-agc-block2-r700",
      "title": "MIT’s Role in Project Apollo, Volume III: Computer Subsystem, R-700",
      "author": "Eldon C. Hall / MIT Charles Stark Draper Laboratory",
      "year": 1972,
      "url": "https://www.ibiblio.org/apollo/hrst/archive/1029.pdf",
      "scope": "August 1972; pp. 29–34, 67–69: Block II registers, common-storage words, arithmetic, bus transfers and I/O; Figure 2-4 visually inspected. Retrospective report by development leader; distinguishes Block I throughout.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private PDF; extracted report and rendered original Figure 2-4 inspected",
        "sections": "August 1972; pp. 29–34, 67–69: Block II registers, common-storage words, arithmetic, bus transfers and I/O; Figure 2-4 visually inspected. Retrospective report by development leader; distinguishes Block I throughout."
      },
      "sha256": "8ec0c08d917cb9e7b7f1b2b02ea3d1fca23d9ab3ffa6f3fdbb3f60e48badd422"
    },
    {
      "id": "hist-ibmpc-1981",
      "title": "IBM Personal Computer Technical Reference, 6025005",
      "author": "International Business Machines Corporation",
      "year": 1981,
      "url": "https://raw.githubusercontent.com/ForgottenMachines/IBM-5150/main/IBM_5150_Technical_Reference_6025005_AUG81.pdf",
      "scope": "August 1981; pp. 1-1–1-4 and 2-3–2-7: original 16–64KB system board, 8088 bus, DMA refresh, interrupts, ROM and I/O. Original board data-flow figure visually inspected.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private manufacturer scan; extracted sections and rendered Figure 2 inspected",
        "sections": "August 1981; pp. 1-1–1-4 and 2-3–2-7: original 16–64KB system board, 8088 bus, DMA refresh, interrupts, ROM and I/O. Original board data-flow figure visually inspected."
      },
      "sha256": "09caa5b2d8741959ea35c022ee797ec5b97c386b7bb15fb2c03dc33c7728caed"
    },
    {
      "id": "hist-apple2-redbook",
      "title": "Apple II Reference Manual, 030-0004-00",
      "author": "Apple Computer, Inc.",
      "year": 1978,
      "url": "https://bitsavers.org/pdf/apple/apple_II/Apple%5D%5BRefJan78.pdf",
      "scope": "January 1978; memory pp. 134–136, I/O bus and pin descriptions; original schematics S-3, S-4, S-5, S-6, S-10, S-11 (pp. 143–151) visually inspected. Companion modern typesetting used only to locate readable prose; original scan is evidence.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private original scan; rendered timing, ROM, RAM-select, on-board I/O and video-generator schematics inspected",
        "sections": "January 1978; memory pp. 134–136, I/O bus and pin descriptions; original schematics S-3, S-4, S-5, S-6, S-10, S-11 (pp. 143–151) visually inspected. Companion modern typesetting used only to locate readable prose; original scan is evidence."
      },
      "sha256": "2fe28aacbc5f4ca682ccd1580067fb261330cbf8d853f579f65d2001ebcac332"
    },
    {
      "id": "hist-mac128-inside3",
      "title": "Inside Macintosh, Volume III",
      "author": "Apple Computer, Inc.",
      "year": 1985,
      "url": "https://vintageapple.org/inside_o/pdf/Inside_Macintosh_Volume_III_1985.pdf",
      "scope": "Published volume, chapter 2 pp. III-17–III-25: original 128K/512K hardware, CPU, RAM interleaving, ROM, video, sound, VIA, SCC and IWM. Explicit 128K buffer addresses used; 512K offsets excluded.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private published Apple reference; extracted hardware chapter inspected; draft training scan discarded in favor of publication",
        "sections": "Published volume, chapter 2 pp. III-17–III-25: original 128K/512K hardware, CPU, RAM interleaving, ROM, video, sound, VIA, SCC and IWM. Explicit 128K buffer addresses used; 512K offsets excluded."
      },
      "sha256": "4c0de9a3a4d41c41b8462b2a77aad8b95b92e1980afff165c1f986da0a81988b"
    },
    {
      "id": "hist-archimedes-a440",
      "title": "High Performance Computer Systems Model 440 Service Manual, 0476,155",
      "author": "Acorn Computers Limited",
      "year": 1988,
      "url": "https://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/A440_Service_Manual.pdf",
      "scope": "Issue 1, November 1988; pp. 5–6 specifications and pp. 10–13 system architecture: ARM, MEMC translation/DMA, VIDC, IOC and I/O bus. Original p. 10 schematic visually inspected.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private manufacturer service manual; extracted technical sections and rendered architecture diagram inspected",
        "sections": "Issue 1, November 1988; pp. 5–6 specifications and pp. 10–13 system architecture: ARM, MEMC translation/DMA, VIDC, IOC and I/O bus. Original p. 10 schematic visually inspected."
      },
      "sha256": "6bf46339092307f6af57ddda3383ae1fc9bef200503a00955274098967b6539b"
    },
    {
      "id": "hist-sun1-1982",
      "title": "Sun-1 System Reference Manual, 800-0345",
      "author": "Sun Microsystems, Inc.",
      "year": 1982,
      "url": "https://www.bitsavers.org/pdf/sun/sun1/800-0345_Sun-1_System_Reference_Manual_Jul82.pdf",
      "scope": "Version 1.0 draft, 27 July 1982; pp. 1–5 system/CPU, p. 11 Ethernet, pp. 37–39 two-level MMU, pp. 51–55 frame buffer/RasterOps. Ordinary copyright; no confidentiality banner found in inspected front matter/text.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private manufacturer PDF; extracted architecture and graphics sections inspected",
        "sections": "Version 1.0 draft, 27 July 1982; pp. 1–5 system/CPU, p. 11 Ethernet, pp. 37–39 two-level MMU, pp. 51–55 frame buffer/RasterOps. Ordinary copyright; no confidentiality banner found in inspected front matter/text."
      },
      "sha256": "8d9ee36f04687e7c9e56acae498bb073e21d237fd2329c6a1d5259835700b7df"
    },
    {
      "id": "hist-sparcstation1-field",
      "title": "SPARCstation 1 and SPARCstation 1+ Field Service Manual, 800-5146-10",
      "author": "Sun Microsystems, Inc.",
      "year": 1991,
      "url": "https://www.oldsilicon.com/sun-pizza-boxes/sparcstation-1-2/docs/SPARCstation_1p_Field_Service_Manual.pdf",
      "scope": "Cover Rev 50 dated 22 May 1990; copyright 1991. Chapter 1 pp. 6–13 and Fig. 1-4: original 20MHz SPARCstation 1 distinguished from 25MHz 1+, S4 cache/buffer/MMU, SBus, DMA and I/O. RAM paragraph internally garbled; installed total not asserted.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private public field-service PDF; extracted chapter and rendered Fig. 1-4 inspected. Confidential June 1989 programmer draft excluded entirely",
        "sections": "Cover Rev 50 dated 22 May 1990; copyright 1991. Chapter 1 pp. 6–13 and Fig. 1-4: original 20MHz SPARCstation 1 distinguished from 25MHz 1+, S4 cache/buffer/MMU, SBus, DMA and I/O. RAM paragraph internally garbled; installed total not asserted."
      },
      "sha256": "d40f92753efbe73caa3e026d165abe022c4763109f92cc91c67c8e346fc366e2"
    },
    {
      "id": "hist-sgi-gt-akeley",
      "title": "High-Performance Polygon Rendering",
      "author": "Kurt Akeley and Tom Jermoluk / Silicon Graphics",
      "year": 1988,
      "url": "https://people.csail.mit.edu/ericchan/bib/pdf/p239-akeley.pdf",
      "scope": "SIGGRAPH 1988 pp. 239–246, especially §§3.1–3.6 and original Fig. 1 (p. 242): host bus, FIFO/format conversion, five geometry engines, polygon/edge/span processors, 20 image engines, VRAM and display processors.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private designer-paper PDF; extracted technical sections and rendered original architecture figure inspected",
        "sections": "SIGGRAPH 1988 pp. 239–246, especially §§3.1–3.6 and original Fig. 1 (p. 242): host bus, FIFO/format conversion, five geometry engines, polygon/edge/span processors, 20 image engines, VRAM and display processors."
      },
      "sha256": "daeed44c0451abf244bfee62701ab88e5c173c398f44e08b62f053fe18c0601a"
    },
    {
      "id": "hist-sgi-gt-identity",
      "title": "RealityEngine Graphics — predecessor identification only",
      "author": "Kurt Akeley / Silicon Graphics",
      "year": 1993,
      "url": "https://www.cse.iitb.ac.in/~cs475/fall2016/handouts/1993--akeley--reality_engine_graphics.pdf",
      "scope": "Introduction identifies Silicon Graphics GT (1988) as second-generation predecessor; reference 11 identifies Iris 4DGT Technical Report (1988). No RealityEngine hardware is assigned to the GT record.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private designer-paper PDF; introduction and references inspected",
        "sections": "Introduction identifies Silicon Graphics GT (1988) as second-generation predecessor; reference 11 identifies Iris 4DGT Technical Report (1988). No RealityEngine hardware is assigned to the GT record."
      },
      "sha256": "76b3bf10b66d0e8ee4f03971a7ecfa6540bfc919c58afce8e37062e5d3b08e71"
    },
    {
      "id": "hist-symbolics3600-1983",
      "title": "Symbolics 3600 Technical Summary",
      "author": "Curtis B. Roads / Symbolics Documentation and Education Services",
      "year": 1983,
      "url": "https://bitsavers.org/pdf/symbolics/3600_series/3600_TechnicalSummary_Feb83.pdf",
      "scope": "February 1983; pp. 6–7 software/word format; pp. 83,88–90 stack-oriented execution, IFU/microcode and Fig. 23; pp. 93–96,100 buffers/maps/L bus; pp. 105,108 FEP and console. Selected scan pages rendered and read visually.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private scanned manufacturer summary; notices, technical prose and original instruction-pipeline diagram visually inspected",
        "sections": "February 1983; pp. 6–7 software/word format; pp. 83,88–90 stack-oriented execution, IFU/microcode and Fig. 23; pp. 93–96,100 buffers/maps/L bus; pp. 105,108 FEP and console. Selected scan pages rendered and read visually."
      },
      "sha256": "83d53ff55b102d7f1fe0c01e7efff980db8c708ea413666d7e704e033bf9b4d6"
    },
    {
      "id": "hist-lmi-lambda-service",
      "title": "LMI Lambda Field Service Manual",
      "author": "Lisp Machine, Inc.",
      "year": 1984,
      "url": "https://bitsavers.org/pdf/lmi/LMI_Lambda_Field_Service_Manual_1984.pdf",
      "scope": "1984; current for UNIX 2.10+LMI, LMI 12/5/83 Root and lboot64. pp. 3-1–3-4 component organization, NuBus/Multibus/8088 SDU, ECC memory and optional 68000; pp. 6-23–6-24 microcode/band boot selection.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private manufacturer PDF; extracted component and boot sections inspected; copyright notice has no confidentiality clause",
        "sections": "1984; current for UNIX 2.10+LMI, LMI 12/5/83 Root and lboot64. pp. 3-1–3-4 component organization, NuBus/Multibus/8088 SDU, ECC memory and optional 68000; pp. 6-23–6-24 microcode/band boot selection."
      },
      "sha256": "a3f9958165ffd28f81e639bd468d8086620e0745c45fa80de8268ace7641c4ed"
    },
    {
      "id": "hist-lmi-lambda-overview",
      "title": "LMI Lambda Machine Overview",
      "author": "Lisp Machine, Inc.",
      "year": 1982,
      "url": "https://bitsavers.org/pdf/lmi/LMI_lambdaOverview_1982.pdf",
      "scope": "pp. 1–3 (PDF 2–4): modular NuBus/Multibus system, 32-bit Lisp format, independent optional 68000 UNIX processor. Future 40-bit option is explicitly excluded.",
      "type": "Primary technical source",
      "accessed": "2026-11-02",
      "inspection": {
        "method": "Private manufacturer scan; selected original pages rendered and read visually",
        "sections": "pp. 1–3 (PDF 2–4): modular NuBus/Multibus system, 32-bit Lisp format, independent optional 68000 UNIX processor. Future 40-bit option is explicitly excluded."
      },
      "sha256": "814091672584bafce01263755848ae111be0a7c62287f037cf44534bcd96e267"
    },
    {
      "id": "hist-amiga1000-repair",
      "title": "Amiga Computer Model 1000: Assembly Level Repair and Component Level Repair",
      "author": "Commodore-Amiga, Inc.",
      "year": 1986,
      "url": "https://amiga.net.au/files/Tech_Amiga/Commodore_Amiga_Computer_Model_1000_Assembly_and_Component_Level_Repair.pdf",
      "scope": "Combined scan: 1985 PN314038-01 assembly; 1986 PN314038-02 component. Component pp. 1-1–1-4 processor/boot RAM/arbitration/system figure; pp. 1-6–1-11 Agnus, Denise and Paula. Original system block diagram visually inspected.",
      "type": "Primary technical source",
      "accessed": "2026-11-02",
      "inspection": {
        "method": "Private manufacturer service scan; extracted component descriptions and rendered original Fig. p. 1-4 inspected",
        "sections": "Combined scan: 1985 PN314038-01 assembly; 1986 PN314038-02 component. Component pp. 1-1–1-4 processor/boot RAM/arbitration/system figure; pp. 1-6–1-11 Agnus, Denise and Paula. Original system block diagram visually inspected."
      },
      "sha256": "5d5359c032ff64faeb3a37dc9c34a056859ba78670931b88240709652eaa48a8"
    },
    {
      "id": "hist-amiga-copper-1989",
      "title": "Amiga Hardware Reference Manual, revised edition",
      "author": "Commodore-Amiga, Inc.",
      "year": 1989,
      "url": "https://www.ikod.se/wp-content/uploads/2020/08/Amiga_Hardware_Reference_Manual_1989.pdf",
      "scope": "pp. 4,13–14: A1000 512KB chip-memory ceiling and Copper WAIT/MOVE/SKIP. Later A500/A2000 Fat Agnus expansion is explicitly excluded.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Private manufacturer PDF; selected architecture and Copper instruction sections inspected",
        "sections": "pp. 4,13–14: A1000 512KB chip-memory ceiling and Copper WAIT/MOVE/SKIP. Later A500/A2000 Fat Agnus expansion is explicitly excluded."
      },
      "sha256": "5117e1aada442f15ca5ca2d3637ef8dd47e6ea5962bc3e9c091f4e9a5f135006"
    },
    {
      "id": "hist-nes-noa1990",
      "title": "World Class Service Authorized Servicer Technical Training Workbook, PN21531",
      "author": "Nintendo of America, Inc.",
      "year": 1990,
      "url": "https://wiki.console5.com/tw/images/d/de/NOA_Independent_Servicer_Technical_Training_Workbook_Rev._11-90.pdf",
      "scope": "Rev. 11/90; Appendix B Control Deck CPU PC Board Schematic (PDF 96), functional sections/test points (PDF 95), notices (PDF 2–3). Original circuit and functional descriptions visually inspected. Copyright/proprietary reference-only notice; no confidentiality or nondisclosure clause.",
      "type": "Primary technical source",
      "accessed": "2026-11-02",
      "inspection": {
        "method": "Private manufacturer scan; independently drawn functional abstraction only, no reproduced schematic artwork",
        "sections": "Rev. 11/90; Appendix B Control Deck CPU PC Board Schematic (PDF 96), functional sections/test points (PDF 95), notices (PDF 2–3). Original circuit and functional descriptions visually inspected. Copyright/proprietary reference-only notice; no confidentiality or nondisclosure clause."
      },
      "sha256": "fc7e58cb2da2400a7f3706961b9939457dd7b8451133403283488f92580bb2ba"
    },
    {
      "id": "hist-nes-nakagawa-patent",
      "title": "US4799635A: System for determining authenticity of an external memory used in an information processing apparatus",
      "author": "Katsuya Nakagawa / Nintendo",
      "year": 1989,
      "url": "https://patents.google.com/patent/US4799635A/en",
      "scope": "Description of preferred embodiments, Fig. 2 discussion: cartridge program/character ROM, lock/key and CPU/PPU reset roles. Patent example CPU Z80A/PPU2C03 are not substituted for installed NES chips.",
      "type": "Primary technical source",
      "accessed": "2026-11-02",
      "inspection": {
        "method": "Public patent HTML opened and specific descriptive paragraphs inspected",
        "sections": "Description of preferred embodiments, Fig. 2 discussion: cartridge program/character ROM, lock/key and CPU/PPU reset roles. Patent example CPU Z80A/PPU2C03 are not substituted for installed NES chips."
      }
    },
    {
      "id": "parallel-seed-cray1-revc",
      "title": "CRAY-1 Hardware Reference Manual, 2240004 Revision C",
      "author": "Cray Research, Inc.",
      "year": 1977,
      "type": "Manufacturer manual · inspected HTML transcription and figure",
      "url": "https://ed-thelen.org/comp-hist/CRAY-1-HardRefMan/CRAY-1-HRM.html",
      "scope": "4 November 1977 change notice; Chapters 1–3; applies from serial 3. One 1M-word/16-bank reference configuration.",
      "accessed": "2026-11-02",
      "inspection": {
        "method": "Read revision table,computation/register descriptions,chain-slot restrictions,instruction buffers and original I/O/front-end/MCU/disk roles. Privately downloaded and visually inspected original Fig.3-1. Full-manual Bitsavers link returned404; HTML contains Chapters1–3,so later chapter detail is not claimed. HTML SHA256:662e43f9b00af0140f085eb642612913fc03ae304d9da68a3d7a41ebfc03edd3; Fig.3-1 GIF SHA256:142b1f2f8092ed78a5d5a43ffc84e870a15ccdd700d0078ecbfc90cc88528b22.",
        "sections": "4 November 1977 change notice; Chapters 1–3; applies from serial 3. One 1M-word/16-bank reference configuration."
      }
    },
    {
      "id": "parallel-seed-cdc6600",
      "title": "Parallel Operation in the Control Data 6600",
      "author": "James E. Thornton / Control Data Corporation",
      "year": 1964,
      "type": "Designer paper · original conference scan",
      "url": "https://cs.uwaterloo.ca/~mashti/cs850-f18/papers/cdc6600.pdf",
      "scope": "1964 paper, pp. 33–40; system organization,PP barrel,central registers/scoreboard and memory.",
      "accessed": "2026-11-02",
      "inspection": {
        "method": "Downloaded8-page designer paper. Read pp.33–38 and visually inspected Figs.2 and6. Ten logical peripheral processors share a physical arithmetic/distribution/assembly slot; their memories remain independent. Central scoreboard tracks register/unit/operand-trunk use separately. Scan running headers say Spring Joint Computer Conference; record asserts the1964 paper year only. SHA256:86be4ed255f3cc9c9467cad3cf1cf3cb5a1c7ef7c02baa547459375daf1fe043.",
        "sections": "1964 paper, pp. 33–40; system organization,PP barrel,central registers/scoreboard and memory."
      }
    },
    {
      "id": "parallel-atlas-basic",
      "title": "One-Level Storage System — basic machine",
      "author": "T. Kilburn, D. B. G. Edwards, M. J. Lanigan, F. H. Sumner",
      "year": 1962,
      "url": "https://gordonbell.azurewebsites.net/Computer_Structures__Readings_and_Examples/00000296.htm",
      "scope": "Original paper, reprinted in Computer Structures, Chapter 23, pp.276–278.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened author/editor-hosted transcription and its next two pages; inspected basic-machine and store descriptions. Original scan at Chilton was also opened but has no extractable text.",
        "sections": "Original paper, reprinted in Computer Structures, Chapter 23, pp.276–278."
      }
    },
    {
      "id": "parallel-atlas-stores",
      "title": "One-Level Storage System — stores and control",
      "author": "T. Kilburn, D. B. G. Edwards, M. J. Lanigan, F. H. Sumner",
      "year": 1962,
      "url": "https://gordonbell.azurewebsites.net/Computer_Structures__Readings_and_Examples/00000297.htm",
      "scope": "Original paper reprint, pp.277–278, Fig.1 and basic-machine text.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Read HTML transcription of store, arithmetic, control, and peripheral paths; followed next page for word length. OCR units are not used as timing evidence.",
        "sections": "Original paper reprint, pp.277–278, Fig.1 and basic-machine text."
      }
    },
    {
      "id": "parallel-cray2",
      "title": "CRAY-2 Computer System Functional Description, HR-2000",
      "author": "Cray Research, Inc.",
      "year": 1985,
      "url": "https://www.mrynet.com/cray/HR-2000-CRAY_2_Computer_System_Functional_Description-May_1985.OCR.pdf",
      "scope": "May 1985; §§1–2,4–5, Figures1-2 and2-1.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened archived manufacturer manual; inspected system architecture, background-processor paths, Common Memory and foreground-system sections. OCR has obvious numeric substitutions; no OCR-only timing figures are used.",
        "sections": "May 1985; §§1–2,4–5, Figures1-2 and2-1."
      }
    },
    {
      "id": "parallel-ymp",
      "title": "CRAY Y-MP Computer Systems Functional Description, HR-04001-0C",
      "author": "Cray Research, Inc.",
      "year": 1990,
      "url": "https://cray-history.net/wp-content/uploads/2021/08/HR-04001-0C_Cray_Y-MP_Computer_Systems_Functional_Description_Jun90.pdf",
      "scope": "June1990; §§1–3,6 and Y-MP8 model table pp.2-67–2-70.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened complete manufacturer manual; inspected mainframe organization, shared-register clusters, computation paths, I/O subsystem, software overview, and model832 configuration.",
        "sections": "June1990; §§1–3,6 and Y-MP8 model table pp.2-67–2-70."
      }
    },
    {
      "id": "parallel-tpu1",
      "title": "In-Datacenter Performance Analysis of a Tensor Processing Unit",
      "author": "N. P. Jouppi et al. / Google",
      "year": 2017,
      "url": "https://arxiv.org/pdf/1704.04760",
      "scope": "ISCA2017; §2, Figures1/4, software stack.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened author preprint; inspected PCIe instructions, buffer/FIFO/matrix/accumulator paths, systolic execution, DMA, and driver descriptions. Performance ratios are not transcribed.",
        "sections": "ISCA2017; §2, Figures1/4, software stack."
      }
    },
    {
      "id": "parallel-tpu4",
      "title": "TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings",
      "author": "N. P. Jouppi et al. / Google",
      "year": 2023,
      "url": "https://arxiv.org/pdf/2304.01433",
      "scope": "ISCA2023; §§2–3, Figures1–3/7.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened full author paper; inspected 4096-chip construction, host ratio, chip TensorCore/HBM organization, electrical/optical ICI boundaries, and SparseCore paths.",
        "sections": "ISCA2023; §§2–3, Figures1–3/7."
      }
    },
    {
      "id": "parallel-eyeriss",
      "title": "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks",
      "author": "Y.-H. Chen, T. Krishna, J. Emer, V. Sze",
      "year": 2016,
      "url": "https://www.rle.mit.edu/eems/wp-content/uploads/2016/02/eyeriss_isscc_2016.pdf",
      "scope": "ISSCC2016, pp.262–263; Figures14.5.2–14.5.5.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened designer-hosted paper; inspected complete architecture/dataflow text, multicast organization, scratchpads, compression, zero gating, and PE pipelines.",
        "sections": "ISSCC2016, pp.262–263; Figures14.5.2–14.5.5."
      }
    },
    {
      "id": "parallel-7600",
      "title": "CDC 7600 Preliminary Hardware Reference Manual",
      "author": "Control Data Corporation",
      "year": null,
      "url": "https://ed-thelen.org/comp-hist/cdc7600hwrm.pdf",
      "scope": "Undated preliminary scan; printed pp.1-0–1-8, Figures1-1/1-2.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded manufacturer scan; visually inspected PDF pages15–23 including rotated system/CPU figures. Foreword and page revisions identify a draft; predicted timing is deliberately excluded. Cache SHA256:2ede4c2e4e591d17cdceb77901d8b369af06b7222836f360c1e23f883dfe175d.",
        "sections": "Undated preliminary scan; printed pp.1-0–1-8, Figures1-1/1-2."
      }
    },
    {
      "id": "parallel-star",
      "title": "STAR-100 Hardware Reference Manual,60256000-09",
      "author": "Control Data Corporation",
      "year": 1975,
      "url": "https://bitsavers.org/pdf/cdc/star-100/60256000-09_STAR-100_Hardware_Reference_197512.pdf",
      "scope": "December1975 revision09; §§1–3, Figures1-1,3-1,3-5–3-13.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded complete manufacturer scan and inspected OCR for pp.1-1–1-4,2-1–2-2,3-1–3-3,3-20–3-27. The revision is mixed-page: some unchanged leaves retain08. Cache SHA256:a5c680ff24de31ff6041bda35fe8c605d159ba9c9f1d23129b91903a8d4763a8.",
        "sections": "December1975 revision09; §§1–3, Figures1-1,3-1,3-5–3-13."
      }
    },
    {
      "id": "parallel-xmp",
      "title": "CRAY X-MP Series Mainframe Reference Manual,HR-0032 RevA",
      "author": "Cray Research, Inc.",
      "year": 1984,
      "url": "https://bitsavers.trailing-edge.com/pdf/cray/CRAY_X-MP/HR-0032-CRAY_X_MP_Series_Mainframe_Reference_Manual-July_1984.OCR.pdf",
      "scope": "July1984; §§1–4, especially pp.2-4–2-5,2-10–2-13,4-9–4-12.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Inspected complete-manual OCR and selected architecture, ports, cluster, and flexible-chaining descriptions. Scope is two-CPU models22/24, not later four-CPU/EA configurations. Cache SHA256:b7b210f74553145db95c5e25013a2a9f5bfde3ba8c6f5beac8fa45016d11c1f4.",
        "sections": "July1984; §§1–4, especially pp.2-4–2-5,2-10–2-13,4-9–4-12."
      }
    },
    {
      "id": "parallel-t3d",
      "title": "CRAY T3D System Architecture Overview,HR-04033",
      "author": "Cray Research, Inc.",
      "year": 1993,
      "url": "https://bitsavers.org/pdf/cray/HR-04033_CRAY_T3D_System_Architecture_Overview_Sep93.pdf",
      "scope": "September1993 original printing; pp.1-1–1-6,3-14–3-15; Figures1-1–1-5.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded manufacturer scan; visually inspected PDF pages3,9–14,39,44–45 and network section16. No extractable body text. Graph follows the data/control keys in Figures1-3/1-4. Cache SHA256:9ad518d158572828b91f02c5ad0186a5dcb410844997faa9605c9a92ef22af15.",
        "sections": "September1993 original printing; pp.1-1–1-6,3-14–3-15; Figures1-1–1-5."
      }
    },
    {
      "id": "parallel-t3e-scott",
      "title": "Synchronization and Communication in the T3E Multiprocessor",
      "author": "Steven L. Scott / Cray Research",
      "year": 1996,
      "url": "https://ctho.org/toread/forclass/18-742/4/p26-scott.pdf",
      "scope": "ASPLOS-VII1996, pp.26–36; §§3–7, Figure1.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened full11-page designer paper and read architecture/global-communication sections. One OCR sentence mislabels the processor21264; abstract/introduction and architecture identify21164. Only local memory is cached.",
        "sections": "ASPLOS-VII1996, pp.26–36; §§3–7, Figure1."
      }
    },
    {
      "id": "parallel-t3e-system",
      "title": "Cray T3E System Architecture Overview",
      "author": "Steve Reinhardt / Cray Research",
      "year": 1996,
      "url": "https://cug.org/5-publications/proceedings_attendee_lists/1997CD/S96PROC/383_386.PDF",
      "scope": "CUG Spring1996 proceedings, pp.383–386.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened all four pages; inspected initial Alpha21164 configuration, adaptive torus, memory stream buffers, self-hosted UNICOS/mk and GigaRing I/O.",
        "sections": "CUG Spring1996 proceedings, pp.383–386."
      }
    },
    {
      "id": "parallel-aurora-arch",
      "title": "SX-Aurora TSUBASA Architecture",
      "author": "NEC Corporation",
      "year": null,
      "url": "https://www.nec.com/en/global/solutions/hpc/sx/architecture.html",
      "scope": "Architecture sections: vector cores, vector processing, cache, memory, communications.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened official architecture page; inspected all technical paragraphs. Eight-core description is scoped here to the first-generation Type10AE, with card capacity checked separately.",
        "sections": "Architecture sections: vector cores, vector processing, cache, memory, communications."
      }
    },
    {
      "id": "parallel-aurora-card",
      "title": "NEC Vector Engine Models",
      "author": "NEC Corporation",
      "year": null,
      "url": "https://www.nec.com/en/global/solutions/hpc/sx/vector_engine.html",
      "scope": "Type10AE/10CE table and first-generation package paragraph.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened current official comparison; distinguished Type10AE from Type20 and Type30. Type10AE specifies8 cores,16MB cache and48GB memory. No later-card bandwidth is attributed to Type10AE.",
        "sections": "Type10AE/10CE table and first-generation package paragraph."
      }
    },
    {
      "id": "parallel-aurora-soft",
      "title": "SX-Aurora TSUBASA Software",
      "author": "NEC Corporation",
      "year": null,
      "url": "https://www.nec.com/en/global/solutions/hpc/sx/software.html",
      "scope": "Vector Host/Vector Engine execution, Linux kernel module, compiler and parallel programming sections.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened official software page and inspected host/engine division, Linux interface, vectorizing compilers, OpenMP and MPI. Page is undated; no release date inferred.",
        "sections": "Vector Host/Vector Engine execution, Linux kernel module, compiler and parallel programming sections."
      }
    },
    {
      "id": "parallel-es1-system",
      "title": "Earth Simulator(ES1): System and hardware overview",
      "author": "JAMSTEC Earth Simulator Center",
      "year": 2002,
      "url": "https://www.jamstec.go.jp/es/en/es1/system/system.html",
      "scope": "System section and Figure1.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened original operator’s ES1 page; inspected640 processing nodes, eight APs and16GB per node, RCU/IOP and640×640 crossbar. Hardware landing page states installation completed February2002.",
        "sections": "System section and Figure1."
      }
    },
    {
      "id": "parallel-es1-ap",
      "title": "Earth Simulator(ES1): Arithmetic Processor",
      "author": "JAMSTEC Earth Simulator Center",
      "year": 2002,
      "url": "https://www.jamstec.go.jp/es/en/es1/system/arithmetic.html",
      "scope": "AP, scalar unit, vector unit descriptions.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened complete operator page; inspected scalar registers/caches,72 vector registers of256 entries, and eight sets of six vector-pipeline types.",
        "sections": "AP, scalar unit, vector unit descriptions."
      }
    },
    {
      "id": "parallel-es1-pn",
      "title": "Earth Simulator(ES1): Processor Node",
      "author": "JAMSTEC Earth Simulator Center",
      "year": 2002,
      "url": "https://www.jamstec.go.jp/es/en/es1/system/pn.html",
      "scope": "Shared main memory description.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened operator page; inspected2048 interleaved memory-bank organization.",
        "sections": "Shared main memory description."
      }
    },
    {
      "id": "parallel-es1-network",
      "title": "Earth Simulator(ES1): Interconnection Network",
      "author": "JAMSTEC Earth Simulator Center",
      "year": 2002,
      "url": "https://www.jamstec.go.jp/es/en/es1/system/in.html",
      "scope": "RCU and crossbar sections.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened full operator page; inspected RCU access and hardware subarray/indirect-transfer support.",
        "sections": "RCU and crossbar sections."
      }
    },
    {
      "id": "parallel-es1-software",
      "title": "Earth Simulator(ES1): Software overview",
      "author": "JAMSTEC Earth Simulator Center",
      "year": 2002,
      "url": "https://www.jamstec.go.jp/es/en/es1/system/software.html",
      "scope": "Programming environment links.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened original software overview; inspected explicitly listed MPI/HPF programming interfaces. OS internals are not inferred from navigation alone.",
        "sections": "Programming environment links."
      }
    },
    {
      "id": "parallel-k-system",
      "title": "K computer: System overview",
      "author": "RIKEN AICS",
      "year": null,
      "url": "https://aics.riken.jp/en/k-computer/system.html",
      "scope": "System, interconnect, I/O and programming environment sections.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened official operator overview; inspected full operation June2012, SPARC64VIIIfx, logical torus allocation and automatic file staging.",
        "sections": "System, interconnect, I/O and programming environment sections."
      }
    },
    {
      "id": "parallel-k-handout",
      "title": "K computer System Configuration and Software handout",
      "author": "RIKEN AICS",
      "year": null,
      "url": "https://aics.riken.jp/en/wp-content/uploads/system_handout.pdf",
      "scope": "Two-page operator handout, hardware diagram and software page.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened both pages; inspected node CPU/ICC/16GiB, shared6MB L2, Tofu6D topology, compute/I/O paths, two-level Lustre-based storage and MPI/OpenMP. Handout has no clear publication date.",
        "sections": "Two-page operator handout, hardware diagram and software page."
      }
    },
    {
      "id": "parallel-illiac4",
      "title": "ILLIAC IV system brochure",
      "author": "Burroughs Corporation",
      "year": 1974,
      "url": "https://archive.computerhistory.org/resources/text/Burroughs/Burroughs.ILLIACIV.1974.102624911.pdf",
      "scope": "1974 manufacturer brochure, PDF pp.3–6: major elements, routing, mode control and broadcasting.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened22-page original manufacturer brochure at CHM; read system diagram/major-elements and array-operation text. This version names B6700, unlike earlier B6500 publications. Performance marketing is excluded.",
        "sections": "1974 manufacturer brochure, PDF pp.3–6: major elements, routing, mode control and broadcasting."
      }
    },
    {
      "id": "parallel-cm1",
      "title": "The Connection Machine, doctoral dissertation",
      "author": "W. Daniel Hillis",
      "year": 1985,
      "url": "https://dspace.mit.edu/bitstream/handle/1721.1/14719/18524280-MIT.pdf",
      "scope": "Chapter4, pp.69–85; §1.5 and Chapter2.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "MIT endpoint returned429. Inspected the complete dissertation transcription at https://studyres.com/doc/1799113/the-connection-machine---dspace@mit, especially §§4.1–4.3/4.5, preserving printed locators. Figures were not used as evidence; relationships come from explicit prose. Thesis calls CM-1 a prototype being constructed; no completed-installation date inferred.",
        "sections": "Chapter4, pp.69–85; §1.5 and Chapter2."
      }
    },
    {
      "id": "parallel-cm2",
      "title": "Connection Machine Model CM-2 Technical Summary,HA87-4",
      "author": "Thinking Machines Corporation",
      "year": 1987,
      "url": "https://bitsavers.org/pdf/thinkingMachines/CM2/HA87-4_Connection_Machine_Model_CM-2_Technical_Summary_Apr1987.pdf",
      "scope": "April1987; Chapters2/4–6, especially pp.4–7 and19–22.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded65-page manufacturer report; inspected system partitioning/Nexus, programmable NEWS, bit-serial ALU,12-cube router and optional floating-point staging. Cache SHA256:189a71c2d73feb7deedd63176b3d3a75f19230dfb10d3aa36904dd491778c7c6.",
        "sections": "April1987; Chapters2/4–6, especially pp.4–7 and19–22."
      }
    },
    {
      "id": "parallel-cm5",
      "title": "The Network Architecture of the Connection Machine CM-5",
      "author": "Charles E. Leiserson et al. /Thinking Machines",
      "year": 1992,
      "url": "https://bitsavers.org/pdf/thinkingMachines/CM5/The_Network_Architecture_of_the_Connection_Machine_CM-5_Nov1992.pdf",
      "scope": "November9,1992 designer report; §§1–6, Figures1–3.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded18-page full report; inspected network interface,4-ary fat-tree, dedicated control and diagnostic networks, partitions and software model. This report explicitly limits specifications to the initial release. Cache SHA256:46b54725f83eaa0e62cc9b13de8e60e7d27561ab0f243d5119db6859cab98a10.",
        "sections": "November9,1992 designer report; §§1–6, Figures1–3."
      }
    },
    {
      "id": "parallel-mp1",
      "title": "The Design of the MasPar MP-1: A Cost Effective Massively Parallel Computer",
      "author": "John R. Nickolls /MasPar Computer Corporation",
      "year": 1990,
      "url": "https://courses.grainger.illinois.edu/cs533/sp2012/reading_list/14a.pdf",
      "scope": "Compcon Spring1990, pp.25–28; Figures1–3.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded and visually inspected all four pages; the PDF has no extractable text. Inspected ACU,PE memory/register/nibble datapath, independent load/store queue, eight-neighbor torus and three router stages. Cache SHA256:1e81c78f8cbfaeec2e54851c8ce612ee6352926c8dd7ed5214bfc0c954b7a5ec.",
        "sections": "Compcon Spring1990, pp.25–28; Figures1–3."
      }
    },
    {
      "id": "parallel-mpp",
      "title": "Architecture of a Massively Parallel Processor",
      "author": "Kenneth E. Batcher /Goodyear Aerospace",
      "year": 1980,
      "url": "https://aggregate.org/GPUCOURSE/p174-batcher.pdf",
      "scope": "1980 paper, pp.174–179; Figures1/2/4.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded six-page original designer paper; read PE bit-serial datapath, memory, programmable boundaries, redundancy, sum-or tree, three ACU controls and PDMU/reordering interfaces. Scope is the described pre-delivery design. Cache SHA256:8e0b7c7ad895c21540ac38b849164a14033a37365ac29505119ae7402172a54c.",
        "sections": "1980 paper, pp.174–179; Figures1/2/4."
      }
    },
    {
      "id": "parallel-ipsc",
      "title": "The Intel Hypercube, part1",
      "author": "Cleve Moler, iPSC development participant",
      "year": 2013,
      "url": "https://blogs.mathworks.com/cleve/2013/10/28/the-intel-hypercube-part-1/",
      "scope": "Intel Personal Supercomputer and Distributed Arrays sections.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened first-person technical retrospective; inspected model d5/d6/d7, node hardware, Cube Manager, local message-passing kernel and column-distributed algorithm. This is participant recollection, not a contemporaneous circuit manual.",
        "sections": "Intel Personal Supercomputer and Distributed Arrays sections."
      }
    },
    {
      "id": "parallel-paragon",
      "title": "Paragon XP/S Product Overview",
      "author": "Intel Corporation",
      "year": 1991,
      "url": "https://bitsavers.org/pdf/intel/supercomputer/Paragon/Intel_Paragon_XPS_Product_Overview_1991.pdf",
      "scope": "1991 overview, pp.5–12 and operating-system/programming sections.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded48-page manufacturer document; inspected basic dual-i860XP node, shared local memory, NIC/two block-transfer engines, PMRC mesh, partition roles, and software. Distinguishes the basic node from the MP node still in development. Cache SHA256:47095f2e01e61d04f268e26cdfce1de65c4332b78b36c7f1f030428864c339c7.",
        "sections": "1991 overview, pp.5–12 and operating-system/programming sections."
      }
    },
    {
      "id": "parallel-asci-red",
      "title": "An Overview of the Intel TFLOPS Supercomputer",
      "author": "Timothy G. Mattson and Greg Henry /Intel",
      "year": 1998,
      "url": "https://www.intel.com/content/dam/www/public/us/en/documents/research/1998-vol02-iss-1-intel-technology-journal.pdf",
      "scope": "Intel Technology Journal Q1,1998, first article pp.1–14; Table2 and Figures1–3.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded original60-page journal issue; read hardware/software organization, Kestrel/Eagle boards and38×32×2 mesh. The table gives4536 compute nodes and9216 total processors; sources reporting7264 often describe an earlier processor-count demonstration. Later333MHz upgrade excluded. Cache SHA256:ba0148c928812fe79803cf863aba3e61e56c6f437a04adab0ab94a93467f0dc4.",
        "sections": "Intel Technology Journal Q1,1998, first article pp.1–14; Table2 and Figures1–3."
      }
    },
    {
      "id": "parallel-bgl",
      "title": "Overview of the Blue Gene/L system architecture",
      "author": "Alan Gara et al. /IBM",
      "year": 2005,
      "url": "https://rsim.cs.uiuc.edu/arch/qual_papers/systems/19.pdf",
      "scope": "IBM Journal of Research and Development49(2/3), pp.195–212; system/network/ASIC/memory sections and Figure5.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded18-page designer article; inspected dual PPC440/FPU organization,512MB documented node,4MB eDRAM, virtual-node vs communication-coprocessor mode and five distinct network roles. Cache SHA256:7adb6daa4a84930e6388e626ef2e5528c2513da2b6022529f66e51b2433797cf.",
        "sections": "IBM Journal of Research and Development49(2/3), pp.195–212; system/network/ASIC/memory sections and Figure5."
      }
    },
    {
      "id": "parallel-bgq-hardware",
      "title": "IBM System Blue Gene Solution: Blue Gene/Q Hardware Overview and Installation Planning",
      "author": "Pamela Lembke and James Milano /IBM",
      "year": 2012,
      "url": "https://www.redbooks.ibm.com/redbooks/pdfs/sg247872.pdf",
      "scope": "IBM Redbooks SG24-7872; Chapter1 and interconnect description.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded108-page public manufacturer Redbook; read compute card, node board, midplane, rack and5D torus sections. Cache SHA256:70d68e27942780b577b33612ac2031b10ee93e45ed42b81d68e0971fe96ed8e6.",
        "sections": "IBM Redbooks SG24-7872; Chapter1 and interconnect description."
      }
    },
    {
      "id": "parallel-bgq-development",
      "title": "IBM System Blue Gene Solution: Blue Gene/Q Application Development",
      "author": "IBM Redbooks authors",
      "year": 2013,
      "url": "https://www.redbooks.ibm.com/redbooks/pdfs/sg247948.pdf",
      "scope": "SG24-7948; §§1.2–1.3,2.1,4.1; Figures1-2/2-1.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded188-page manufacturer Redbook; inspected A2 core/node memory, CNK/CIOS function shipping, L1P/switch/32MB L2, on-node SMP and no hardware sharing between nodes. Cache SHA256:a3b4d57c79c9b49746a3db95a6dbc4e4c1deebe1880faff49c77e27ab775ebd4.",
        "sections": "SG24-7948; §§1.2–1.3,2.1,4.1; Figures1-2/2-1."
      }
    },
    {
      "id": "parallel-origin",
      "title": "The SGI Origin: A ccNUMA Highly Scalable Server",
      "author": "James Laudon and Daniel Lenoski /Silicon Graphics",
      "year": 1997,
      "url": "https://www.cs.umd.edu/class/fall2019/cmsc714/readings/SGI-Origin-2000.pdf",
      "scope": "ISCA1997, pp.241–251; §§2–3, Figures1–3 and read-request flow.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded11-page designer paper; read Hub crossbar, directory protocol, fat-hypercube/SPIDER routers, global XIO/DMA and page migration. Two processors multiplex a bus but explicitly do not form a snoopy cluster. Cache SHA256:5830e453977941c8fb27aea11318151535e8ba44c6b542d53fb30640ea60763b.",
        "sections": "ISCA1997, pp.241–251; §§2–3, Figures1–3 and read-request flow."
      }
    },
    {
      "id": "parallel-ksr1",
      "title": "The KSR1: Experimentation and Modeling of Poststore,ORNL/TM-12287",
      "author": "E. Rosti, E. Smirni, T. D. Wagner, A. W. Apon, L. W. Dowdy",
      "year": 1993,
      "url": "https://www.osti.gov/servlets/purl/10154837",
      "scope": "February1993 primary experiment report; §§1–2, printed pp.1–6.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Retrieved the complete public report as OSTI text; inspected system hardware, subcache/local-cache/subpage organization, state transitions,32-cell experimental configuration and OS R1.0.5. This is a hardware-user measurement report, not a designer circuit manual; graph is limited to explicit descriptions. Cache SHA256:fccbb6664403a448af1e5c84f86160a500190aeb1f669dcc06c3971b92ca258f.",
        "sections": "February1993 primary experiment report; §§1–2, printed pp.1–6."
      }
    },
    {
      "id": "parallel-dash",
      "title": "The Stanford Dash Multiprocessor",
      "author": "Daniel Lenoski et al. /Stanford University",
      "year": 1992,
      "url": "https://rsim.cs.uiuc.edu/arch/qual_papers/arch/lenoski_dash.pdf",
      "scope": "IEEE Computer25(3),March1992,pp.63–79; prototype/software sections, Figures4–5.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded17-page designer article; inspected four-R3000 clusters, local MESI snooping, distributed directories, separate request/reply meshes, remote-access cache/pseudo-CPU and modified IRIX running on four clusters. Cache SHA256:804dfe7f6b3cb78cbbdd797f04fde09d7bc7d38516a573700fc2080f8d7f9fa4.",
        "sections": "IEEE Computer25(3),March1992,pp.63–79; prototype/software sections, Figures4–5."
      }
    },
    {
      "id": "parallel-alewife",
      "title": "The MIT Alewife Machine: Architecture and Performance",
      "author": "Anant Agarwal et al. /MIT",
      "year": 1995,
      "url": "https://dl.icdst.org/pdfs/files/b6a4a5a9672faca6f9fe12729e3baa86.pdf",
      "scope": "ISCA1995 author manuscript, §§1–3; Figures1/3 and LimitLESS/message-interface descriptions.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded12-page designer manuscript from public mirror after original project link redirected; read first-silicon32-node configuration, CMMU, software-extended directories and direct packet launch. Paper explicitly notes20MHz floating operation due to a silicon timing bug; intended33MHz not substituted. Cache SHA256:babf59c01ccd43779748a83c3100d51449cabf86c6301ce0a2d6943a6a76ba39.",
        "sections": "ISCA1995 author manuscript, §§1–3; Figures1/3 and LimitLESS/message-interface descriptions."
      }
    },
    {
      "id": "parallel-beowulf",
      "title": "Communication Overhead for Space Science Applications on the Beowulf Parallel Workstation",
      "author": "Donald J. Becker, Thomas Sterling, Daniel Savarese, Bruce Fryxell, Kevin Olson",
      "year": 1995,
      "url": "https://webhome.phy.duke.edu/~rgb/brahma/Resources/beowulf/papers/HPDC95/hpdc95.html",
      "scope": "HPDC1995 designer paper; Introduction, Beowulf Architecture and software/experiment sections.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened full designer-authored HTML paper; read16 DX4 nodes, local disks/memory, two differently wired Ethernet channels, kernel packet distribution and PVM. MPI port is future work here, not an installed feature.",
        "sections": "HPDC1995 designer paper; Introduction, Beowulf Architecture and software/experiment sections."
      }
    },
    {
      "id": "parallel-summit",
      "title": "Summit User Guide —archived system organization",
      "author": "Oak Ridge Leadership Computing Facility",
      "year": null,
      "url": "https://docs.olcf.ornl.gov/systems/summit_user_guide.html",
      "scope": "System Overview, Summit Nodes, Interconnect, Operating System and node-architecture figure.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened operator guide and privately inspected original summit_node_architecture.png. Standard512GB/16GB-per-GPU nodes distinguished from54 high-memory nodes. Figure labels CPU–CPU as X-Bus and CPU/GPU triangles as NVLink. Archive states retirement November15,2024. Cache SHA256:c7a9bab2d12babf78b3b38b7e570bab807720d78c15a92f841e3cda39a16ef28.",
        "sections": "System Overview, Summit Nodes, Interconnect, Operating System and node-architecture figure."
      }
    },
    {
      "id": "parallel-frontier",
      "title": "Frontier User Guide",
      "author": "Oak Ridge Leadership Computing Facility",
      "year": null,
      "url": "https://docs.olcf.ornl.gov/systems/frontier_user_guide.html",
      "scope": "System Overview, Compute Nodes, Interconnect, GPUs and Frontier_Node_Diagram.jpg.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened current operator guide and privately inspected the complete node diagram. Four MI250X packages contain eight independently exposed GCDs; NIC placement and CPU NUMA affinity are explicit. No changing rank or performance superlative is repeated. Cache SHA256:fc5e0c1136e7b8540e403f8af9a6203a4df69a0ae9f0a8eeb720dddfd59832f4.",
        "sections": "System Overview, Compute Nodes, Interconnect, GPUs and Frontier_Node_Diagram.jpg."
      }
    },
    {
      "id": "parallel-aurora-system",
      "title": "Aurora Machine Overview",
      "author": "Argonne Leadership Computing Facility",
      "year": 2025,
      "url": "https://docs.alcf.anl.gov/aurora/",
      "scope": "Machine overview and Compute Node table; updated February5,2025.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened official operator page despite direct cache403. Read104CPU cores, dual CPU HBM/DDR5 domains, six Max1550 GPUs, XeLink all-to-all, eight Slingshot NICs and GPUDirect-style PCIe message path. GPU internal table mixes physical/active counts; those disputed detail counts are excluded.",
        "sections": "Machine overview and Compute Node table; updated February5,2025."
      }
    },
    {
      "id": "parallel-aurora-pe",
      "title": "Aurora Programming Environment",
      "author": "Argonne Leadership Computing Facility",
      "year": 2026,
      "url": "https://docs.alcf.anl.gov/aurora/aurora-pe/",
      "scope": "Overview; updated October12,2026.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened official operator environment page; read oneAPI SDK, MPICH and Spack PE composition. Hardware dossier retains the February2025 overview as its configuration reference.",
        "sections": "Overview; updated October12,2026."
      }
    },
    {
      "id": "parallel-elcap-hardware",
      "title": "Using El Capitan Systems: Hardware Overview",
      "author": "Lawrence Livermore National Laboratory",
      "year": null,
      "url": "https://hpc.llnl.gov/documentation/user-guides/using-el-capitan-systems/hardware-overview",
      "scope": "APU, memory/coherence, node diagram and System Interconnect sections.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened operator page, cached full HTML and privately inspected node diagram. Read unified HBM3 within MI300A, six XCDs/three CCDs, four APU sockets, intra-socket hardware GPU coherence and cross-socket software GPU coherence. The latter boundary is preserved. Cache SHA256:a5b638f4d52fcccbfd69b2813008672be766022db0762ab7ab3816bfe99554a8.",
        "sections": "APU, memory/coherence, node diagram and System Interconnect sections."
      }
    },
    {
      "id": "parallel-elcap-installation",
      "title": "El Capitan platform specification",
      "author": "Lawrence Livermore National Laboratory",
      "year": null,
      "url": "https://hpc.llnl.gov/hardware/compute-platforms/el-capitan",
      "scope": "Platform table and current system description.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened official platform page; table explicitly gives2024 commissioning, four MI300A/96 CPU cores/512GiB per node, Slingshot11, TOSS4 and Flux. Current queue counts differ between prose/table, so no total login/debug count used.",
        "sections": "Platform table and current system description."
      }
    },
    {
      "id": "parallel-dgx1-v100",
      "title": "NVIDIA DGX-1 With Tesla V100 System Architecture,WP-08437-002_v01",
      "author": "NVIDIA Corporation",
      "year": 2017,
      "url": "https://images.nvidia.com/content/pdf/dgx1-v100-system-architecture-whitepaper.pdf",
      "scope": "System overview/specification; §3.1 and Figure4,p.9; network/software sections.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded43-page manufacturer whitepaper; read16GB V100 configuration, hybrid cube-mesh and GPUDirect/network discussion; visually inspected PDFp.11/Fig.4. Eight GPUs form two complete four-GPU faces with corresponding cross-face links; link multiplicity is not flattened into bandwidth. Cache SHA256:a5bedaad9aa6c3557f9658125027aa0a09fa1319c39c17b22fb88e68d9189ef9.",
        "sections": "System overview/specification; §3.1 and Figure4,p.9; network/software sections."
      }
    },
    {
      "id": "parallel-dgx1-guide",
      "title": "DGX-1 User Guide —Introduction",
      "author": "NVIDIA Corporation",
      "year": 2020,
      "url": "https://archive.docs.nvidia.com/dgx/archives/dgx1-user-guide/introduction-to-dgx1.html",
      "scope": "December2,2020 archived guide; hardware specifications and base software.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Official archive fetched successfully although web redirect failed. Inspected512GB DDR4, dual E5-2698v4, GPU options and Ubuntu/Docker/driver text. Selected16GB V100 variant; P100 and32GB V100 are separate options. Cache SHA256:4df1b6f89b304aa3108b6202e05e0ed257eecfcc0069a3223c5f0b0b1f23c6f1.",
        "sections": "December2,2020 archived guide; hardware specifications and base software."
      }
    },
    {
      "id": "parallel-dgxh100",
      "title": "NVIDIA DGX H100/H200 User Guide",
      "author": "NVIDIA Corporation",
      "year": 2026,
      "url": "https://docs.nvidia.com/dgx/dgxh100-user-guide/dgxh100-user-guide.pdf",
      "scope": "October17,2026 edition; §§1.1,1.3–1.4 and topology Figure,p.15.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded122-page current manual; selected H100640GB variant from shared H100/H200 tables and visually inspected PDFp.21/p.15 topology. Four NVSwitches and per-GPU ConnectX7 paths are preserved separately from PCIe control. Cache SHA256:239ad6be941b81e6b9cad1ca9c727c14347c5696ebd9e4d6cc4ed647c12b0918.",
        "sections": "October17,2026 edition; §§1.1,1.3–1.4 and topology Figure,p.15."
      }
    },
    {
      "id": "parallel-dgx-hopper-fabric",
      "title": "NVIDIA Fabric Manager —NVSwitch-based systems",
      "author": "NVIDIA Corporation",
      "year": null,
      "url": "https://docs.nvidia.com/hgx-platforms/fabric-manager-user-guide/index.html",
      "scope": "Third-generation NVSwitch/H100 architecture and topology table.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened manufacturer guide; read eight H100/four NVSwitch baseboard,4/5 NVLinks to individual switches, and lack of direct two-baseboard NVLink expansion in this generation. Avoided conflating NVLink generation with NVSwitch generation.",
        "sections": "Third-generation NVSwitch/H100 architecture and topology table."
      }
    },
    {
      "id": "parallel-gb200-components",
      "title": "DGX GB200 SuperPOD Reference Architecture —Components",
      "author": "NVIDIA Corporation",
      "year": 2025,
      "url": "https://docs.nvidia.com/dgx-superpod/reference-architecture-scalable-infrastructure-gb200/latest/dgx-superpod-components.html",
      "scope": "November19,2025 edition; Compute Tray, NVLink Switch Tray, Tables1–2 and Figure5.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened full manufacturer component chapter and privately inspected Figure5. Two Grace/four B200 GPUs per tray,18 trays/rack, separate ConnectX7 and BlueField3 roles, local NVMe and software management inspected. This is DGX GB200 reference configuration, not all OEM NVL72 implementations.",
        "sections": "November19,2025 edition; Compute Tray, NVLink Switch Tray, Tables1–2 and Figure5."
      }
    },
    {
      "id": "parallel-gb200-network",
      "title": "DGX GB200 SuperPOD Reference Architecture —Network Fabrics",
      "author": "NVIDIA Corporation",
      "year": 2025,
      "url": "https://docs.nvidia.com/dgx-superpod/reference-architecture-scalable-infrastructure-gb200/latest/network-fabrics.html",
      "scope": "November19,2025; Multi-node NVLink, Compute Fabric, Ethernet and OOB sections.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened full chapter; verified nine switch trays/two chips each and one GPU link to every switch chip. Distinguished72-GPU scale-up domain, InfiniBand between racks, storage/in-band Ethernet and OOB control.",
        "sections": "November19,2025; Multi-node NVLink, Compute Fabric, Ethernet and OOB sections."
      }
    },
    {
      "id": "parallel-ttda",
      "title": "Executing a Program on the MIT Tagged-Token Dataflow Architecture",
      "author": "Arvind; R. S. Nikhil",
      "year": 1990,
      "url": "https://www.cs.cmu.edu/~15740-f20/papers/arvind90.pdf",
      "scope": "IEEE Transactions on Computers39(3),pp.300–318; §§III-C,IV,VI.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded complete19-page designer paper. Read I-structure semantics and PE/multiprocessor organization, pp.313–315; rendered/inspected Figs.17–18. This is the TTDA architectural model, not the later Monsoon implementation. SHA256:9a30151dd519d4c5a89c39be139ea87eb7f365ad23087c2b68491c09efd61bcf.",
        "sections": "IEEE Transactions on Computers39(3),pp.300–318; §§III-C,IV,VI."
      }
    },
    {
      "id": "parallel-manchester-dataflow",
      "title": "The Manchester Prototype Dataflow Computer",
      "author": "J. R. Gurd; C. C. Kirkham; I. Watson",
      "year": 1985,
      "url": "https://cartheur.com/Files/manchester-data-flow.pdf",
      "scope": "CACM28(1),pp.34–52; system section pp.40–42, Figs.5,7,8; benchmark languages p.44.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Inspected indexed complete primary article text and figure descriptions. Direct mirror request returned404; no local scan was available. Critical distinction on p.42: overflow was software-emulated; the special-purpose overflow processor was still under construction.",
        "sections": "CACM28(1),pp.34–52; system section pp.40–42, Figs.5,7,8; benchmark languages p.44."
      }
    },
    {
      "id": "parallel-monsoon",
      "title": "Monsoon: an Explicit Token-Store Architecture",
      "author": "Gregory M. Papadopoulos; David E. Culler",
      "year": 1990,
      "url": "https://www.cs.cmu.edu/~18742/papers/Papadopoulos1990.pdf",
      "scope": "ISCA1990,pp.82–91; §§2–4, Fig.2.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded10-page designer paper; read ETS frame allocation, eight-stage pipeline, and actual prototype limits. Rendered Fig.2. The operational prototype lacked the pictured interprocessor connection and separate I-structure module (§4); these are not added to its graph. SHA256:e365101f3bc1bd8cd8da0856198c2a6bfe525c2f5a49fe45c1daac5b0d638005.",
        "sections": "ISCA1990,pp.82–91; §§2–4, Fig.2."
      }
    },
    {
      "id": "parallel-trips",
      "title": "Distributed Microarchitectural Protocols in the TRIPS Prototype Processor",
      "author": "K. Sankaralingam et al.",
      "year": 2006,
      "url": "https://pages.cs.wisc.edu/~karu/docs/papers/utexas/micro06-trips-proto.pdf",
      "scope": "MICRO2006; §§2–5, Figs.2–5.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded12-page designer paper and read tile counts, operand/control micronetworks, memory organization, and distributed fetch/commit protocols. Distinguishes physical five instruction banks from the paper’s logical64KB instruction-cache summary. SHA256:a94e2d2215a8ac3381c8fbfa03f9f55536c9292bae6e7546ee8cc6e814fbda5f.",
        "sections": "MICRO2006; §§2–5, Figs.2–5."
      }
    },
    {
      "id": "parallel-wavescalar",
      "title": "WaveScalar",
      "author": "Steven Swanson; Ken Michelson; Andrew Schwerin; Mark Oskin",
      "year": 2003,
      "url": "https://www.cs.cmu.edu/~18742/papers/Swanson2003.pdf",
      "scope": "MICRO2003; §§3–4,6, Fig.3.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded12-page original proposal; read wave tags, memory-operation links, PE matching, cluster buses, proposed store-buffer alternatives and simulation sections. Hardware described as a design that could be built in5–10years, not an existing chip. SHA256:805eea666fc314e64cf2a7b801d5d9b0ca23e27e7bb262d271618ad696b4826e.",
        "sections": "MICRO2003; §§3–4,6, Fig.3."
      }
    },
    {
      "id": "parallel-t800",
      "title": "IMS T800 transputer — Preliminary Data",
      "author": "INMOS",
      "year": 1987,
      "url": "https://bitsavers.org/components/inmos/transputer/Inmos_IMS_T800_Transputer_preliminary_datasheet_Apr87.pdf",
      "scope": "April1987,42 1082 00; feature page and printedp.2 block diagram.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded scanned manufacturer datasheet; extracted text was empty. Rendered/visually inspected PDFpages1 and4 (printedp.2), including internal bus, FPU, RAM, memory interface, independent link interfaces and service signals. Only these inspected pages underpin internal graph. SHA256:3a7168effc0017ce766252d8c10ea53043a283b23b3c58a437bc0c1f48f0d08c.",
        "sections": "April1987,42 1082 00; feature page and printedp.2 block diagram."
      }
    },
    {
      "id": "parallel-b401",
      "title": "Transputer Development and iq Systems Databook,Second Edition",
      "author": "INMOS",
      "year": 1991,
      "url": "https://www.bitsavers.org/components/inmos/transputer/72-TRN-219-01_Transputer_Development_and_Iq_Systems_Databook_Second_Edition_1991.pdf",
      "scope": "72-TRN-219-01; Chapter17,pp.149–154; software descriptions.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded manufacturer book and read B401 engineering data, memory map, pin table and ordering table. B401-3 is the T800-20 variant with32KB external SRAM; B403 is a different module. Chapter17 carries December1990 component revision within1991 book. SHA256:0d9b7beca9162a00b2c913c1b3cf35a529aae8f7f07e48b0ea7bae39e834a0a4.",
        "sections": "72-TRN-219-01; Chapter17,pp.149–154; software descriptions."
      }
    },
    {
      "id": "parallel-iwarp",
      "title": "Supporting Systolic and Memory Communication in iWarp",
      "author": "Shekhar Borkar et al.",
      "year": 1990,
      "url": "https://people.eecs.berkeley.edu/~kubitron/cs258/handouts/papers/p70-borkar.pdf",
      "scope": "ISCA1990,pp.70–81; §§1,4–7, Figs.1,5,7.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded12-page Intel/CMU designer paper. Read three-agent organization, physical/logical channels, systolic gates, spooling and pathway control. First silicon was December1989;8×8 demonstration systems were future deliveries in this paper. SHA256:847e99e13ae00e4d45fcdfeb2e83a77f46a862fd7c6679b8416030fc3f2d9ef1.",
        "sections": "ISCA1990,pp.70–81; §§1,4–7, Figs.1,5,7."
      }
    },
    {
      "id": "parallel-raw",
      "title": "Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams",
      "author": "Michael Bedford Taylor et al.",
      "year": 2004,
      "url": "https://www.princeton.edu/~wentzlaf/documents/Taylor.2004.ISCA.Raw.pdf",
      "scope": "ISCA2004; §§1–3, Fig.1.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded12-page designer paper. Read actual prototype/chip receipt, tile pipelines, four meshes, static routing instructions, dynamic-network trust/deadlock roles and direct I/O. Rendered/inspected Fig.1. Performance evaluation mainly uses a hardware-validated simulator (§4.1), not every result measured on silicon. SHA256:8629087e353f271926463f780f2d9b90b446b6652e75ba34809c3fa63d12a02a.",
        "sections": "ISCA2004; §§1–3, Fig.1."
      }
    },
    {
      "id": "parallel-cs2",
      "title": "Cerebras Architecture Deep Dive: First Look Inside the Hardware/Software Co-Design for Deep Learning",
      "author": "Sean Lie",
      "year": 2023,
      "url": "https://8968533.fs1.hubspotusercontent-na2.net/hubfs/8968533/IEEE%20Micro%202023-03%20Hot%20Chips%2034%20Cerebras%20Architecture%20Deep%20Dive.pdf",
      "scope": "IEEE Micro43(3); preprint pp.2–9, Figs.2–8,10–13.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded14-page designer article; read core SRAM banking, DSRs, microthreads, five-port colored mesh and weight streaming. Article current-version date15May2023; WSE-2 release identified as2021. SHA256:bafe1375a6e35920303e2b42daa1a0eb2e7fe7cfdd41fe299d06acf528b46d59.",
        "sections": "IEEE Micro43(3); preprint pp.2–9, Figs.2–8,10–13."
      }
    },
    {
      "id": "parallel-cs2-streaming",
      "title": "Cerebras Architecture Deep Dive — weight streaming",
      "author": "Sean Lie / Cerebras",
      "year": 2023,
      "url": "https://www.cerebras.ai/blog/cerebras-architecture-deep-dive-first-look-inside-the-hw-sw-co-design-for-deep-learning",
      "scope": "Updated22May2023; Weight Streaming and Scale-up sections.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened complete designer-authored article. Inspected MemoryX weight/gradient directions and local-activation reduction example. Scope is the documented weight-streaming configuration, not every CS-2 deployment.",
        "sections": "Updated22May2023; Weight Streaming and Scale-up sections."
      }
    },
    {
      "id": "parallel-m2000",
      "title": "IPU-Machine:M2000 Datasheet,Version1.0",
      "author": "Graphcore",
      "year": 2020,
      "url": "https://docs.graphcore.ai/projects/graphcore-ipu-m2000-datasheet/en/1.0.0/_downloads/3324c02e071a26a432e11753f3fd092f/IPU-Machine_M2000_datasheet.pdf",
      "scope": "30September2020 release; §§2,3.1.1,3.1.5,3.2.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened indexed complete manufacturer PDF body/figure descriptions after live endpoint502. Read revision table, standalone host/RNIC diagram, fabric/synchronization and default2×64GB configuration. Later live datasheets change available DDR capacities; this version remains fixed.",
        "sections": "30September2020 release; §§2,3.1.1,3.1.5,3.2."
      }
    },
    {
      "id": "parallel-gc200",
      "title": "Introducing2nd Generation IPU Systems for AI at Scale",
      "author": "Nigel Toon / Graphcore",
      "year": 2020,
      "url": "https://www.graphcore.ai/posts/introducing-second-generation-ipu-systems-for-ai-at-scale",
      "scope": "15July2020; Compute,Data,Communication sections.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened full manufacturer article. Read1472-core GC200, tile-local SRAM, Exchange Memory, GC4000 gateway and Poplar graph compilation. Commissioned third-party analyst PDFs were inspected for provenance but excluded from the atlas evidence set.",
        "sections": "15July2020; Compute,Data,Communication sections."
      }
    },
    {
      "id": "parallel-ipu-bsp",
      "title": "Optimising IPU Applications Using the PopVision Analysis Tools",
      "author": "Chris Gray / Graphcore",
      "year": 2022,
      "url": "https://www.graphcore.ai/posts/optimising-ipu-applications-using-the-popvision-analysis-tools",
      "scope": "6April2022; Discovering the problem, BSP execution trace description.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened full manufacturer case study. Read compute/sync/exchange phases and implications of one tile serializing a sort. Used only for the BSP execution model, not a particular deployment’s performance.",
        "sections": "6April2022; Discovering the problem, BSP execution trace description."
      }
    },
    {
      "id": "parallel-groq-tsp",
      "title": "Think Fast: A Tensor Streaming Processor for Accelerating Deep Learning Workloads",
      "author": "Dennis Abts et al.",
      "year": 2020,
      "url": "https://pkamath.com/publications/papers/tsp-isca20.pdf",
      "scope": "ISCA2020,pp.145–158; §§I–III, Figs.2–7.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened indexed full designer paper and inspected architecture/instruction/memory body plus figure descriptions. Direct author mirror has expired TLS certificate; vendor old PDF path404. Evidence remains the first-generation2020 paper, not later LPU products or multiprocessors.",
        "sections": "ISCA2020,pp.145–158; §§I–III, Figs.2–7."
      }
    },
    {
      "id": "parallel-anton2",
      "title": "Anton2: Raising the Bar for Performance and Programmability in a Special-Purpose Molecular Dynamics Supercomputer",
      "author": "David E. Shaw et al.",
      "year": 2014,
      "url": "https://doczz.net/doc/8102859/anton-2--raising-the-bar-for-performance-and-programmabil...",
      "scope": "SC14,pp.41–53; §§III–V, Figs.3–6.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Read full mirrored primary paper transcription and figure descriptions, corroborated title/DOI10.1109/SC.2014.9 on designer publication list. Inspected flex/HTIS hierarchy, counted writes, dispatch and torus. Mirror is HTML transcription rather than a verified local scan.",
        "sections": "SC14,pp.41–53; §§III–V, Figs.3–6."
      }
    },
    {
      "id": "parallel-grape6",
      "title": "GRAPE-6: Massively-Parallel Special-Purpose Computer for Astrophysical Particle Simulations",
      "author": "Junichiro Makino; Toshiyuki Fukushige; Masaki Koga; Ken Namura",
      "year": 2003,
      "url": "https://arxiv.org/pdf/astro-ph/0310702",
      "scope": "2003 designer paper; §§2–4, Figs.1–7.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded25-page primary paper. Read actual4-cluster/64-board architecture,32 chips/board, predictor, force/derivative pipelines and hierarchical broadcast/reduction. This supersedes the authors’ earlier12-cluster proposal. SHA256:c36c56ab6f26bfde3d12a547fa73d320993a1cd39c6784a48e69fb062792c271.",
        "sections": "2003 designer paper; §§2–4, Figs.1–7."
      }
    },
    {
      "id": "parallel-am2045",
      "title": "Structural Object Programming Model: Enabling Efficient Development on Massively Parallel Architectures",
      "author": "Mike Butts; Laurent Bonetto; Brad Budlong; Paul Wasson",
      "year": 2008,
      "url": "https://archive.ll.mit.edu/HPEC/agendas/proc08/Day3/34-Butts-Presentation.pdf",
      "scope": "HPEC September2008; slides17–24,26–32.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded34-slide designer presentation. Read channel backpressure, bric architecture, production chip counts and toolchain. Rendered/inspected slide21. Production336 processors differs from earlier360-processor descriptions; no mixing. SHA256:a1c37620b637d5071d9b60a7d7fc0d5a4abe56500147f938948c853c839df9d9.",
        "sections": "HPEC September2008; slides17–24,26–32."
      }
    },
    {
      "id": "parallel-upmem-p21",
      "title": "Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture",
      "author": "Juan Gómez-Luna; Izzat El Hajj; Ivan Fernandez; Christina Giannoula; Geraldo F. Oliveira; Onur Mutlu",
      "year": 2022,
      "url": "https://arxiv.org/pdf/2105.03814",
      "scope": "arXiv2105.03814v7,4May2022; §§2.1–2.3, Figs.1–3, Table1.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded39-page primary hardware experiment. Read measured P21 machine, DPU pipeline/memory transfers and host-mediated inter-DPU communication. Four unusable DPUs reduce2560 nominal to2556 operational. SDK2021.1.1; not a claim about all UPMEM generations. SHA256:6cc38e3bdb512ab77fad160b5029ade53856b64bde73c2b1cdd9e2fe4f846e15.",
        "sections": "arXiv2105.03814v7,4May2022; §§2.1–2.3, Figs.1–3, Table1."
      }
    },
    {
      "id": "parallel-hbm-pim",
      "title": "Introducing Real-world HBM-PIM Powered System for Memory-bound Applications",
      "author": "Sukhan Lee / Samsung Electronics DRAM Design Team",
      "year": null,
      "url": "https://events.safari.ethz.ch/isca-pim-tutorial/lib/exe/fetch.php?media=introducing_real-world_hbm-pim_powered_system_for_memory-bound_applications.pdf",
      "scope": "Public ISCA PIM tutorial; PDFslides5–7,12–16; source cites2021 silicon papers.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded39-page manufacturer tutorial; read fabricated Aquabolt-XL, unmodified host controllers, bank-boundary SIMD execution and U280 two-stack system. Rendered/inspected PDFslide6 bank/FPU paths. No publication date visible on title; hardware event dates separately identified. SHA256:d94bcee68699415765f3fa751e2b7a56490c568968c42ca3915bbdf845b1fc20.",
        "sections": "Public ISCA PIM tutorial; PDFslides5–7,12–16; source cites2021 silicon papers."
      }
    },
    {
      "id": "parallel-hbm-pim-model",
      "title": "PIMSimulator — hardware description and programming guide",
      "author": "Samsung SAITPublic contributors",
      "year": null,
      "url": "https://github.com/SAITPublic/PIMSimulator",
      "scope": "README §§2.1–2.4,4.2; dev branch snapshot1November2026.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened full official repository README. Inspected bank-pair placement, CRF/GRF/SRF model, command-triggered execution, and host programming steps. This is a simulator description; its detailed capacities are not silently substituted for measured boards.",
        "sections": "README §§2.1–2.4,4.2; dev branch snapshot1November2026."
      }
    },
    {
      "id": "parallel-sx2-lanl",
      "title": "The Performance of the NEC SX-2 and Cray X-MP Supercomputers",
      "author": "Olaf M. Lubeck; James W. Moore; Raul Mendez",
      "year": 1987,
      "url": "https://www.osti.gov/servlets/purl/5046371",
      "scope": "LA-UR-87-227; §2 and Fig.1; measurements December1985–October1986.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded official full-report OCR text and read architecture, measurement scope and manufacturer acknowledgments. Fig.1 is explicitly reprinted from Furukatsu/Watanabe/Kondo’s1984 NEC designer article. OCR/other sources disagree on memory banking, so no bank count is asserted. SHA256:066dab0624444ac1ab8c3910ee78b78bd7521f0c4a884eb8df60156272ad7c45.",
        "sections": "LA-UR-87-227; §2 and Fig.1; measurements December1985–October1986."
      }
    },
    {
      "id": "parallel-vp200-anl",
      "title": "Comparison of the CRAY X-MP-4,Fujitsu VP-200,and Hitachi S-810/20: An Argonne Perspective",
      "author": "Jack J. Dongarra; Alan Hinds",
      "year": 1985,
      "url": "https://digital.library.unt.edu/ark:/67531/metadc282753/m2/1/high_res_d/metadc282753.pdf",
      "scope": "ANL-85-19,October1985; §2.2,Fig.2,§§3.4,6.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded48-page original benchmark report; read VP architecture,64MB tested memory, scalar cache and two bidirectional vector-memory pipes. Scope notes US Amdahl configurations in some comparisons; machine identity kept separate from maximum options. No Hitachi inference tables used. SHA256:63141ed2c7dfea8f5bfbaedd8c4402bce6fb3f1b93eb5bf5c2239b63069c67dd.",
        "sections": "ANL-85-19,October1985; §2.2,Fig.2,§§3.4,6."
      }
    },
    {
      "id": "parallel-vp200-miura",
      "title": "FACOM Vector Processor System: VP-100/VP-200 — Current Status and Performance Measurements",
      "author": "Kenichi Miura / Fujitsu",
      "year": 1984,
      "url": "https://lss.fnal.gov/conf/C840508/C840508.pdf",
      "scope": "Guanajuato1984 proceedings,pp.317–319; Tables2–3 and Q&A.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened indexed complete proceedings and read the Fujitsu-authored contribution. Table3 identifies Numazu VP-200 with64MB and listed M-series front ends; Table2 identifies real applications. Direct PDF cache request403; indexed body accessible.",
        "sections": "Guanajuato1984 proceedings,pp.317–319; Tables2–3 and Q&A."
      }
    },
    {
      "id": "parallel-hitachi-s810",
      "title": "Supercomputer HITAC S-810 Array Processor System",
      "author": "Toshihiko Odaka; Shigeo Nagashima; Shun Kawabe; Hiroshi Murayama; Fumio Goto / Hitachi",
      "year": 1983,
      "url": "https://www.hitachihyoron.com/jp/pdf/1983/08/1983_08_03.pdf",
      "scope": "Hitachi Review65(8),August1983,pp.541–546; §§3–6,Figs.3–8.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded6-page Japanese designer article; read indexed Japanese body/figures with OCR cross-check. Fig.8 depicts Model10; Model20 doubling is stated in §5.2, so graph aggregates arithmetic without copying Model10 unit counts. Final paragraph describes planned second-half1983 shipment. SHA256:3713d60a71ba8d4fe999642011469c0a44460eec1e20dc4e755eeded197ec828.",
        "sections": "Hitachi Review65(8),August1983,pp.541–546; §§3–6,Figs.3–8."
      }
    },
    {
      "id": "parallel-sequent-s2000",
      "title": "Sequent Symmetry2000 Hardware Maintenance",
      "author": "Sequent Educational Services",
      "year": 1991,
      "url": "https://bitsavers.org/pdf/sequent/1003-54362-00_Sequent_Symmetry_2000_Hardware_Maintenance_1991.pdf",
      "scope": "1003-54362-00; pp.1.9,2.4–2.15,2.27–2.31.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded230-page manufacturer training manual. Read printed text and rendered system,SSM,andprocessor diagrams pp.2.4,2.9,2.13. Handwritten student annotations ignored. Does not justify a named cache-coherence protocol. SHA256:deb3ec45773c4f12831256c96c0b44ee372b865dc4d4a0fa7c34ccefa7a4fff1.",
        "sections": "1003-54362-00; pp.1.9,2.4–2.15,2.27–2.31."
      }
    },
    {
      "id": "parallel-dima-2016",
      "title": "A481pJ/decision3.4Mdecision/s Multifunctional Deep In-memory Inference Processor using Standard6T SRAM Array",
      "author": "Mingu Kang; Sujan Gonugondla; Ameya Patil; Naresh Shanbhag",
      "year": 2016,
      "url": "https://arxiv.org/pdf/1610.07501",
      "scope": "arXiv1610.07501v1,24October2016; pp.2–5,Figs.1–4,6–7.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded12-page primary prototype report; read measured65nm16KB SRAM core, four-stage mixed-signal inference, separate normal read/write path and multi-bank estimates. Rendered/inspected Fig.2. Measured one-bank results distinguished from estimated multi-bank savings. SHA256:ba8a4fde2a4b095395d36b0292e4f290b962d43ae65b94798e023cf4ceefbffc.",
        "sections": "arXiv1610.07501v1,24October2016; pp.2–5,Figs.1–4,6–7."
      }
    },
    {
      "id": "parallel-m1076",
      "title": "M1076 Analog Matrix Processor Product Brief,v202106-1",
      "author": "Mythic",
      "year": 2021,
      "url": "https://mythic.ai/wp-content/uploads/2022/03/M1076-AMP-Product-Brief-v1.0-1.pdf",
      "scope": "June2021 revision,pp.1–2.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Opened indexed complete manufacturer brief and host/card diagram. Direct old PDF path404. Read76 tiles,flash weight storage,digital tile companions,PCIe and supported workflow. New2026 M1 marketing and confidential2022 slides are not evidence for this product.",
        "sections": "June2021 revision,pp.1–2."
      }
    },
    {
      "id": "parallel-m1076-codasip",
      "title": "Mythic Case Study",
      "author": "Codasip",
      "year": 2022,
      "url": "https://codasip.com/wp-content/uploads/2021/03/Codasip_case-study_Mythic.pdf",
      "scope": "PublishedFebruary2022; §§1,3,pp.2–4.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Downloaded6-page supplier integration case study; read exactM1076 core requirements,scoreboard,workload commands and customRV32IC configuration. Rendered/inspected p.2 Mythic-provided tile diagram. Its loose “over80” replication wording is not used to override manufacturer76 tiles. SHA256:ad6f1230c8acad88583aa931a10f337aa4f655325173024d6ce669482c6ea7e9.",
        "sections": "PublishedFebruary2022; §§1,3,pp.2–4."
      }
    },
    {
      "id": "seed-s360-princops",
      "title": "IBM System/360 Principles of Operation, A22-6821-0",
      "author": "IBM",
      "year": 1964,
      "url": "https://bitsavers.org/pdf/ibm/360/princOps/A22-6821-0_360PrincOps.pdf",
      "scope": "Printed/PDF pp. 7–9, 15, 20–22; Figures 1, 4, 5 and 20. Family logical organization, not a model-specific datapath.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Selected PDF pages extracted; cited organization figures visually inspected where present",
        "sections": "Printed/PDF pp. 7–9, 15, 20–22; Figures 1, 4, 5 and 20. Family logical organization, not a model-specific datapath.",
        "sha256": "7618524e58b0299de72dc92852d4aeed244b69446736f56b6dec2c065f5553e9"
      }
    },
    {
      "id": "seed-a64fx-manual",
      "title": "A64FX Microarchitecture Manual, English 1.8.1",
      "author": "Fujitsu",
      "year": 2022,
      "url": "https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Microarchitecture_Manual_en_1.8.1.pdf",
      "scope": "30 November 2022; pp. 12–14, §§1.1–1.3, Figure 1-1 and Tables 1-1/1-2. Public microarchitecture release.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Selected PDF pages extracted; cited organization figures visually inspected where present",
        "sections": "30 November 2022; pp. 12–14, §§1.1–1.3, Figure 1-1 and Tables 1-1/1-2. Public microarchitecture release.",
        "sha256": "c71d289e4770b4f1c9813103f3c9bc87688cef921c5dfb4667bdf127db3642d2"
      }
    },
    {
      "id": "seed-fugaku-system",
      "title": "Fugaku system configuration",
      "author": "RIKEN R-CCS",
      "year": null,
      "url": "https://www.r-ccs.riken.jp/fugaku/system/",
      "scope": "Node specifications; Tofu D; storage and system software. Japanese technical sections inspected; not a current ranking claim.",
      "type": "Operator technical specifications",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Web-open technical tables and interconnect description",
        "sections": "Node performance, Tofu Interconnect D, storage, system software"
      }
    },
    {
      "id": "seed-d2nn-paper",
      "title": "All-Optical Machine Learning Using Diffractive Deep Neural Networks — author manuscript",
      "author": "X. Lin et al.",
      "year": 2018,
      "url": "https://arxiv.org/pdf/1804.08711",
      "scope": "Author manuscript v2; pp. 6–7 and 17–18, Figures 1–2. Training, fixed phase layers, and experimental THz generation/detection inspected.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Selected PDF pages extracted; cited organization figures visually inspected where present",
        "sections": "Author manuscript v2; pp. 6–7 and 17–18, Figures 1–2. Training, fixed phase layers, and experimental THz generation/detection inspected.",
        "sha256": "da29cac392c286d4fa12ec35097f157c9e51c36531142e093814b7c80305fdaf"
      }
    },
    {
      "id": "seed-hala-announcement",
      "title": "Hala Point system announcement — official Intel release PDF",
      "author": "Intel",
      "year": 2024,
      "url": "https://d1io3yog0oux5.cloudfront.net/_e934f4596bf86b98821803b537ed1f05/intel/news/2024-04-17_Intel_Builds_World_s_Largest_Neuromorphic_System_1691.pdf",
      "scope": "17 April 2024; pp. 1–3, especially “About Hala Point” and benchmark footnote 2. Disclosed hierarchy, not a board-level topology.",
      "type": "Primary technical source",
      "accessed": "2026-11-01",
      "inspection": {
        "method": "Selected PDF pages extracted; cited organization figures visually inspected where present",
        "sections": "17 April 2024; pp. 1–3, especially “About Hala Point” and benchmark footnote 2. Disclosed hierarchy, not a board-level topology.",
        "sha256": "8a3c205e04d9822b2878a082e6e7152b79809257429f36543a5c195005d501b3"
      }
    }
  ],
  "systems": [
    {
      "status": "dossier",
      "aliases": [],
      "models": [
        "continuous"
      ],
      "sources": [
        "seed-bush-1931-detailed"
      ],
      "id": "differential-analyzer",
      "name": "MIT Differential Analyzer",
      "organization": "Massachusetts Institute of Technology",
      "year": 1931,
      "yearLabel": "1931 paper",
      "kind": "Experimental machine",
      "paradigms": [
        "analog",
        "unconventional"
      ],
      "architectures": [
        "analog-integrator",
        "mechanical"
      ],
      "substrates": [
        "mechanical"
      ],
      "summary": "Geared shafts and torque-amplified integrators solve configured differential equations.",
      "config": "Six-integrator 1931 machine; Fig. 7 two-integrator falling-body setup: x″ + kx′ + g = 0.",
      "insight": "How does a physical variable stand in for a mathematical variable?",
      "fields": {
        "state": {
          "value": "Shaft rotation and integrator carriage displacement",
          "source": "seed-bush-1931-detailed",
          "locator": "§§4–6"
        },
        "compute": {
          "value": "Six disc integrators; two used in Fig. 7",
          "source": "seed-bush-1931-detailed",
          "locator": "§6; Fig. 7"
        },
        "memory": {
          "value": "Initial carriage positions and evolving mechanical state",
          "source": "seed-bush-1931-detailed",
          "locator": "§5 pp. 457–458"
        },
        "control": {
          "value": "Gear connections, ratios, signs and motor start",
          "source": "seed-bush-1931-detailed",
          "locator": "§4; Fig. 7"
        },
        "io": {
          "value": "Input tables and two recording pencils",
          "source": "seed-bush-1931-detailed",
          "locator": "§4; §8"
        },
        "software": {
          "value": "Equation-specific physical setup",
          "source": "seed-bush-1931-detailed",
          "locator": "§5"
        },
        "workload": {
          "value": "Ordinary differential equations; falling-body example",
          "source": "seed-bush-1931-detailed",
          "locator": "§5"
        }
      },
      "gaps": [
        "Individual gears and amplifier shafts are aggregated.",
        "Backlash, scale and loading affect accuracy; later machines differ."
      ],
      "diagram": {
        "title": "Two integrators close the falling-body feedback loop",
        "width": 1020,
        "height": 500,
        "scope": "Fig. 7 dependencies; torque amplification aggregated; signs include gearing.",
        "nodes": [
          {
            "id": "time",
            "label": "Time-shaft motor",
            "subtitle": "INDEPENDENT VARIABLE",
            "text": "Drives the t shaft.",
            "x": 25,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-bush-1931-detailed",
            "locator": "§4; Fig. 7",
            "control": true
          },
          {
            "id": "setup",
            "label": "Initial carriage settings",
            "subtitle": "BOUNDARY CONDITIONS",
            "text": "Sets x(0) and initial velocity.",
            "x": 265,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-bush-1931-detailed",
            "locator": "§5 pp. 457–458",
            "control": true
          },
          {
            "id": "gravity",
            "label": "Input-table index g",
            "subtitle": "CONSTANT PARAMETER",
            "text": "Supplies gravitational term.",
            "x": 505,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-bush-1931-detailed",
            "locator": "§5 p. 457",
            "control": false
          },
          {
            "id": "drag",
            "label": "Ratio gearing k",
            "subtitle": "DRAG TERM",
            "text": "Forms k times velocity.",
            "x": 745,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-bush-1931-detailed",
            "locator": "§5; Fig. 7",
            "control": false
          },
          {
            "id": "sum",
            "label": "Adder / signed connection",
            "subtitle": "k x′ + g",
            "text": "Forms the acceleration input.",
            "x": 745,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-bush-1931-detailed",
            "locator": "§4; Fig. 7",
            "control": false
          },
          {
            "id": "velocity",
            "label": "Integrator II",
            "subtitle": "VELOCITY UPDATE",
            "text": "Integrates signed acceleration.",
            "x": 505,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-bush-1931-detailed",
            "locator": "Fig. 7",
            "control": false
          },
          {
            "id": "torque",
            "label": "Torque amplifiers",
            "subtitle": "POWER ASSIST",
            "text": "Drives loads from weak rollers.",
            "x": 265,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-bush-1931-detailed",
            "locator": "§6; Figs. 10–11",
            "control": false
          },
          {
            "id": "position",
            "label": "Integrator I",
            "subtitle": "POSITION UPDATE",
            "text": "Integrates velocity.",
            "x": 25,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-bush-1931-detailed",
            "locator": "Fig. 7",
            "control": false
          },
          {
            "id": "table",
            "label": "Output-table carriage",
            "subtitle": "TIME AXIS",
            "text": "Advances plotting paper coordinates.",
            "x": 25,
            "y": 380,
            "w": 180,
            "h": 66,
            "source": "seed-bush-1931-detailed",
            "locator": "§4; Fig. 7",
            "control": false
          },
          {
            "id": "pencils",
            "label": "Two recording pencils",
            "subtitle": "x(t) AND x′(t)",
            "text": "Plots position and velocity.",
            "x": 265,
            "y": 380,
            "w": 180,
            "h": 66,
            "source": "seed-bush-1931-detailed",
            "locator": "§5 p. 457",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "time",
            "to": "velocity",
            "type": "data",
            "source": "seed-bush-1931-detailed",
            "locator": "Fig. 7",
            "label": "integration variable"
          },
          {
            "from": "time",
            "to": "position",
            "type": "data",
            "source": "seed-bush-1931-detailed",
            "locator": "Fig. 7",
            "label": "integration variable"
          },
          {
            "from": "time",
            "to": "table",
            "type": "data",
            "source": "seed-bush-1931-detailed",
            "locator": "Fig. 7",
            "label": ""
          },
          {
            "from": "setup",
            "to": "velocity",
            "type": "control",
            "source": "seed-bush-1931-detailed",
            "locator": "§5 pp. 457–458",
            "label": ""
          },
          {
            "from": "setup",
            "to": "position",
            "type": "control",
            "source": "seed-bush-1931-detailed",
            "locator": "§5 pp. 457–458",
            "label": ""
          },
          {
            "from": "gravity",
            "to": "sum",
            "type": "data",
            "source": "seed-bush-1931-detailed",
            "locator": "Fig. 7",
            "label": ""
          },
          {
            "from": "drag",
            "to": "sum",
            "type": "data",
            "source": "seed-bush-1931-detailed",
            "locator": "Fig. 7",
            "label": ""
          },
          {
            "from": "sum",
            "to": "velocity",
            "type": "data",
            "source": "seed-bush-1931-detailed",
            "locator": "Fig. 7",
            "label": "signed input"
          },
          {
            "from": "velocity",
            "to": "torque",
            "type": "data",
            "source": "seed-bush-1931-detailed",
            "locator": "§6",
            "label": ""
          },
          {
            "from": "torque",
            "to": "drag",
            "type": "data",
            "source": "seed-bush-1931-detailed",
            "locator": "Fig. 7; §6",
            "label": "velocity feedback"
          },
          {
            "from": "torque",
            "to": "position",
            "type": "data",
            "source": "seed-bush-1931-detailed",
            "locator": "Fig. 7; §6",
            "label": ""
          },
          {
            "from": "torque",
            "to": "pencils",
            "type": "data",
            "source": "seed-bush-1931-detailed",
            "locator": "Fig. 7; §6",
            "label": "velocity"
          },
          {
            "from": "position",
            "to": "pencils",
            "type": "data",
            "source": "seed-bush-1931-detailed",
            "locator": "Fig. 7",
            "label": "position"
          },
          {
            "from": "table",
            "to": "pencils",
            "type": "association",
            "source": "seed-bush-1931-detailed",
            "locator": "§8",
            "label": "common carriage"
          }
        ]
      },
      "researchDepth": "architecture-dossier",
      "originalCandidate": "MIT Differential Analyzer"
    },
    {
      "status": "dossier",
      "aliases": [
        "Electronic Numerical Integrator and Computer"
      ],
      "models": [
        "register"
      ],
      "sources": [
        "hist-seed-eniac-burks-inspected"
      ],
      "id": "eniac",
      "name": "ENIAC",
      "organization": "Moore School / U.S. Army",
      "year": 1946,
      "yearLabel": "Original 1946 external programming mode, documented in 1947",
      "kind": "Built system",
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "configured",
        "accumulator"
      ],
      "substrates": [
        "vacuum-tube"
      ],
      "summary": "Clocked decimal pulse arithmetic is distributed among accumulators and specialized units; switch settings and chains of local program controls establish operations, repetition and sequencing.",
      "config": "Original externally configured ENIAC. Twenty ten-digit-plus-sign accumulators, function tables, card equipment and original master/local program controls; later converter-code execution excluded.",
      "insight": "How can one pulse sequence select the next operation while a separate set of digit pulses carries its numbers?",
      "fields": {
        "state": {
          "value": "Decimal decade counters plus binary sign state",
          "source": "hist-seed-eniac-burks-inspected",
          "locator": "p. 763 §VI-A"
        },
        "compute": {
          "value": "20 accumulator/adders with dedicated multiplier and divide/square-root control",
          "source": "hist-seed-eniac-burks-inspected",
          "locator": "p. 761 §V"
        },
        "memory": {
          "value": "Ten decimal digits and sign per accumulator; switch-set function values",
          "source": "hist-seed-eniac-burks-inspected",
          "locator": "pp. 761, 763"
        },
        "control": {
          "value": "Cycling unit timing; local program-control chains and master programmer",
          "source": "hist-seed-eniac-burks-inspected",
          "locator": "pp. 761–762, 764–765"
        },
        "io": {
          "value": "Card reader through constant transmitter; printer relays drive card punch",
          "source": "hist-seed-eniac-burks-inspected",
          "locator": "p. 761"
        },
        "software": {
          "value": "Cables connect program-control inputs/outputs; switches select operations",
          "source": "hist-seed-eniac-burks-inspected",
          "locator": "pp. 757, 761–762"
        },
        "workload": {
          "value": "Repetitive numerical procedures including ballistic integration",
          "source": "hist-seed-eniac-burks-inspected",
          "locator": "pp. 756, 761–762"
        }
      },
      "gaps": [
        "This is a conceptual organization, not an individual problem’s cable or digit-tray plan.",
        "Specialized arithmetic borrows accumulators for operands, partial products and results; it is not represented as self-contained register arithmetic.",
        "The paper notes that original function tables can emit program pulses; this does not import the later converter-code mode.",
        "No source scan, original artwork or full circuit is redistributed."
      ],
      "diagram": {
        "title": "Independent number and program paths in original ENIAC",
        "scope": "Program lines carry operation-start/completion pulses; digit trunks carry decimal values. Logical unit relationships are aggregated from Burks, not a modern CPU-memory bus.",
        "nodes": [
          {
            "id": "clock",
            "label": "Cycling unit",
            "subtitle": "SYNCHRONIZED TIMING PULSES",
            "text": "Gates digit, carry and program pulses across units.",
            "locator": "p. 762; Fig. 6",
            "control": true,
            "source": "hist-seed-eniac-burks-inspected",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66
          },
          {
            "id": "master",
            "label": "Master programmer",
            "subtitle": "SEQUENCE / REPETITION",
            "text": "Uses step counters to select or repeat program sequences.",
            "locator": "p. 762",
            "control": true,
            "source": "hist-seed-eniac-burks-inspected",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66
          },
          {
            "id": "local",
            "label": "Local program controls",
            "subtitle": "SWITCH-SET OPERATIONS",
            "text": "Start the selected unit action and emit completion pulses.",
            "locator": "pp. 761–762, 764–765",
            "control": true,
            "source": "hist-seed-eniac-burks-inspected",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66
          },
          {
            "id": "acc",
            "label": "Twenty accumulators",
            "subtitle": "TEN DIGITS + SIGN EACH",
            "text": "Add and retain operands, intermediate values and results.",
            "locator": "pp. 761, 763",
            "control": false,
            "source": "hist-seed-eniac-burks-inspected",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66
          },
          {
            "id": "digits",
            "label": "Digit trunks",
            "subtitle": "DECIMAL PULSE GROUPS",
            "text": "Carry numerical transfers between connected units.",
            "locator": "pp. 761, 763–764",
            "control": false,
            "source": "hist-seed-eniac-burks-inspected",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66
          },
          {
            "id": "input",
            "label": "Card reader / constant transmitter",
            "subtitle": "INPUT RELAYS TO PULSES",
            "text": "Convert punched-card data into gated digit pulses.",
            "locator": "p. 761",
            "control": false,
            "source": "hist-seed-eniac-burks-inspected",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66
          },
          {
            "id": "tables",
            "label": "Three function tables",
            "subtitle": "SWITCH-SET FUNCTION VALUES",
            "text": "Select a stored value from an argument.",
            "locator": "p. 761",
            "control": false,
            "source": "hist-seed-eniac-burks-inspected",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66
          },
          {
            "id": "special",
            "label": "Multiplier / divider-square-rooter",
            "subtitle": "DEDICATED ARITHMETIC CONTROL",
            "text": "Use selected accumulators for operands and partial results.",
            "locator": "pp. 761, 765–766",
            "control": false,
            "source": "hist-seed-eniac-burks-inspected",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66
          },
          {
            "id": "output",
            "label": "Printer relays / card punch",
            "subtitle": "STATIC VALUE CAPTURE",
            "text": "Latch accumulator output before mechanical punching.",
            "locator": "p. 761",
            "control": false,
            "source": "hist-seed-eniac-burks-inspected",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66
          }
        ],
        "edges": [
          {
            "from": "clock",
            "to": "local",
            "type": "control",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "pp. 762, 765 cycling-unit program pulse",
            "label": ""
          },
          {
            "from": "clock",
            "to": "acc",
            "type": "control",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "pp. 762–764 carry/digit timing",
            "label": ""
          },
          {
            "from": "master",
            "to": "local",
            "type": "control",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "p. 762 next-sequence selection",
            "label": ""
          },
          {
            "from": "local",
            "to": "master",
            "type": "control",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "p. 762 last completion pulse",
            "label": ""
          },
          {
            "from": "local",
            "to": "acc",
            "type": "control",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "pp. 764–765 selected receive/transmit/add action",
            "label": ""
          },
          {
            "from": "local",
            "to": "special",
            "type": "control",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "pp. 761–762 local unit controls",
            "label": ""
          },
          {
            "from": "local",
            "to": "tables",
            "type": "control",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "pp. 761–762 local unit controls",
            "label": ""
          },
          {
            "from": "acc",
            "to": "digits",
            "type": "data",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "pp. 763–764 transmission gates",
            "label": ""
          },
          {
            "from": "digits",
            "to": "acc",
            "type": "data",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "p. 763 reception gates",
            "label": ""
          },
          {
            "from": "input",
            "to": "digits",
            "type": "data",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "p. 761 constant transmitter",
            "label": ""
          },
          {
            "from": "digits",
            "to": "tables",
            "type": "data",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "p. 761 function argument",
            "label": ""
          },
          {
            "from": "tables",
            "to": "digits",
            "type": "data",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "p. 761 output pulse groups",
            "label": ""
          },
          {
            "from": "acc",
            "to": "special",
            "type": "data",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "pp. 761, 765–766 operand/static selector connections",
            "label": ""
          },
          {
            "from": "special",
            "to": "acc",
            "type": "data",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "pp. 761, 766 partial products/results",
            "label": ""
          },
          {
            "from": "acc",
            "to": "output",
            "type": "data",
            "source": "hist-seed-eniac-burks-inspected",
            "locator": "p. 761 static output→relay coils",
            "label": ""
          }
        ]
      },
      "originalCandidate": "ENIAC"
    },
    {
      "status": "dossier",
      "aliases": [],
      "models": [
        "register"
      ],
      "sources": [
        "parallel-seed-cdc6600"
      ],
      "id": "cdc-6600",
      "name": "CDC 6600",
      "organization": "Control Data Corporation",
      "year": 1964,
      "yearLabel": "1964 designer paper configuration",
      "kind": "Built system",
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "scoreboard",
        "distributed",
        "heterogeneous"
      ],
      "substrates": [
        "transistor"
      ],
      "summary": "The central scoreboard overlaps independent arithmetic units; ten logical peripheral processors share an execution slot while retaining private memories.",
      "config": "Organization in Thornton’s 1964 paper: 32-bank central memory, ten logical PPs and twelve I/O channels. Later upgrades excluded.",
      "insight": "How do functional-unit concurrency and peripheral barrel scheduling differ?",
      "fields": {
        "state": {
          "value": "60-bit central words;12-bit peripheral words",
          "source": "parallel-seed-cdc6600",
          "locator": "pp.34–36"
        },
        "compute": {
          "value": "Ten central functional units; shared PP execution slot",
          "source": "parallel-seed-cdc6600",
          "locator": "pp.34–36"
        },
        "memory": {
          "value": "32×4096 central words;4096×12 bits per PP",
          "source": "parallel-seed-cdc6600",
          "locator": "pp.34,37"
        },
        "control": {
          "value": "Central scoreboard; rotating ten-context PP barrel",
          "source": "parallel-seed-cdc6600",
          "locator": "pp.34–37"
        },
        "io": {
          "value": "Twelve shared12-bit peripheral channels",
          "source": "parallel-seed-cdc6600",
          "locator": "pp.34–35"
        },
        "software": {
          "value": "Executive control resides in a peripheral processor",
          "source": "parallel-seed-cdc6600",
          "locator": "p.34"
        },
        "workload": {
          "value": "Large scientific problems and time sharing",
          "source": "parallel-seed-cdc6600",
          "locator": "p.33"
        }
      },
      "gaps": [
        "The paper does not identify a full operating-system release or installed peripheral-device inventory.",
        "Ten PP contexts are not ten physical arithmetic engines.",
        "The instruction stack holds eight60-bit words; its32-instruction description assumes15-bit instructions."
      ],
      "diagram": {
        "title": "Central scoreboarding and peripheral barrel execution",
        "scope": "Central and PP execution controls are separate. Read/write pyramids convert five 12-bit words to/from a 60-bit central word. The PP exchange-jump and program-counter monitor controls are omitted.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "mem",
            "label": "Central memory",
            "subtitle": "32×4096×60 BITS",
            "text": "Holds central code,operands and results.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cdc6600",
            "locator": "p.37",
            "control": false
          },
          {
            "id": "stack",
            "label": "Instruction stack",
            "subtitle": "EIGHT60-BIT WORDS",
            "text": "Retains loops without repeated central-memory fetches.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cdc6600",
            "locator": "p.37, Figs.5–6",
            "control": false
          },
          {
            "id": "score",
            "label": "Central scoreboard",
            "subtitle": "REGISTER /UNIT /TRUNK STATE",
            "text": "Delays operations until their required resources permit.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cdc6600",
            "locator": "pp.36–37",
            "control": true
          },
          {
            "id": "x",
            "label": "Eight X registers",
            "subtitle": "60-BIT OPERANDS",
            "text": "Feeds functional units; X1–5 load,X6–7 store.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cdc6600",
            "locator": "pp.36–38,Fig.6",
            "control": false
          },
          {
            "id": "ab",
            "label": "A/B address/index state",
            "subtitle": "SIXTEEN18-BIT REGISTERS",
            "text": "Address-register results implicitly trigger memory references.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cdc6600",
            "locator": "pp.36–38,Fig.6",
            "control": false
          },
          {
            "id": "fu",
            "label": "Ten functional units",
            "subtitle": "PARALLEL BY FUNCTION",
            "text": "Runs independent arithmetic/control operations concurrently.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cdc6600",
            "locator": "p.36",
            "control": false
          },
          {
            "id": "barrel",
            "label": "Ten PP contexts",
            "subtitle": "ROTATING REGISTER BARREL",
            "text": "Cycles each logical processor through the shared slot.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cdc6600",
            "locator": "pp.34–35",
            "control": false
          },
          {
            "id": "slot",
            "label": "Shared PP execution slot",
            "subtitle": "TIME-SHARED CONTROL /ALU",
            "text": "Performs one step for the current PP context.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cdc6600",
            "locator": "pp.34–35,Fig.2",
            "control": true
          },
          {
            "id": "pmem",
            "label": "Ten private PP memories",
            "subtitle": "4096×12 BITS EACH",
            "text": "Keeps each PP’s program and buffers independent.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cdc6600",
            "locator": "pp.34–35",
            "control": false
          },
          {
            "id": "convert",
            "label": "Read/write pyramids",
            "subtitle": "12↔60-BIT ASSEMBLY",
            "text": "Assembles and disassembles central-memory words.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cdc6600",
            "locator": "pp.34–35,Fig.2",
            "control": false
          },
          {
            "id": "channels",
            "label": "Twelve I/O channels",
            "subtitle": "BIDIRECTIONAL12-BIT PATHS",
            "text": "Any PP may service the shared channels.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cdc6600",
            "locator": "pp.34–35",
            "control": false
          },
          {
            "id": "devices",
            "label": "External equipment",
            "subtitle": "PERIPHERAL ENDPOINTS",
            "text": "Connects devices and possible satellite computers.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cdc6600",
            "locator": "p.35",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "mem",
            "to": "stack",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.6",
            "label": ""
          },
          {
            "from": "stack",
            "to": "score",
            "type": "control",
            "source": "parallel-seed-cdc6600",
            "locator": "pp.36–37",
            "label": ""
          },
          {
            "from": "score",
            "to": "fu",
            "type": "control",
            "source": "parallel-seed-cdc6600",
            "locator": "pp.36–37",
            "label": ""
          },
          {
            "from": "score",
            "to": "x",
            "type": "control",
            "source": "parallel-seed-cdc6600",
            "locator": "p.37",
            "label": "result /operand reservations"
          },
          {
            "from": "x",
            "to": "fu",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.6",
            "label": ""
          },
          {
            "from": "fu",
            "to": "x",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.6",
            "label": ""
          },
          {
            "from": "ab",
            "to": "fu",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.6",
            "label": ""
          },
          {
            "from": "fu",
            "to": "ab",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.6",
            "label": ""
          },
          {
            "from": "ab",
            "to": "mem",
            "type": "control",
            "source": "parallel-seed-cdc6600",
            "locator": "p.37",
            "label": "load/store addresses"
          },
          {
            "from": "mem",
            "to": "x",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.6",
            "label": "five read trunks"
          },
          {
            "from": "x",
            "to": "mem",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.6",
            "label": "two store trunks"
          },
          {
            "from": "barrel",
            "to": "slot",
            "type": "control",
            "source": "parallel-seed-cdc6600",
            "locator": "pp.34–35",
            "label": ""
          },
          {
            "from": "slot",
            "to": "barrel",
            "type": "control",
            "source": "parallel-seed-cdc6600",
            "locator": "pp.34–35",
            "label": "updated context"
          },
          {
            "from": "pmem",
            "to": "slot",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "slot",
            "to": "pmem",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "slot",
            "to": "convert",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "convert",
            "to": "slot",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "convert",
            "to": "mem",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "mem",
            "to": "convert",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "slot",
            "to": "channels",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "channels",
            "to": "slot",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "channels",
            "to": "devices",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "devices",
            "to": "channels",
            "type": "data",
            "source": "parallel-seed-cdc6600",
            "locator": "Fig.2",
            "label": ""
          }
        ]
      },
      "scope": "Paper’s built system organization,not an unspecified family maximum.",
      "originalCandidate": "CDC 6600"
    },
    {
      "status": "dossier",
      "aliases": [],
      "models": [
        "register"
      ],
      "sources": [
        "seed-s360-princops",
        "ibm-history",
        "ibm-architecture"
      ],
      "id": "ibm-system-360",
      "name": "IBM System/360",
      "organization": "IBM",
      "year": 1964,
      "yearLabel": "1964 A22-6821-0 architectural contract",
      "kind": "Architecture family",
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "register-memory"
      ],
      "substrates": [
        "integrated"
      ],
      "summary": "A compatible architecture spanning multiple mainframe implementations, with a standardized I/O channel interface.",
      "config": "The original Principles of Operation logical architecture. Model-specific implementations, optional facilities, and the exceptional Model 20 require their own records.",
      "insight": "Which properties remain stable while implementations change?",
      "fields": {
        "state": {
          "value": "8-bit bytes; 32-bit words",
          "source": "seed-s360-princops",
          "locator": "p. 7, information formats"
        },
        "compute": {
          "value": "16 general registers; separate floating-point register set",
          "source": "seed-s360-princops",
          "locator": "p. 9, Figures 4–5"
        },
        "memory": {
          "value": "Byte-addressed main storage; model-dependent capacity",
          "source": "seed-s360-princops",
          "locator": "pp. 7–8"
        },
        "control": {
          "value": "PSW sequencing, status switching, and interruptions",
          "source": "seed-s360-princops",
          "locator": "p. 15"
        },
        "io": {
          "value": "Independent channel programs and device control units",
          "source": "seed-s360-princops",
          "locator": "pp. 20–21, Figure 20"
        },
        "software": {
          "value": "Machine-language architectural contract across implementations",
          "source": "ibm-architecture",
          "locator": "Compatibility design abstract"
        },
        "workload": {
          "value": "Commercial and scientific processing",
          "source": "ibm-architecture",
          "locator": "General-purpose design abstract"
        }
      },
      "gaps": [
        "Floating-point and other facilities are configuration-dependent; the diagram does not assign every facility to every model.",
        "No common clock, storage capacity, cache, or microcode implementation is asserted."
      ],
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Program execution, storage, and independent I/O channels",
        "width": 1120,
        "height": 535,
        "scope": "Logical resources from Figures 1 and 4; the control-unit block aggregates distinct device controllers. Links are architectural relationships, not internal wires.",
        "nodes": [
          {
            "id": "psw",
            "label": "Program status word",
            "subtitle": "EXECUTION STATE",
            "text": "Holds instruction address and condition/status state.",
            "x": 25,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-s360-princops",
            "locator": "p. 15",
            "control": true
          },
          {
            "id": "control",
            "label": "CPU sequencing",
            "subtitle": "INSTRUCTIONS / ADDRESSES",
            "text": "Fetches and sequences instructions.",
            "x": 310,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-s360-princops",
            "locator": "pp. 9, 15",
            "control": true
          },
          {
            "id": "gpr",
            "label": "General registers",
            "subtitle": "16 × 32 BITS",
            "text": "Supply integer operands and indexing values.",
            "x": 595,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-s360-princops",
            "locator": "p. 9, Figures 4–5",
            "control": false
          },
          {
            "id": "fpr",
            "label": "Floating-point registers",
            "subtitle": "4 × 64 BITS",
            "text": "Retain short or long floating-point operands.",
            "x": 880,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-s360-princops",
            "locator": "p. 9, Figures 4–5",
            "control": false
          },
          {
            "id": "mux",
            "label": "Multiplexor channel",
            "subtitle": "INDEPENDENT I/O",
            "text": "Executes channel commands.",
            "x": 25,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-s360-princops",
            "locator": "pp. 7, 20",
            "control": false
          },
          {
            "id": "memory",
            "label": "Main storage",
            "subtitle": "INSTRUCTIONS + DATA",
            "text": "Holds programs, operands, and channel commands.",
            "x": 310,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-s360-princops",
            "locator": "pp. 7, 20",
            "control": false
          },
          {
            "id": "arithmetic",
            "label": "Arithmetic and logic",
            "subtitle": "FIXED / DECIMAL / FP",
            "text": "Executes the selected data operations.",
            "x": 595,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-s360-princops",
            "locator": "p. 9, Figure 4",
            "control": false
          },
          {
            "id": "selector",
            "label": "Selector channels",
            "subtitle": "INDEPENDENT I/O",
            "text": "Connect through device control units.",
            "x": 880,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-s360-princops",
            "locator": "pp. 7, 20",
            "control": false
          },
          {
            "id": "units",
            "label": "Device control units",
            "subtitle": "DEVICE ORDERS",
            "text": "Translate channel operations into device orders.",
            "x": 595,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "seed-s360-princops",
            "locator": "p. 20, Figure 20",
            "control": false
          },
          {
            "id": "devices",
            "label": "I/O devices",
            "subtitle": "EXTERNAL DATA",
            "text": "Exchange information through control units.",
            "x": 880,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "seed-s360-princops",
            "locator": "p. 7, Figure 1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "psw",
            "to": "control",
            "type": "control",
            "source": "seed-s360-princops",
            "locator": "p. 15",
            "label": "",
            "note": ""
          },
          {
            "from": "memory",
            "to": "control",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 9, Figure 4",
            "label": "instructions",
            "note": ""
          },
          {
            "from": "control",
            "to": "memory",
            "type": "control",
            "source": "seed-s360-princops",
            "locator": "p. 9, Figure 4",
            "label": "address",
            "note": ""
          },
          {
            "from": "gpr",
            "to": "control",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 9, Figure 4",
            "label": "index",
            "note": ""
          },
          {
            "from": "gpr",
            "to": "arithmetic",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 9, Figure 4",
            "label": "",
            "note": ""
          },
          {
            "from": "arithmetic",
            "to": "gpr",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 9, Figure 4",
            "label": "",
            "note": ""
          },
          {
            "from": "fpr",
            "to": "arithmetic",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 9, Figure 4",
            "label": "",
            "note": ""
          },
          {
            "from": "arithmetic",
            "to": "fpr",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 9, Figure 4",
            "label": "",
            "note": ""
          },
          {
            "from": "memory",
            "to": "arithmetic",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 9, Figure 4",
            "label": "",
            "note": ""
          },
          {
            "from": "arithmetic",
            "to": "memory",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 9, Figure 4",
            "label": "",
            "note": ""
          },
          {
            "from": "control",
            "to": "mux",
            "type": "control",
            "source": "seed-s360-princops",
            "locator": "p. 20, START I/O",
            "label": "",
            "note": ""
          },
          {
            "from": "control",
            "to": "selector",
            "type": "control",
            "source": "seed-s360-princops",
            "locator": "p. 20, START I/O",
            "label": "",
            "note": ""
          },
          {
            "from": "memory",
            "to": "selector",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 20, channel commands",
            "label": "",
            "note": ""
          },
          {
            "from": "memory",
            "to": "mux",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 20, channel commands",
            "label": "",
            "note": ""
          },
          {
            "from": "mux",
            "to": "units",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 7, Figure 1",
            "label": "",
            "note": ""
          },
          {
            "from": "selector",
            "to": "units",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 7, Figure 1",
            "label": "",
            "note": ""
          },
          {
            "from": "units",
            "to": "devices",
            "type": "data",
            "source": "seed-s360-princops",
            "locator": "p. 7, Figure 1",
            "label": "",
            "note": ""
          }
        ]
      },
      "originalCandidate": "IBM System/360"
    },
    {
      "status": "dossier",
      "aliases": [
        "KA11",
        "UNIBUS"
      ],
      "models": [
        "register"
      ],
      "sources": [
        "hist-seed-pdp1120-handbook-inspected"
      ],
      "id": "pdp-11-20",
      "name": "PDP-11/20",
      "organization": "Digital Equipment Corporation",
      "year": 1970,
      "yearLabel": "1970 second-edition basic 4K-word configuration",
      "kind": "Commercial system",
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "register-memory",
        "cisc"
      ],
      "substrates": [
        "integrated"
      ],
      "summary": "The KA11 shares asynchronous UNIBUS with core memory and peripheral registers; device-supplied vectors, a hardware-managed memory stack and priority arbitration support nested service and DMA.",
      "config": "Basic PDP-11/20: KA11, 4096×16-bit read/write core, console and ASR-33. The optional NPR-capable controller illustrates documented UNIBUS DMA; later MMU, cache and FPU models excluded.",
      "insight": "What is the difference between a device borrowing UNIBUS for DMA and a device using it to vector an interrupt?",
      "fields": {
        "state": {
          "value": "Eight 16-bit registers; R6 stack pointer, R7 program counter; PSW",
          "source": "hist-seed-pdp1120-handbook-inspected",
          "locator": "pp. 2, 6"
        },
        "compute": {
          "value": "Two-operand register/memory operations with variable-length addressing",
          "source": "hist-seed-pdp1120-handbook-inspected",
          "locator": "p. 2"
        },
        "memory": {
          "value": "4096×16-bit core in base system; devices share address space",
          "source": "hist-seed-pdp1120-handbook-inspected",
          "locator": "pp. 1, 5–6"
        },
        "control": {
          "value": "Four interrupt-request levels plus higher-priority NPR; PSW priority",
          "source": "hist-seed-pdp1120-handbook-inspected",
          "locator": "pp. 7–10"
        },
        "io": {
          "value": "Memory-mapped UNIBUS registers; base ASR-33",
          "source": "hist-seed-pdp1120-handbook-inspected",
          "locator": "pp. 1, 5, 7"
        },
        "software": {
          "value": "Assembler, editor, debugger, device handlers and math library",
          "source": "hist-seed-pdp1120-handbook-inspected",
          "locator": "p. 3"
        },
        "workload": {
          "value": "General-purpose and real-time peripheral-control computing",
          "source": "hist-seed-pdp1120-handbook-inspected",
          "locator": "pp. 1–2, 5–10"
        }
      },
      "gaps": [
        "No OS or installation-specific application is assigned by the handbook’s software package list.",
        "NPR is a transfer protocol supported by the system; the base ASR-33 is not claimed to perform DMA.",
        "The stack and vector nodes are areas of the same core memory, not additional memory hardware.",
        "CISC labels the documented variable-length two-operand instruction organization."
      ],
      "diagram": {
        "title": "UNIBUS ownership and memory-resident interrupt context",
        "scope": "Data links show logical transfers on the shared bus. Control links distinguish requests, grants and device-supplied interrupt vectors; no later memory management is introduced.",
        "nodes": [
          {
            "id": "regs",
            "label": "R0–R5 registers",
            "subtitle": "GENERAL OPERANDS / POINTERS",
            "text": "Hold values and effective-address components.",
            "locator": "pp. 2, 6",
            "control": false,
            "source": "hist-seed-pdp1120-handbook-inspected",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66
          },
          {
            "id": "cpu",
            "label": "KA11 execution",
            "subtitle": "TWO-OPERAND INSTRUCTIONS",
            "text": "Executes references and handles bus ownership.",
            "locator": "pp. 2, 5–7",
            "control": false,
            "source": "hist-seed-pdp1120-handbook-inspected",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66
          },
          {
            "id": "pcps",
            "label": "R7 / processor status",
            "subtitle": "PC / FLAGS / PRIORITY",
            "text": "Retain instruction location and interrupt priority state.",
            "locator": "p. 6",
            "control": false,
            "source": "hist-seed-pdp1120-handbook-inspected",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66
          },
          {
            "id": "sp",
            "label": "R6 stack pointer",
            "subtitle": "MEMORY STACK ADDRESS",
            "text": "Tracks saved context and nested service frames.",
            "locator": "pp. 6, 8–9",
            "control": false,
            "source": "hist-seed-pdp1120-handbook-inspected",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66
          },
          {
            "id": "bus",
            "label": "UNIBUS",
            "subtitle": "ASYNCHRONOUS MASTER / SLAVE",
            "text": "Shares addressed word/byte transfers and arbitration.",
            "locator": "pp. 5–7; Ch. 8",
            "control": false,
            "source": "hist-seed-pdp1120-handbook-inspected",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66
          },
          {
            "id": "core",
            "label": "4K-word core",
            "subtitle": "BASE READ/WRITE STORE",
            "text": "Holds instructions, data, stacks and vectors.",
            "locator": "pp. 1, 6",
            "control": false,
            "source": "hist-seed-pdp1120-handbook-inspected",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66
          },
          {
            "id": "vectors",
            "label": "Vectors / saved PC and PS",
            "subtitle": "REGIONS WITHIN CORE",
            "text": "Supply service entry and preserve interrupted context.",
            "locator": "pp. 8–10; Fig. 2-2",
            "control": false,
            "source": "hist-seed-pdp1120-handbook-inspected",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66
          },
          {
            "id": "tty",
            "label": "Console / ASR-33 interface",
            "subtitle": "BASE DEVICE REGISTERS",
            "text": "Provides console, keyboard, printing and paper tape.",
            "locator": "pp. 1, 7",
            "control": false,
            "source": "hist-seed-pdp1120-handbook-inspected",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66
          },
          {
            "id": "dma",
            "label": "NPR-capable controller",
            "subtitle": "OPTIONAL DIRECT TRANSFERS",
            "text": "Becomes bus master for device-to-memory transfers.",
            "locator": "pp. 7–8",
            "control": false,
            "source": "hist-seed-pdp1120-handbook-inspected",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66
          }
        ],
        "edges": [
          {
            "from": "regs",
            "to": "cpu",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 2, 6 operand roles",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "regs",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 2, 6",
            "label": ""
          },
          {
            "from": "pcps",
            "to": "cpu",
            "type": "control",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 6–7 priority/PC",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "pcps",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 6, 9 vector load",
            "label": ""
          },
          {
            "from": "sp",
            "to": "cpu",
            "type": "control",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 8–9 stack address",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "sp",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 8–9 push/pop",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "bus",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 5–7",
            "label": ""
          },
          {
            "from": "bus",
            "to": "cpu",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 5–7",
            "label": ""
          },
          {
            "from": "bus",
            "to": "core",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 5–7",
            "label": ""
          },
          {
            "from": "core",
            "to": "bus",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 5–7",
            "label": ""
          },
          {
            "from": "vectors",
            "to": "core",
            "type": "association",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 8–10 memory-resident context",
            "label": ""
          },
          {
            "from": "pcps",
            "to": "vectors",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "p. 9 interrupt save via CPU/bus",
            "label": ""
          },
          {
            "from": "vectors",
            "to": "pcps",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "p. 9 new PC/PS via CPU/bus",
            "label": ""
          },
          {
            "from": "tty",
            "to": "bus",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 5, 7 mapped registers",
            "label": ""
          },
          {
            "from": "bus",
            "to": "tty",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 5, 7",
            "label": ""
          },
          {
            "from": "dma",
            "to": "bus",
            "type": "control",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 7–8 NPR arbitration",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "dma",
            "type": "control",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "pp. 7–8 relinquish bus",
            "label": ""
          },
          {
            "from": "dma",
            "to": "bus",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "p. 8 direct transfers",
            "label": ""
          },
          {
            "from": "bus",
            "to": "dma",
            "type": "data",
            "source": "hist-seed-pdp1120-handbook-inspected",
            "locator": "p. 8",
            "label": ""
          }
        ]
      },
      "originalCandidate": "PDP-11/20"
    },
    {
      "status": "dossier",
      "aliases": [],
      "models": [
        "register"
      ],
      "sources": [
        "hist-seed-alto-originalscan"
      ],
      "id": "xerox-alto",
      "name": "Xerox Alto",
      "organization": "Xerox PARC",
      "year": 1973,
      "yearLabel": "Initial 1973 configuration, distinguished by designer revision table",
      "kind": "Research system",
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "microcoded"
      ],
      "substrates": [
        "integrated"
      ],
      "summary": "One microcoded processor is time-shared by the user-instruction emulator and device tasks; peripheral wakeups schedule computation, and the processor initiates all memory references.",
      "config": "1973 baseline: 64K×16-bit parity DRAM, 1K-word PROM control store and 32 R registers. Standard display, disk, Ethernet and input roles follow the designer account; later control RAM, S-register banks and ECC memory excluded.",
      "insight": "Why can sharing the processor with device tasks remove the need for ordinary DMA address hardware?",
      "fields": {
        "state": {
          "value": "16-bit datapath; initial 32 R registers",
          "source": "hist-seed-alto-originalscan",
          "locator": "Fig. 2 1973 row; §2.4"
        },
        "compute": {
          "value": "16-bit microcoded arithmetic and BCPL instruction emulator",
          "source": "hist-seed-alto-originalscan",
          "locator": "§§2, 2.1, 2.4"
        },
        "memory": {
          "value": "Initial 64K×16 parity memory; 1K-word PROM microstore",
          "source": "hist-seed-alto-originalscan",
          "locator": "p. 3 Fig. 2; p. 4"
        },
        "control": {
          "value": "16 fixed-priority tasks with per-task microprogram counters",
          "source": "hist-seed-alto-originalscan",
          "locator": "p. 4; §2.3"
        },
        "io": {
          "value": "Device tasks for display, disk and Ethernet; mapped keyboard/keyset",
          "source": "hist-seed-alto-originalscan",
          "locator": "§2.2"
        },
        "software": {
          "value": "BCPL emulator in PROM; later RAM-loaded emulators outside baseline",
          "source": "hist-seed-alto-originalscan",
          "locator": "p. 5 §2.1; Fig. 2"
        },
        "workload": {
          "value": "Interactive text, program preparation and personal computing",
          "source": "hist-seed-alto-originalscan",
          "locator": "§1; p. 3"
        }
      },
      "gaps": [
        "The 1979 paper is a retrospective covering multiple revisions; only its explicit 1973 capacities and persistent logical roles are used here.",
        "The diagram deliberately omits later writable control banks, S registers, extended memory and ECC circuitry.",
        "Peripheral-task wakeups are different from the emulator’s microcoded interrupt mechanism.",
        "Network application services surveyed later in the paper are not all assigned to the 1973 machine."
      ],
      "diagram": {
        "title": "A PROM micromachine multiplexed between emulator and device tasks",
        "scope": "Functional roles from §§2.2–2.4 with 1973 storage counts from the inspected revision table. Every memory request is initiated by processor microcode.",
        "nodes": [
          {
            "id": "tasks",
            "label": "Task priority / MPC RAM",
            "subtitle": "16 FIXED-PRIORITY TASKS",
            "text": "Selects wakeup service and retains each microprogram counter.",
            "locator": "p. 4; §2.3",
            "control": true,
            "source": "hist-seed-alto-originalscan",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66
          },
          {
            "id": "prom",
            "label": "Original control PROM",
            "subtitle": "1K-WORD STORE",
            "text": "Supplies emulator and device microinstructions.",
            "locator": "p. 3 Fig. 2; §§2.1–2.3",
            "control": true,
            "source": "hist-seed-alto-originalscan",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66
          },
          {
            "id": "datapath",
            "label": "ALU / T / L / 32 R registers",
            "subtitle": "16-BIT MICROMACHINE",
            "text": "Performs arithmetic and temporary storage for every task.",
            "locator": "Fig. 2 1973 row; §2.4",
            "control": false,
            "source": "hist-seed-alto-originalscan",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66
          },
          {
            "id": "bus",
            "label": "Processor bus",
            "subtitle": "16-BIT DATA PATH",
            "text": "Moves values among registers, memory and controllers.",
            "locator": "§2.4",
            "control": false,
            "source": "hist-seed-alto-originalscan",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66
          },
          {
            "id": "memory",
            "label": "Main memory / address port",
            "subtitle": "64K×16 / PARITY",
            "text": "Stores user code, data and device communication structures.",
            "locator": "p. 4; §§2.2, 2.4",
            "control": false,
            "source": "hist-seed-alto-originalscan",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66
          },
          {
            "id": "display",
            "label": "Display / cursor controller",
            "subtitle": "MICROCODED DISPLAY TASKS",
            "text": "Requests service to replenish display information.",
            "locator": "p. 4; §2.2",
            "control": false,
            "source": "hist-seed-alto-originalscan",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66
          },
          {
            "id": "disk",
            "label": "Disk controller",
            "subtitle": "TWO TASKS / CARTRIDGE DISK",
            "text": "Requests short-latency sector and word service.",
            "locator": "p. 4; §2.2",
            "control": false,
            "source": "hist-seed-alto-originalscan",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66
          },
          {
            "id": "ethernet",
            "label": "Ethernet controller",
            "subtitle": "NETWORK TASK",
            "text": "Buffers network words and requests microcode service.",
            "locator": "p. 4; §2.2",
            "control": false,
            "source": "hist-seed-alto-originalscan",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66
          },
          {
            "id": "input",
            "label": "Keyboard / keyset / mouse",
            "subtitle": "MAPPED AND TIMED INPUT",
            "text": "Provides key state and mouse position changes.",
            "locator": "§2.2",
            "control": false,
            "source": "hist-seed-alto-originalscan",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66
          }
        ],
        "edges": [
          {
            "from": "tasks",
            "to": "prom",
            "type": "control",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.3 MPC selects microinstruction",
            "label": ""
          },
          {
            "from": "prom",
            "to": "tasks",
            "type": "control",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.3 NEXT updates MPC",
            "label": ""
          },
          {
            "from": "prom",
            "to": "datapath",
            "type": "control",
            "source": "hist-seed-alto-originalscan",
            "locator": "§§2.3–2.4 ALU/register controls",
            "label": ""
          },
          {
            "from": "datapath",
            "to": "bus",
            "type": "data",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.4",
            "label": ""
          },
          {
            "from": "bus",
            "to": "datapath",
            "type": "data",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.4",
            "label": ""
          },
          {
            "from": "datapath",
            "to": "memory",
            "type": "control",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.4 MAR initiates all references",
            "label": ""
          },
          {
            "from": "memory",
            "to": "bus",
            "type": "data",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.4",
            "label": ""
          },
          {
            "from": "bus",
            "to": "memory",
            "type": "data",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.4",
            "label": ""
          },
          {
            "from": "display",
            "to": "tasks",
            "type": "control",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.2 wakeup requests",
            "label": ""
          },
          {
            "from": "disk",
            "to": "tasks",
            "type": "control",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.2 wakeup requests",
            "label": ""
          },
          {
            "from": "ethernet",
            "to": "tasks",
            "type": "control",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.2 wakeup requests",
            "label": ""
          },
          {
            "from": "bus",
            "to": "display",
            "type": "data",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.2 processor-bus attachment",
            "label": ""
          },
          {
            "from": "bus",
            "to": "disk",
            "type": "data",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.2 processor-bus attachment",
            "label": ""
          },
          {
            "from": "disk",
            "to": "bus",
            "type": "data",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "bus",
            "to": "ethernet",
            "type": "data",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "ethernet",
            "to": "bus",
            "type": "data",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "input",
            "to": "memory",
            "type": "association",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.2 keyboard mapped memory-bus device",
            "label": ""
          },
          {
            "from": "input",
            "to": "bus",
            "type": "data",
            "source": "hist-seed-alto-originalscan",
            "locator": "§2.2 timed-task mouse input",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Xerox Alto"
    },
    {
      "status": "dossier",
      "aliases": [
        "CRAY-1",
        "vector chaining"
      ],
      "models": [
        "register"
      ],
      "sources": [
        "parallel-seed-cray1-revc"
      ],
      "id": "cray-1",
      "name": "Cray-1",
      "organization": "Cray Research",
      "year": 1977,
      "yearLabel": "November 1977 Revision C reference configuration",
      "kind": "Commercial reference configuration",
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "vector",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "summary": "Separate address,scalar and vector register paths feed segmented units; chain-slot availability lets a result vector become a following operation’s operand.",
      "config": "2240004 Revision C, November 1977, serial 3 onward; 1M-word/16-bank option. CRAY-1S and X-MP are excluded.",
      "insight": "When can a reserved result register feed the next vector pipeline?",
      "fields": {
        "state": {
          "value": "64-bit scalar/vector values;24-bit address state",
          "source": "parallel-seed-cray1-revc",
          "locator": "Table1-1; p.3-3"
        },
        "compute": {
          "value": "Eight64-element V registers; twelve segmented units",
          "source": "parallel-seed-cray1-revc",
          "locator": "Table1-1; p.3-1"
        },
        "memory": {
          "value": "1,048,576 words across16 banks in selected option",
          "source": "parallel-seed-cray1-revc",
          "locator": "p.1-5"
        },
        "control": {
          "value": "In-order issue with reservations and chain slots",
          "source": "parallel-seed-cray1-revc",
          "locator": "pp.3-5,3-30–3-34"
        },
        "io": {
          "value": "Twelve full-duplex16-bit channel pairs",
          "source": "parallel-seed-cray1-revc",
          "locator": "p.1-5"
        },
        "software": {
          "value": "Scalar/vector instruction interface; FORTRAN strip-mining",
          "source": "parallel-seed-cray1-revc",
          "locator": "pp.1-4,1-7"
        },
        "workload": {
          "value": "General-purpose scalar and scientific vector computation",
          "source": "parallel-seed-cray1-revc",
          "locator": "pp.1-1,1-6"
        }
      },
      "gaps": [
        "Eight-bank phasing is another Revision C option; this graph uses sixteen banks.",
        "A chain slot is a particular reservation-release opportunity,not later flexible chaining.",
        "Vector stores cannot start in a chain slot; vector reads are blocked there for increments divisible by eight."
      ],
      "diagram": {
        "title": "Register classes,shared floating units,and chain-slot control",
        "scope": "Selected 16-bank configuration. Reservation control is logical; all chained data still passes through V-register element paths.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "mem",
            "label": "Banked bipolar memory",
            "subtitle": "1MWORDS /16 BANKS",
            "text": "Stores code,data and exchange state.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cray1-revc",
            "locator": "p.1-5",
            "control": false
          },
          {
            "id": "ib",
            "label": "Instruction buffers",
            "subtitle": "FOUR×64 PARCELS",
            "text": "Supplies16-bit parcels to issue registers.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cray1-revc",
            "locator": "pp.3-30–3-34",
            "control": false
          },
          {
            "id": "issue",
            "label": "NIP /LIP /CIP issue",
            "subtitle": "CURRENT INSTRUCTION",
            "text": "Waits until the current instruction can issue.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cray1-revc",
            "locator": "pp.3-30–3-32",
            "control": true
          },
          {
            "id": "reserve",
            "label": "Reservations /chain slot",
            "subtitle": "REGISTER /UNIT CONTROL",
            "text": "Releases a result register for eligible chaining.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cray1-revc",
            "locator": "pp.3-5,3-13",
            "control": true
          },
          {
            "id": "ab",
            "label": "Address A/B paths",
            "subtitle": "24-BIT /TWO INTEGER UNITS",
            "text": "Generates addresses and buffers index state.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cray1-revc",
            "locator": "pp.3-1,3-8–3-11",
            "control": false
          },
          {
            "id": "st",
            "label": "Scalar S/T paths",
            "subtitle": "64-BIT /FOUR SCALAR UNITS",
            "text": "Buffers scalar data and executes scalar operations.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cray1-revc",
            "locator": "pp.3-1,3-7–3-8,3-12",
            "control": false
          },
          {
            "id": "v",
            "label": "Eight V registers",
            "subtitle": "64 ELEMENTS EACH",
            "text": "Holds vector operands and streamed results.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cray1-revc",
            "locator": "pp.3-4–3-5",
            "control": false
          },
          {
            "id": "vector",
            "label": "Vector-only units",
            "subtitle": "ADD /LOGICAL /SHIFT",
            "text": "Executes dedicated vector operations.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cray1-revc",
            "locator": "pp.3-13–3-17",
            "control": false
          },
          {
            "id": "fp",
            "label": "Shared floating units",
            "subtitle": "ADD /MULTIPLY /RECIPROCAL",
            "text": "Accepts either scalar or vector operands.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cray1-revc",
            "locator": "pp.3-17–3-18",
            "control": false
          },
          {
            "id": "vlvm",
            "label": "VL /VM vector control",
            "subtitle": "LENGTH /MERGE MASK",
            "text": "Controls element count and merge selection.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cray1-revc",
            "locator": "p.3-6",
            "control": true
          },
          {
            "id": "io",
            "label": "I/O channel groups",
            "subtitle": "12 INPUT +12 OUTPUT",
            "text": "Arbitrates channel transfers to memory.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cray1-revc",
            "locator": "p.1-5",
            "control": false
          },
          {
            "id": "external",
            "label": "Front end /MCU /disk",
            "subtitle": "SEPARATE EXTERNAL ROLES",
            "text": "Provides batch entry,initialization and disk storage.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-seed-cray1-revc",
            "locator": "pp.2-9–2-11",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "mem",
            "to": "ib",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "p.3-34",
            "label": ""
          },
          {
            "from": "ib",
            "to": "issue",
            "type": "control",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-6",
            "label": ""
          },
          {
            "from": "issue",
            "to": "reserve",
            "type": "control",
            "source": "parallel-seed-cray1-revc",
            "locator": "pp.3-5,3-13,3-31",
            "label": ""
          },
          {
            "from": "reserve",
            "to": "v",
            "type": "control",
            "source": "parallel-seed-cray1-revc",
            "locator": "p.3-5",
            "label": "chain-slot eligibility"
          },
          {
            "from": "reserve",
            "to": "vector",
            "type": "control",
            "source": "parallel-seed-cray1-revc",
            "locator": "p.3-13",
            "label": "unit reservation"
          },
          {
            "from": "reserve",
            "to": "fp",
            "type": "control",
            "source": "parallel-seed-cray1-revc",
            "locator": "p.3-13",
            "label": ""
          },
          {
            "from": "mem",
            "to": "ab",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": ""
          },
          {
            "from": "ab",
            "to": "mem",
            "type": "control",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": "addresses"
          },
          {
            "from": "mem",
            "to": "st",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": ""
          },
          {
            "from": "st",
            "to": "mem",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": ""
          },
          {
            "from": "mem",
            "to": "v",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": ""
          },
          {
            "from": "v",
            "to": "mem",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": ""
          },
          {
            "from": "v",
            "to": "vector",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": "including eligible chained element"
          },
          {
            "from": "vector",
            "to": "v",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": ""
          },
          {
            "from": "v",
            "to": "fp",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": "vector operand /chain"
          },
          {
            "from": "fp",
            "to": "v",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": ""
          },
          {
            "from": "st",
            "to": "fp",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": "scalar operand"
          },
          {
            "from": "fp",
            "to": "st",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": ""
          },
          {
            "from": "st",
            "to": "vector",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "Fig.3-1",
            "label": "scalar-vector operand"
          },
          {
            "from": "vlvm",
            "to": "vector",
            "type": "control",
            "source": "parallel-seed-cray1-revc",
            "locator": "p.3-6",
            "label": "length /merge mask"
          },
          {
            "from": "vlvm",
            "to": "fp",
            "type": "control",
            "source": "parallel-seed-cray1-revc",
            "locator": "p.3-6",
            "label": "vector length"
          },
          {
            "from": "ab",
            "to": "vlvm",
            "type": "control",
            "source": "parallel-seed-cray1-revc",
            "locator": "p.3-6",
            "label": "set length"
          },
          {
            "from": "st",
            "to": "vlvm",
            "type": "control",
            "source": "parallel-seed-cray1-revc",
            "locator": "p.3-6",
            "label": "set mask"
          },
          {
            "from": "io",
            "to": "mem",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "p.1-5",
            "label": ""
          },
          {
            "from": "mem",
            "to": "io",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "p.1-5",
            "label": ""
          },
          {
            "from": "external",
            "to": "io",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "pp.2-9–2-11",
            "label": ""
          },
          {
            "from": "io",
            "to": "external",
            "type": "data",
            "source": "parallel-seed-cray1-revc",
            "locator": "pp.2-9–2-11",
            "label": ""
          }
        ]
      },
      "scope": "Documented reference configuration,not a named installation.",
      "originalCandidate": "Cray-1"
    },
    {
      "status": "dossier",
      "aliases": [],
      "models": [
        "chemical"
      ],
      "sources": [
        "seed-adleman-1994-detailed"
      ],
      "id": "adleman-dna",
      "name": "Adleman DNA experiment",
      "organization": "University of Southern California",
      "year": 1994,
      "yearLabel": "1994 experiment",
      "kind": "Laboratory experiment",
      "paradigms": [
        "molecular",
        "parallel"
      ],
      "architectures": [
        "dna-reaction"
      ],
      "substrates": [
        "molecular-material"
      ],
      "summary": "DNA ligation generates candidate paths; PCR, length selection and affinity capture impose graph constraints.",
      "config": "Fig. 1 seven-vertex directed graph, endpoints 0 and 6; laboratory selection.",
      "insight": "Where does molecular parallelism end and experimental selection begin?",
      "fields": {
        "state": {
          "value": "Vertex/edge sequences in DNA molecules",
          "source": "seed-adleman-1994-detailed",
          "locator": "Fig. 2"
        },
        "compute": {
          "value": "Ligation followed by biochemical selection",
          "source": "seed-adleman-1994-detailed",
          "locator": "Algorithm steps 1–5"
        },
        "memory": {
          "value": "Candidate DNA pool",
          "source": "seed-adleman-1994-detailed",
          "locator": "p. 1022"
        },
        "control": {
          "value": "Ordered bench protocol and thermal cycling",
          "source": "seed-adleman-1994-detailed",
          "locator": "Notes 4–7"
        },
        "io": {
          "value": "Synthesized oligonucleotides; graduated PCR/gel",
          "source": "seed-adleman-1994-detailed",
          "locator": "Figs. 2–3"
        },
        "software": {
          "value": "Graph encoding and laboratory algorithm",
          "source": "seed-adleman-1994-detailed",
          "locator": "Algorithm; Fig. 2"
        },
        "workload": {
          "value": "One seven-vertex directed Hamiltonian path",
          "source": "seed-adleman-1994-detailed",
          "locator": "Fig. 1"
        }
      },
      "gaps": [
        "Experiment took about seven days; selection was labor-intensive.",
        "Expected exponential reagent growth prevents an efficiency claim for large NP-complete problems.",
        "Nonspecific binding, loss and incompatible ligation can cause errors."
      ],
      "diagram": {
        "title": "The experiment filters candidates with three independent constraints",
        "width": 1020,
        "height": 500,
        "scope": "Laboratory protocol; graduated-PCR lanes identify the path through external interpretation.",
        "nodes": [
          {
            "id": "encode",
            "label": "Vertex / edge encoding",
            "subtitle": "20-MER DESIGN",
            "text": "Encodes directed adjacency.",
            "x": 25,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-adleman-1994-detailed",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "ligate",
            "label": "Splints + T4 ligase",
            "subtitle": "GENERATE PATHS",
            "text": "Joins compatible edge strands.",
            "x": 265,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-adleman-1994-detailed",
            "locator": "p. 1022; note 4",
            "control": false
          },
          {
            "id": "ends",
            "label": "Endpoint PCR",
            "subtitle": "START 0 / END 6",
            "text": "Amplifies endpoint candidates.",
            "x": 505,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-adleman-1994-detailed",
            "locator": "Step 2; note 5",
            "control": false
          },
          {
            "id": "length",
            "label": "140-bp gel band",
            "subtitle": "SEVEN VERTICES",
            "text": "Excises desired path length.",
            "x": 745,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-adleman-1994-detailed",
            "locator": "Step 3",
            "control": false
          },
          {
            "id": "single",
            "label": "Single-strand preparation",
            "subtitle": "AFFINITY INPUT",
            "text": "Prepares selected DNA.",
            "x": 745,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-adleman-1994-detailed",
            "locator": "Step 4; note 7",
            "control": false
          },
          {
            "id": "capture",
            "label": "Sequential bead capture",
            "subtitle": "VERTICES 1 THROUGH 5",
            "text": "Retains each required sequence.",
            "x": 505,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-adleman-1994-detailed",
            "locator": "Step 4; note 7",
            "control": false
          },
          {
            "id": "detect",
            "label": "Final PCR + gel",
            "subtitle": "EXISTENCE TEST",
            "text": "Detects remaining candidates.",
            "x": 265,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-adleman-1994-detailed",
            "locator": "Step 5",
            "control": false
          },
          {
            "id": "graduated",
            "label": "Graduated PCR",
            "subtitle": "PATH READOUT",
            "text": "Uses multiple endpoint primers.",
            "x": 25,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-adleman-1994-detailed",
            "locator": "Fig. 3C; note 9",
            "control": false
          },
          {
            "id": "bands",
            "label": "Gel-band pattern",
            "subtitle": "EXTERNAL INTERPRETATION",
            "text": "Identifies 0→1→2→3→4→5→6.",
            "x": 25,
            "y": 380,
            "w": 180,
            "h": 66,
            "source": "seed-adleman-1994-detailed",
            "locator": "Fig. 3C",
            "control": false
          },
          {
            "id": "bench",
            "label": "Experimenter / apparatus",
            "subtitle": "PROCEDURAL CONTROL",
            "text": "Transfers, heats and separates.",
            "x": 505,
            "y": 380,
            "w": 180,
            "h": 66,
            "source": "seed-adleman-1994-detailed",
            "locator": "Notes 4–7",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "encode",
            "to": "ligate",
            "type": "control",
            "source": "seed-adleman-1994-detailed",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "ligate",
            "to": "ends",
            "type": "data",
            "source": "seed-adleman-1994-detailed",
            "locator": "Steps 1–2",
            "label": ""
          },
          {
            "from": "ends",
            "to": "length",
            "type": "data",
            "source": "seed-adleman-1994-detailed",
            "locator": "Steps 2–3",
            "label": ""
          },
          {
            "from": "length",
            "to": "single",
            "type": "data",
            "source": "seed-adleman-1994-detailed",
            "locator": "Steps 3–4",
            "label": ""
          },
          {
            "from": "single",
            "to": "capture",
            "type": "data",
            "source": "seed-adleman-1994-detailed",
            "locator": "Step 4",
            "label": ""
          },
          {
            "from": "capture",
            "to": "detect",
            "type": "data",
            "source": "seed-adleman-1994-detailed",
            "locator": "Steps 4–5",
            "label": ""
          },
          {
            "from": "capture",
            "to": "graduated",
            "type": "data",
            "source": "seed-adleman-1994-detailed",
            "locator": "Fig. 3C",
            "label": ""
          },
          {
            "from": "graduated",
            "to": "bands",
            "type": "data",
            "source": "seed-adleman-1994-detailed",
            "locator": "Fig. 3C",
            "label": ""
          },
          {
            "from": "bench",
            "to": "ends",
            "type": "control",
            "source": "seed-adleman-1994-detailed",
            "locator": "Note 5",
            "label": ""
          },
          {
            "from": "bench",
            "to": "length",
            "type": "control",
            "source": "seed-adleman-1994-detailed",
            "locator": "Note 6",
            "label": ""
          },
          {
            "from": "bench",
            "to": "capture",
            "type": "control",
            "source": "seed-adleman-1994-detailed",
            "locator": "Note 7",
            "label": "repeat capture for vertices 1–5"
          }
        ]
      },
      "researchDepth": "architecture-dossier",
      "originalCandidate": "Adleman DNA experiment"
    },
    {
      "status": "dossier",
      "aliases": [
        "D2NN",
        "D²NN"
      ],
      "models": [
        "neural"
      ],
      "sources": [
        "seed-d2nn-paper",
        "optical-paper"
      ],
      "id": "diffractive-network",
      "name": "Diffractive neural network — 2018 THz digit classifier",
      "organization": "Lin et al. / UCLA",
      "year": 2018,
      "yearLabel": "2018 fixed five-layer experimental classifier",
      "kind": "Optical laboratory experiment",
      "paradigms": [
        "optical",
        "analog"
      ],
      "architectures": [
        "optical-linear"
      ],
      "substrates": [
        "photonic"
      ],
      "summary": "An optical inference demonstrator in which trained diffractive surfaces transform light propagation.",
      "config": "The 3D-printed phase-mask digit classifier and its laboratory measurement chain in Figures 1–2. The separate imaging-lens experiment and proposed reconfigurable variants are excluded.",
      "insight": "Which part of a learning system is actually implemented in optics?",
      "fields": {
        "state": {
          "value": "Coherent optical field; fixed phase profiles",
          "source": "seed-d2nn-paper",
          "locator": "pp. 6–7; Figure 1"
        },
        "compute": {
          "value": "Five transmissive diffractive layers",
          "source": "seed-d2nn-paper",
          "locator": "p. 18, Figure 2A"
        },
        "memory": {
          "value": "Fabricated layer profiles retain the trained design",
          "source": "seed-d2nn-paper",
          "locator": "pp. 2–3; Figure 1"
        },
        "control": {
          "value": "Offline numerical training; fixed optical inference",
          "source": "seed-d2nn-paper",
          "locator": "pp. 2–3; Figure 1"
        },
        "io": {
          "value": "0.4 THz illumination and scanned output detection",
          "source": "seed-d2nn-paper",
          "locator": "pp. 7, 18; Figure 2C–D"
        },
        "software": {
          "value": "Backpropagation designs the phase masks before fabrication",
          "source": "seed-d2nn-paper",
          "locator": "pp. 3–6"
        },
        "workload": {
          "value": "Handwritten-digit classification demonstration",
          "source": "seed-d2nn-paper",
          "locator": "pp. 6–7"
        }
      },
      "gaps": [
        "The 50 printed experimental inputs were selected from successful numerical examples; they are not an independent random accuracy test.",
        "Numerical training, sources, scanning, electronics, and readout remain outside the passive optical transform.",
        "No end-to-end application speedup or general-purpose learning capability is inferred."
      ],
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Offline mask design and the measured optical inference chain",
        "width": 1120,
        "height": 535,
        "scope": "The laboratory classifier from Figures 1–2. Training/fabrication links are associations between stages, not signals inside the passive optical network.",
        "nodes": [
          {
            "id": "train",
            "label": "Numerical training",
            "subtitle": "OFFLINE BACKPROPAGATION",
            "text": "Optimizes the layer phase profiles.",
            "x": 25,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-d2nn-paper",
            "locator": "pp. 3–6; Figure 1",
            "control": true
          },
          {
            "id": "print",
            "label": "Mask fabrication",
            "subtitle": "3D-PRINTED PHASE LAYERS",
            "text": "Realizes the trained layer geometry.",
            "x": 310,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-d2nn-paper",
            "locator": "p. 18, Figure 2A",
            "control": false
          },
          {
            "id": "rf",
            "label": "RF synthesis",
            "subtitle": "SOURCE / DETECTOR REFERENCE",
            "text": "Drives the generation and detection chains.",
            "x": 595,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-d2nn-paper",
            "locator": "p. 18, Figure 2C",
            "control": true
          },
          {
            "id": "thz",
            "label": "THz generation chain",
            "subtitle": "0.4 THz ILLUMINATION",
            "text": "Produces the coherent incident radiation.",
            "x": 880,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-d2nn-paper",
            "locator": "p. 18, Figure 2C",
            "control": false
          },
          {
            "id": "input",
            "label": "Printed input digit",
            "subtitle": "AMPLITUDE OBJECT",
            "text": "Encodes the input at the optical plane.",
            "x": 880,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-d2nn-paper",
            "locator": "pp. 6–7; Figure 2D",
            "control": false
          },
          {
            "id": "layers",
            "label": "Five phase-mask layers",
            "subtitle": "PASSIVE DIFFRACTION",
            "text": "Transform the wave through propagation.",
            "x": 595,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-d2nn-paper",
            "locator": "Figures 1B and 2A",
            "control": false
          },
          {
            "id": "plane",
            "label": "Output plane",
            "subtitle": "TEN CLASS REGIONS",
            "text": "Contains the resulting intensity pattern.",
            "x": 310,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-d2nn-paper",
            "locator": "pp. 6–7; Figure 1B",
            "control": false
          },
          {
            "id": "detector",
            "label": "Scanned THz detector",
            "subtitle": "MIXER / AMPLIFIER CHAIN",
            "text": "Measures the output distribution.",
            "x": 25,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-d2nn-paper",
            "locator": "p. 18, Figure 2C–D",
            "control": false
          },
          {
            "id": "readout",
            "label": "Electronic readout",
            "subtitle": "FILTER / POWER / LOCK-IN",
            "text": "Records the measured signal.",
            "x": 25,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "seed-d2nn-paper",
            "locator": "p. 18, Figure 2C",
            "control": false
          },
          {
            "id": "criterion",
            "label": "Class-selection criterion",
            "subtitle": "MAXIMUM REGION SIGNAL",
            "text": "Interprets the class-region intensities.",
            "x": 310,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "seed-d2nn-paper",
            "locator": "p. 6, classification criterion",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "train",
            "to": "print",
            "type": "association",
            "source": "seed-d2nn-paper",
            "locator": "Figures 1A and 2A",
            "label": "design",
            "note": ""
          },
          {
            "from": "print",
            "to": "layers",
            "type": "association",
            "source": "seed-d2nn-paper",
            "locator": "Figure 2A",
            "label": "fabrication",
            "note": ""
          },
          {
            "from": "rf",
            "to": "thz",
            "type": "control",
            "source": "seed-d2nn-paper",
            "locator": "Figure 2C",
            "label": "",
            "note": ""
          },
          {
            "from": "thz",
            "to": "input",
            "type": "data",
            "source": "seed-d2nn-paper",
            "locator": "Figure 2C",
            "label": "",
            "note": ""
          },
          {
            "from": "input",
            "to": "layers",
            "type": "data",
            "source": "seed-d2nn-paper",
            "locator": "Figures 1B and 2C",
            "label": "",
            "note": ""
          },
          {
            "from": "layers",
            "to": "plane",
            "type": "data",
            "source": "seed-d2nn-paper",
            "locator": "Figure 1B",
            "label": "",
            "note": ""
          },
          {
            "from": "plane",
            "to": "detector",
            "type": "data",
            "source": "seed-d2nn-paper",
            "locator": "Figure 2C–D",
            "label": "",
            "note": ""
          },
          {
            "from": "rf",
            "to": "detector",
            "type": "control",
            "source": "seed-d2nn-paper",
            "locator": "Figure 2C",
            "label": "reference",
            "note": ""
          },
          {
            "from": "detector",
            "to": "readout",
            "type": "data",
            "source": "seed-d2nn-paper",
            "locator": "Figure 2C",
            "label": "",
            "note": ""
          },
          {
            "from": "readout",
            "to": "criterion",
            "type": "association",
            "source": "seed-d2nn-paper",
            "locator": "p. 6 and Figure 2C",
            "label": "interpretation",
            "note": ""
          }
        ]
      },
      "originalCandidate": "Diffractive neural network"
    },
    {
      "status": "dossier",
      "aliases": [],
      "models": [
        "register",
        "process"
      ],
      "sources": [
        "seed-a64fx-manual",
        "seed-fugaku-system",
        "fugaku-spec",
        "fugaku-paper"
      ],
      "id": "fugaku",
      "name": "Fugaku",
      "organization": "RIKEN / Fujitsu",
      "year": 2022,
      "yearLabel": "2022 public A64FX manual; published system specification",
      "kind": "Supercomputer",
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "distributed",
        "mimd",
        "vector",
        "load-store",
        "numa",
        "superscalar"
      ],
      "substrates": [
        "integrated"
      ],
      "summary": "A distributed-memory A64FX system coupling Arm vector execution with HBM2 and the Tofu D interconnect.",
      "config": "Published 158,976-node Fugaku system and its A64FX organization. The 52-core chip and the active assistant-core counts of different node variants are distinguished.",
      "insight": "How are node-local bandwidth and machine-wide communication balanced?",
      "fields": {
        "state": {
          "value": "Armv8.2-A; implemented SVE vector lengths through 512 bits",
          "source": "seed-a64fx-manual",
          "locator": "§§1.1–1.2"
        },
        "compute": {
          "value": "48 computational cores per node; four CMGs",
          "source": "seed-fugaku-system",
          "locator": "Node specifications"
        },
        "memory": {
          "value": "32 GiB HBM2 per node; 8 MiB L2 per CMG",
          "source": "seed-fugaku-system",
          "locator": "Node memory and cache"
        },
        "control": {
          "value": "Out-of-order cores with coherent on-chip NUMA groups",
          "source": "seed-a64fx-manual",
          "locator": "§1.1"
        },
        "io": {
          "value": "Six-dimensional Tofu D mesh/torus; PCIe Gen3",
          "source": "seed-fugaku-system",
          "locator": "Tofu D and node specifications"
        },
        "software": {
          "value": "Linux / McKernel, MPI, and layered I/O",
          "source": "seed-fugaku-system",
          "locator": "System software"
        },
        "workload": {
          "value": "Scientific parallel applications",
          "source": "fugaku-paper",
          "locator": "Design-paper abstract"
        }
      },
      "gaps": [
        "The chip contains 13 core positions per CMG; enabled compute/assistant roles depend on the node variant.",
        "The diagram shows a representative CMG and inter-node organization, not every core or cable.",
        "No peak arithmetic figure is treated as measured application performance."
      ],
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "A64FX memory groups inside a distributed-memory machine",
        "width": 1120,
        "height": 535,
        "scope": "One CMG is expanded; three peer CMGs are aggregated. Interconnect and storage relationships follow the public operator description; no unpublished physical routing is inferred.",
        "nodes": [
          {
            "id": "cores",
            "label": "Cores in one CMG",
            "subtitle": "CORE-LOCAL L1 CACHES",
            "text": "Execute scalar and vector instructions.",
            "x": 25,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-a64fx-manual",
            "locator": "§§1.1–1.2",
            "control": false
          },
          {
            "id": "l2",
            "label": "CMG L2 cache",
            "subtitle": "8 MiB SHARED",
            "text": "Coherent cache for the group.",
            "x": 310,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-a64fx-manual",
            "locator": "§§1.1–1.2",
            "control": false
          },
          {
            "id": "mac",
            "label": "Memory controller",
            "subtitle": "ONE PER CMG",
            "text": "Connects the group to local main memory.",
            "x": 595,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-a64fx-manual",
            "locator": "§1.3, Table 1-2",
            "control": false
          },
          {
            "id": "hbm",
            "label": "HBM2 memory",
            "subtitle": "32 GiB / NODE TOTAL",
            "text": "Node-local high-bandwidth main memory.",
            "x": 880,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-fugaku-system",
            "locator": "Node memory",
            "control": false
          },
          {
            "id": "peers",
            "label": "Three peer CMGs",
            "subtitle": "FOUR GROUPS TOTAL",
            "text": "Other coherent NUMA groups on the chip.",
            "x": 25,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-a64fx-manual",
            "locator": "§1.1",
            "control": false
          },
          {
            "id": "router",
            "label": "On-chip routing",
            "subtitle": "COHERENT NUMA",
            "text": "Connects the CMGs and integrated controllers.",
            "x": 310,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-a64fx-manual",
            "locator": "§1.3, Figure 1-1",
            "control": false
          },
          {
            "id": "tofu",
            "label": "Tofu D controller",
            "subtitle": "INTEGRATED IN A64FX",
            "text": "Connects the node to the machine network.",
            "x": 595,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-a64fx-manual",
            "locator": "§§1.2–1.3",
            "control": false
          },
          {
            "id": "remote",
            "label": "Other compute nodes",
            "subtitle": "6D MESH / TORUS",
            "text": "Exchange remote data through Tofu D.",
            "x": 880,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-fugaku-system",
            "locator": "Tofu Interconnect D",
            "control": false
          },
          {
            "id": "pcie",
            "label": "PCIe root complex",
            "subtitle": "GEN3 ×16",
            "text": "Provides the node’s PCIe interface.",
            "x": 310,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "seed-a64fx-manual",
            "locator": "§§1.2–1.3",
            "control": false
          },
          {
            "id": "storage",
            "label": "Layered storage",
            "subtitle": "LLIO / FEFS",
            "text": "Provides temporary, cache, and shared storage roles.",
            "x": 880,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "seed-fugaku-system",
            "locator": "Storage and I/O network",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cores",
            "to": "l2",
            "type": "data",
            "source": "seed-a64fx-manual",
            "locator": "§1.1, CMG",
            "label": "",
            "note": ""
          },
          {
            "from": "l2",
            "to": "cores",
            "type": "data",
            "source": "seed-a64fx-manual",
            "locator": "§1.1, CMG",
            "label": "",
            "note": ""
          },
          {
            "from": "l2",
            "to": "mac",
            "type": "data",
            "source": "seed-a64fx-manual",
            "locator": "§1.1, CMG",
            "label": "",
            "note": ""
          },
          {
            "from": "mac",
            "to": "hbm",
            "type": "data",
            "source": "seed-a64fx-manual",
            "locator": "§1.1, HBM2",
            "label": "",
            "note": ""
          },
          {
            "from": "hbm",
            "to": "mac",
            "type": "data",
            "source": "seed-a64fx-manual",
            "locator": "§1.1, HBM2",
            "label": "",
            "note": ""
          },
          {
            "from": "l2",
            "to": "router",
            "type": "data",
            "source": "seed-a64fx-manual",
            "locator": "§1.3, Figure 1-1",
            "label": "",
            "note": ""
          },
          {
            "from": "peers",
            "to": "router",
            "type": "data",
            "source": "seed-a64fx-manual",
            "locator": "§1.1, coherent NUMA",
            "label": "",
            "note": ""
          },
          {
            "from": "router",
            "to": "peers",
            "type": "data",
            "source": "seed-a64fx-manual",
            "locator": "§1.1, coherent NUMA",
            "label": "",
            "note": ""
          },
          {
            "from": "router",
            "to": "tofu",
            "type": "association",
            "source": "seed-a64fx-manual",
            "locator": "§1.3, integrated controller organization",
            "label": "",
            "note": ""
          },
          {
            "from": "tofu",
            "to": "remote",
            "type": "data",
            "source": "seed-fugaku-system",
            "locator": "Tofu Interconnect D",
            "label": "",
            "note": ""
          },
          {
            "from": "remote",
            "to": "tofu",
            "type": "data",
            "source": "seed-fugaku-system",
            "locator": "Tofu Interconnect D",
            "label": "",
            "note": ""
          },
          {
            "from": "router",
            "to": "pcie",
            "type": "association",
            "source": "seed-a64fx-manual",
            "locator": "§1.3, integrated controller organization",
            "label": "",
            "note": ""
          },
          {
            "from": "remote",
            "to": "storage",
            "type": "association",
            "source": "seed-fugaku-system",
            "locator": "I/O network and storage",
            "label": "",
            "note": ""
          }
        ]
      },
      "originalCandidate": "Fugaku"
    },
    {
      "status": "dossier",
      "aliases": [],
      "models": [
        "neural"
      ],
      "sources": [
        "seed-loihi2-detailed"
      ],
      "id": "loihi-2",
      "name": "Loihi 2",
      "organization": "Intel Labs",
      "year": 2021,
      "yearLabel": "2021 technology brief",
      "kind": "Research processor",
      "paradigms": [
        "digital",
        "neuromorphic",
        "parallel"
      ],
      "architectures": [
        "spiking"
      ],
      "substrates": [
        "integrated"
      ],
      "summary": "Neuron microcode and learning share partitioned memory behind asynchronous routing.",
      "config": "2021 chip: 128 neuromorphic cores maximum, six embedded processors, 8×16-core mesh.",
      "insight": "How does event communication change where state and computation live?",
      "fields": {
        "state": {
          "value": "Neuron variables, traces and graded spike payloads",
          "source": "seed-loihi2-detailed",
          "locator": "pp. 5–7"
        },
        "compute": {
          "value": "128 asynchronous neural cores; six support processors",
          "source": "seed-loihi2-detailed",
          "locator": "p. 5; Table 2"
        },
        "memory": {
          "value": "192 KB per neural core, flexibly partitioned",
          "source": "seed-loihi2-detailed",
          "locator": "p. 6; Table 2"
        },
        "control": {
          "value": "Neuron microcode; NoC timestep handshaking",
          "source": "seed-loihi2-detailed",
          "locator": "Table 1; Table 2"
        },
        "io": {
          "value": "Spike I/O encoding; Ethernet, SPI, AER, GPIO",
          "source": "seed-loihi2-detailed",
          "locator": "p. 6"
        },
        "software": {
          "value": "Lava framework and embedded C support",
          "source": "seed-loihi2-detailed",
          "locator": "pp. 4–5"
        },
        "workload": {
          "value": "Programmable neural inference, dynamics and learning",
          "source": "seed-loihi2-detailed",
          "locator": "pp. 5–6"
        }
      },
      "gaps": [
        "Core memory is shared across features; maximum neurons/synapses are not simultaneously guaranteed.",
        "Board interfaces and deployed topology require separate evidence.",
        "Manufacturer benchmarks mix measurement and simulation."
      ],
      "diagram": {
        "title": "A programmable neural core inside the event fabric",
        "width": 1020,
        "height": 500,
        "scope": "Figs. 1–2 representative-core functions; internal resources are aggregated.",
        "nodes": [
          {
            "id": "io",
            "label": "Spike I/O module",
            "subtitle": "EXTERNAL BOUNDARY",
            "text": "Encodes incoming data as events.",
            "x": 25,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-loihi2-detailed",
            "locator": "p. 6 I/O and Scalability",
            "control": false
          },
          {
            "id": "mesh",
            "label": "Asynchronous NoC",
            "subtitle": "8×16 MESH",
            "text": "Routes and synchronizes events.",
            "x": 265,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-loihi2-detailed",
            "locator": "Fig. 1; Table 2",
            "control": false
          },
          {
            "id": "support",
            "label": "Embedded processors",
            "subtitle": "SIX SUPPORT CORES",
            "text": "Runs configuration and I/O code.",
            "x": 505,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-loihi2-detailed",
            "locator": "p. 5",
            "control": true
          },
          {
            "id": "offchip",
            "label": "Parallel chip links",
            "subtitle": "SYSTEM BOUNDARY",
            "text": "Extends mesh to other chips.",
            "x": 745,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-loihi2-detailed",
            "locator": "Fig. 1; p. 6",
            "control": false
          },
          {
            "id": "synapse",
            "label": "Synapse processing",
            "subtitle": "EVENT WEIGHTS",
            "text": "Combines events and connectivity.",
            "x": 265,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-loihi2-detailed",
            "locator": "p. 5; Fig. 2",
            "control": false
          },
          {
            "id": "neuron",
            "label": "Neuron microcode",
            "subtitle": "STATE UPDATE",
            "text": "Executes programmed dynamics.",
            "x": 505,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-loihi2-detailed",
            "locator": "Table 1",
            "control": false
          },
          {
            "id": "mem",
            "label": "Flexible local memory",
            "subtitle": "192 KB / CORE",
            "text": "Holds state, synapses and routing.",
            "x": 745,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-loihi2-detailed",
            "locator": "Fig. 2; Table 2",
            "control": false
          },
          {
            "id": "learn",
            "label": "Learning rules",
            "subtitle": "THREE-FACTOR TRACES",
            "text": "Updates synaptic parameters.",
            "x": 745,
            "y": 380,
            "w": 180,
            "h": 66,
            "source": "seed-loihi2-detailed",
            "locator": "pp. 5–6",
            "control": false
          },
          {
            "id": "axon",
            "label": "Axon routing / emission",
            "subtitle": "OUTPUT SPIKES",
            "text": "Addresses downstream targets.",
            "x": 265,
            "y": 380,
            "w": 180,
            "h": 66,
            "source": "seed-loihi2-detailed",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "probe",
            "label": "Probe events",
            "subtitle": "READOUT",
            "text": "Exports selected neural state.",
            "x": 505,
            "y": 380,
            "w": 180,
            "h": 66,
            "source": "seed-loihi2-detailed",
            "locator": "Table 1; Table 2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "io",
            "to": "mesh",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "p. 6",
            "label": ""
          },
          {
            "from": "support",
            "to": "mesh",
            "type": "control",
            "source": "seed-loihi2-detailed",
            "locator": "p. 5",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "support",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "p. 5",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "offchip",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "Fig. 1",
            "label": ""
          },
          {
            "from": "offchip",
            "to": "mesh",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "Fig. 1",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "synapse",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "Figs. 1–2",
            "label": ""
          },
          {
            "from": "synapse",
            "to": "neuron",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "mem",
            "to": "synapse",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "mem",
            "to": "neuron",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "Table 1",
            "label": ""
          },
          {
            "from": "neuron",
            "to": "mem",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "Table 1",
            "label": ""
          },
          {
            "from": "neuron",
            "to": "learn",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "pp. 5–6",
            "label": ""
          },
          {
            "from": "learn",
            "to": "mem",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "pp. 5–6",
            "label": ""
          },
          {
            "from": "neuron",
            "to": "axon",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "axon",
            "to": "mesh",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "Figs. 1–2",
            "label": ""
          },
          {
            "from": "neuron",
            "to": "probe",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "Table 1",
            "label": ""
          },
          {
            "from": "probe",
            "to": "support",
            "type": "data",
            "source": "seed-loihi2-detailed",
            "locator": "Table 1",
            "label": ""
          }
        ]
      },
      "researchDepth": "architecture-dossier",
      "originalCandidate": "Loihi 2"
    },
    {
      "status": "dossier",
      "aliases": [],
      "models": [
        "quantum-circuit"
      ],
      "sources": [
        "seed-ibm-system2-launch",
        "seed-ibm-2023-letter"
      ],
      "id": "ibm-quantum-two",
      "name": "IBM Quantum System Two",
      "organization": "IBM",
      "year": 2023,
      "yearLabel": "4 December 2023 configuration",
      "kind": "Quantum system",
      "paradigms": [
        "quantum",
        "hybrid"
      ],
      "architectures": [
        "gate-quantum",
        "heterogeneous"
      ],
      "substrates": [
        "superconducting",
        "integrated"
      ],
      "summary": "Modular cryogenic and classical infrastructure hosts three quantum processors for classically coordinated circuit workloads.",
      "config": "Yorktown Heights initial installation announced 4 December 2023: three Heron processors with supporting classical control; February 2024 retrospective confirms classical interprocessor communication.",
      "insight": "What must surround a quantum processor to make it a usable system?",
      "fields": {
        "state": {
          "value": "Separate processor quantum states and classical workflow state",
          "source": "seed-ibm-2023-letter",
          "locator": "IBM Quantum System Two"
        },
        "compute": {
          "value": "Three initial Heron processors",
          "source": "seed-ibm-system2-launch",
          "locator": "Initial operation"
        },
        "memory": {
          "value": "Quantum circuit state; classical runtime resources",
          "source": "seed-ibm-system2-launch",
          "locator": "System Two organization"
        },
        "control": {
          "value": "Classical runtime servers and modular qubit controls",
          "source": "seed-ibm-system2-launch",
          "locator": "System Two organization"
        },
        "io": {
          "value": "Classically communicated circuit workflows/results",
          "source": "seed-ibm-2023-letter",
          "locator": "IBM Quantum System Two; Utility-scale software"
        },
        "software": {
          "value": "Qiskit circuit/runtime workflow; Patterns announced",
          "source": "seed-ibm-system2-launch",
          "locator": "Qiskit and Generative AI"
        },
        "workload": {
          "value": "Circuit execution and classical parallelization",
          "source": "seed-ibm-2023-letter",
          "locator": "IBM Quantum System Two"
        }
      },
      "gaps": [
        "No coherent inter-QPU quantum link or combined 399-qubit register is established.",
        "Cryostat wiring, per-channel control/readout timing and calibration details are not disclosed in these sources.",
        "Later processors, error-corrected operation and roadmap capacities are outside this configuration."
      ],
      "diagram": {
        "title": "Three processors coordinated across a classical boundary",
        "width": 1020,
        "height": 500,
        "scope": "System-level functional diagram from manufacturer descriptions. Quantum links between processors are absent; measurement return paths aggregate undisclosed electronics.",
        "nodes": [
          {
            "id": "program",
            "label": "Qiskit circuit preparation",
            "subtitle": "CLASSICAL SOFTWARE",
            "text": "Maps and optimizes circuits.",
            "x": 25,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-ibm-system2-launch",
            "locator": "Qiskit and Generative AI",
            "control": false
          },
          {
            "id": "runtime",
            "label": "Classical runtime servers",
            "subtitle": "WORKFLOW EXECUTION",
            "text": "Coordinates circuit tasks.",
            "x": 265,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-ibm-system2-launch",
            "locator": "System Two organization",
            "control": true
          },
          {
            "id": "control",
            "label": "Modular control electronics",
            "subtitle": "CLASSICAL ↔ QUANTUM",
            "text": "Operates processor resources.",
            "x": 505,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-ibm-system2-launch",
            "locator": "System Two organization",
            "control": true
          },
          {
            "id": "cryo",
            "label": "Cryogenic infrastructure",
            "subtitle": "PHYSICAL SUPPORT",
            "text": "Supports the processor environment.",
            "x": 745,
            "y": 30,
            "w": 180,
            "h": 66,
            "source": "seed-ibm-system2-launch",
            "locator": "System Two organization",
            "control": false
          },
          {
            "id": "h1",
            "label": "Heron processor A",
            "subtitle": "SEPARATE QPU",
            "text": "Executes a circuit state.",
            "x": 25,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-ibm-system2-launch",
            "locator": "Initial operation",
            "control": false
          },
          {
            "id": "h2",
            "label": "Heron processor B",
            "subtitle": "SEPARATE QPU",
            "text": "Executes a circuit state.",
            "x": 265,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-ibm-system2-launch",
            "locator": "Initial operation",
            "control": false
          },
          {
            "id": "h3",
            "label": "Heron processor C",
            "subtitle": "SEPARATE QPU",
            "text": "Executes a circuit state.",
            "x": 505,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-ibm-system2-launch",
            "locator": "Initial operation",
            "control": false
          },
          {
            "id": "result",
            "label": "Classical result handling",
            "subtitle": "READOUT BOUNDARY",
            "text": "Collects circuit outcomes.",
            "x": 745,
            "y": 205,
            "w": 180,
            "h": 66,
            "source": "seed-ibm-system2-launch",
            "locator": "Qiskit Patterns",
            "control": false
          },
          {
            "id": "post",
            "label": "Classical postprocessing",
            "subtitle": "WORKFLOW OUTPUT",
            "text": "Interprets measured results.",
            "x": 745,
            "y": 380,
            "w": 180,
            "h": 66,
            "source": "seed-ibm-system2-launch",
            "locator": "Qiskit Patterns",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "program",
            "to": "runtime",
            "type": "control",
            "source": "seed-ibm-system2-launch",
            "locator": "Qiskit Patterns",
            "label": ""
          },
          {
            "from": "runtime",
            "to": "control",
            "type": "control",
            "source": "seed-ibm-system2-launch",
            "locator": "System Two organization",
            "label": ""
          },
          {
            "from": "control",
            "to": "h1",
            "type": "control",
            "source": "seed-ibm-system2-launch",
            "locator": "Initial operation",
            "label": ""
          },
          {
            "from": "control",
            "to": "h2",
            "type": "control",
            "source": "seed-ibm-system2-launch",
            "locator": "Initial operation",
            "label": ""
          },
          {
            "from": "control",
            "to": "h3",
            "type": "control",
            "source": "seed-ibm-system2-launch",
            "locator": "Initial operation",
            "label": ""
          },
          {
            "from": "cryo",
            "to": "h1",
            "type": "association",
            "source": "seed-ibm-system2-launch",
            "locator": "System Two organization",
            "label": ""
          },
          {
            "from": "cryo",
            "to": "h2",
            "type": "association",
            "source": "seed-ibm-system2-launch",
            "locator": "System Two organization",
            "label": ""
          },
          {
            "from": "cryo",
            "to": "h3",
            "type": "association",
            "source": "seed-ibm-system2-launch",
            "locator": "System Two organization",
            "label": ""
          },
          {
            "from": "h1",
            "to": "result",
            "type": "data",
            "source": "seed-ibm-system2-launch",
            "locator": "Qiskit Patterns",
            "label": "measurement outcome"
          },
          {
            "from": "h2",
            "to": "result",
            "type": "data",
            "source": "seed-ibm-system2-launch",
            "locator": "Qiskit Patterns",
            "label": "measurement outcome"
          },
          {
            "from": "h3",
            "to": "result",
            "type": "data",
            "source": "seed-ibm-system2-launch",
            "locator": "Qiskit Patterns",
            "label": "measurement outcome"
          },
          {
            "from": "result",
            "to": "runtime",
            "type": "data",
            "source": "seed-ibm-2023-letter",
            "locator": "IBM Quantum System Two",
            "label": "classical coordination"
          },
          {
            "from": "runtime",
            "to": "post",
            "type": "data",
            "source": "seed-ibm-system2-launch",
            "locator": "Qiskit Patterns",
            "label": ""
          }
        ]
      },
      "researchDepth": "architecture-dossier",
      "originalCandidate": "IBM Quantum System Two"
    },
    {
      "status": "dossier",
      "aliases": [],
      "models": [
        "neural"
      ],
      "sources": [
        "seed-hala-announcement",
        "loihi-brief"
      ],
      "id": "hala-point",
      "name": "Hala Point",
      "organization": "Intel / Sandia National Laboratories",
      "year": 2024,
      "yearLabel": "17 April 2024 announcement",
      "kind": "Neuromorphic research system",
      "paradigms": [
        "digital",
        "neuromorphic",
        "parallel"
      ],
      "architectures": [
        "spiking",
        "distributed",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "uses": [
        "loihi-2"
      ],
      "summary": "A multi-chip neuromorphic research system built around Loihi 2 processors, with embedded processors for supporting work.",
      "config": "The April 2024 six-rack-unit Hala Point research prototype. Its disclosed system hierarchy is linked to the separately documented Loihi 2 chip architecture; undisclosed board routing is not filled in.",
      "insight": "What changes when a neuromorphic architecture scales beyond one chip?",
      "fields": {
        "state": {
          "value": "Distributed neural and synaptic state",
          "source": "seed-hala-announcement",
          "locator": "p. 2, About Hala Point"
        },
        "compute": {
          "value": "1,152 Loihi 2 chips; 140,544 neuromorphic cores system-wide",
          "source": "seed-hala-announcement",
          "locator": "p. 2"
        },
        "memory": {
          "value": "Local state integrated with neural processing",
          "source": "loihi-brief",
          "locator": "pp. 5–7"
        },
        "control": {
          "value": "Embedded x86 processors for ancillary computation",
          "source": "seed-hala-announcement",
          "locator": "p. 2"
        },
        "io": {
          "value": "Distinct inter-core and inter-chip communication fabrics",
          "source": "seed-hala-announcement",
          "locator": "p. 2"
        },
        "software": {
          "value": "Research workloads; no complete deployment stack disclosed",
          "source": "seed-hala-announcement",
          "locator": "pp. 1–3, disclosure scope"
        },
        "workload": {
          "value": "Neuromorphic and conventional neural-network research",
          "source": "seed-hala-announcement",
          "locator": "pp. 1–3"
        }
      },
      "gaps": [
        "No board graph, exact link allocation, host attachment path, or full software deployment is publicly established by these sources.",
        "Loihi 2’s maximum per-chip capacity is not substituted for the enabled system-wide core count.",
        "Reported efficiency uses the source’s specified sparse MLP and activity conditions; it is not a generic GPU comparison."
      ],
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Disclosed system hierarchy and local event processing",
        "width": 1120,
        "height": 535,
        "scope": "System hierarchy from the Intel release; local chip roles from the 2021 Loihi 2 brief. Dotted relationships indicate membership/support, not guessed physical links.",
        "nodes": [
          {
            "id": "system",
            "label": "Hala Point chassis",
            "subtitle": "6 RACK UNITS",
            "text": "Contains the announced research system.",
            "x": 25,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-hala-announcement",
            "locator": "p. 2",
            "control": false
          },
          {
            "id": "chips",
            "label": "Loihi 2 processors",
            "subtitle": "1,152 CHIPS",
            "text": "Provide distributed neuromorphic resources.",
            "x": 310,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-hala-announcement",
            "locator": "p. 2",
            "control": false
          },
          {
            "id": "interchip",
            "label": "Inter-chip communication",
            "subtitle": "SYSTEM FABRIC",
            "text": "Connects the distributed chip resources.",
            "x": 595,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-hala-announcement",
            "locator": "p. 2",
            "control": false
          },
          {
            "id": "support",
            "label": "Embedded x86 processors",
            "subtitle": "ANCILLARY COMPUTATION",
            "text": "Perform supporting system computations.",
            "x": 880,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "seed-hala-announcement",
            "locator": "p. 2",
            "control": true
          },
          {
            "id": "cores",
            "label": "Neuromorphic cores",
            "subtitle": "140,544 SYSTEM-WIDE",
            "text": "Process neural state and events.",
            "x": 310,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "seed-hala-announcement",
            "locator": "p. 2",
            "control": false
          },
          {
            "id": "noc",
            "label": "On-chip network",
            "subtitle": "SPIKE MESSAGES",
            "text": "Routes messages among Loihi 2 cores.",
            "x": 595,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "loihi-brief",
            "locator": "p. 5",
            "control": false
          },
          {
            "id": "state",
            "label": "Neuron / synaptic state",
            "subtitle": "LOCAL MEMORY",
            "text": "Retains models and interactions in a core.",
            "x": 25,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "loihi-brief",
            "locator": "pp. 5–7",
            "control": false
          },
          {
            "id": "dynamics",
            "label": "Programmable dynamics",
            "subtitle": "EVENT-DRIVEN UPDATES",
            "text": "Updates neuron state using programmed models.",
            "x": 310,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "loihi-brief",
            "locator": "pp. 5–7",
            "control": false
          },
          {
            "id": "interfaces",
            "label": "Chip interfaces",
            "subtitle": "EXTERNAL EVENT EXCHANGE",
            "text": "Support communication with other devices.",
            "x": 595,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "loihi-brief",
            "locator": "p. 6",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "system",
            "to": "chips",
            "type": "association",
            "source": "seed-hala-announcement",
            "locator": "p. 2",
            "label": "contains",
            "note": ""
          },
          {
            "from": "system",
            "to": "support",
            "type": "association",
            "source": "seed-hala-announcement",
            "locator": "p. 2",
            "label": "contains",
            "note": ""
          },
          {
            "from": "chips",
            "to": "interchip",
            "type": "association",
            "source": "seed-hala-announcement",
            "locator": "p. 2",
            "label": "system communication",
            "note": ""
          },
          {
            "from": "chips",
            "to": "cores",
            "type": "association",
            "source": "seed-hala-announcement",
            "locator": "p. 2",
            "label": "contains",
            "note": ""
          },
          {
            "from": "cores",
            "to": "noc",
            "type": "data",
            "source": "loihi-brief",
            "locator": "p. 5",
            "label": "",
            "note": ""
          },
          {
            "from": "noc",
            "to": "cores",
            "type": "data",
            "source": "loihi-brief",
            "locator": "p. 5",
            "label": "",
            "note": ""
          },
          {
            "from": "cores",
            "to": "state",
            "type": "association",
            "source": "loihi-brief",
            "locator": "pp. 5–7",
            "label": "local state",
            "note": ""
          },
          {
            "from": "cores",
            "to": "dynamics",
            "type": "association",
            "source": "loihi-brief",
            "locator": "pp. 5–7",
            "label": "local processing",
            "note": ""
          },
          {
            "from": "state",
            "to": "dynamics",
            "type": "data",
            "source": "loihi-brief",
            "locator": "pp. 5–7",
            "label": "",
            "note": ""
          },
          {
            "from": "dynamics",
            "to": "state",
            "type": "data",
            "source": "loihi-brief",
            "locator": "pp. 5–7",
            "label": "",
            "note": ""
          },
          {
            "from": "noc",
            "to": "interfaces",
            "type": "data",
            "source": "loihi-brief",
            "locator": "pp. 5–6",
            "label": "",
            "note": ""
          },
          {
            "from": "interfaces",
            "to": "interchip",
            "type": "association",
            "source": "seed-hala-announcement",
            "locator": "p. 2",
            "label": "system role",
            "note": ""
          }
        ]
      },
      "originalCandidate": "Hala Point"
    },
    {
      "id": "queue-001",
      "name": "Babbage Analytical Engine (1843 design)",
      "organization": "Charles Babbage / Menabrea / Lovelace",
      "year": 1843,
      "yearLabel": "1843 published design account",
      "kind": "Unbuilt machine design",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "unconventional"
      ],
      "architectures": [
        "configured",
        "mechanical"
      ],
      "substrates": [
        "mechanical"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-menabrea-1843",
        "hist-lovelace-1843"
      ],
      "summary": "A mechanical design separating arithmetic in a mill from variables in a store and directing both with punched cards.",
      "config": "The 1843 Menabrea–Lovelace account; not a claim that a complete Analytical Engine was built.",
      "gaps": [
        "Several later Babbage designs differ; this is one published account.",
        "No measured speed, complete physical layout, or built implementation is asserted."
      ],
      "originalName": "Babbage Analytical Engine (design)",
      "insight": "How are the choice of operation and the choice of operand kept separate?",
      "fields": {
        "state": {
          "value": "Decimal figure-wheel variables",
          "source": "hist-menabrea-1843",
          "locator": "Mill and store description"
        },
        "compute": {
          "value": "Mill performs arithmetic",
          "source": "hist-menabrea-1843",
          "locator": "Mill and store description"
        },
        "memory": {
          "value": "Columns of variables form the store",
          "source": "hist-menabrea-1843",
          "locator": "Store description"
        },
        "control": {
          "value": "Operation cards and variable cards",
          "source": "hist-menabrea-1843",
          "locator": "Cards description"
        },
        "io": {
          "value": "Number cards and printed results",
          "source": "hist-menabrea-1843",
          "locator": "Number cards and output"
        },
        "software": {
          "value": "A sequence of operation and variable cards",
          "source": "hist-menabrea-1843",
          "locator": "Programming examples"
        },
        "workload": {
          "value": "Algebraic numerical calculations",
          "source": "hist-menabrea-1843",
          "locator": "Simultaneous-equation example"
        }
      },
      "diagram": {
        "title": "Separate operations, variables, and arithmetic",
        "scope": "Conceptual design relationships from the 1843 account and Notes. Card roles are distinct from numerical data.",
        "nodes": [
          {
            "id": "op",
            "label": "Operation cards",
            "subtitle": "OPERATION SEQUENCE",
            "text": "Select the mill operation.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-lovelace-1843",
            "locator": "Note B",
            "control": true
          },
          {
            "id": "supply",
            "label": "Supplying cards",
            "subtitle": "SOURCE SELECTION",
            "text": "Select variables entering the mill.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-lovelace-1843",
            "locator": "Note B",
            "control": true
          },
          {
            "id": "receive",
            "label": "Receiving cards",
            "subtitle": "RESULT DESTINATION",
            "text": "Select columns receiving results.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-lovelace-1843",
            "locator": "Note B",
            "control": true
          },
          {
            "id": "numbers",
            "label": "Number cards",
            "subtitle": "NUMERICAL INPUT",
            "text": "Introduce ready-made constants.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-menabrea-1843",
            "locator": "Cards of numbers",
            "control": false
          },
          {
            "id": "mill",
            "label": "Mill",
            "subtitle": "ARITHMETIC",
            "text": "Operates on a pair of numbers.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-lovelace-1843",
            "locator": "Note B",
            "control": false
          },
          {
            "id": "store",
            "label": "Store",
            "subtitle": "VARIABLE COLUMNS",
            "text": "Retains variables and results.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-menabrea-1843",
            "locator": "Store description",
            "control": false
          },
          {
            "id": "print",
            "label": "Printing mechanism",
            "subtitle": "OUTPUT",
            "text": "Records numerical results.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-menabrea-1843",
            "locator": "Output description",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "op",
            "to": "mill",
            "type": "control",
            "source": "hist-lovelace-1843",
            "locator": "Note B",
            "label": ""
          },
          {
            "from": "supply",
            "to": "store",
            "type": "control",
            "source": "hist-lovelace-1843",
            "locator": "Note B",
            "label": ""
          },
          {
            "from": "supply",
            "to": "mill",
            "type": "control",
            "source": "hist-lovelace-1843",
            "locator": "Note B",
            "label": ""
          },
          {
            "from": "receive",
            "to": "store",
            "type": "control",
            "source": "hist-lovelace-1843",
            "locator": "Note B",
            "label": ""
          },
          {
            "from": "store",
            "to": "mill",
            "type": "data",
            "source": "hist-menabrea-1843",
            "locator": "Mill/store transfers",
            "label": ""
          },
          {
            "from": "mill",
            "to": "store",
            "type": "data",
            "source": "hist-menabrea-1843",
            "locator": "Mill/store transfers",
            "label": ""
          },
          {
            "from": "numbers",
            "to": "mill",
            "type": "data",
            "source": "hist-menabrea-1843",
            "locator": "Cards of numbers",
            "label": ""
          },
          {
            "from": "mill",
            "to": "print",
            "type": "data",
            "source": "hist-menabrea-1843",
            "locator": "Output description",
            "label": ""
          },
          {
            "from": "mill",
            "to": "op",
            "type": "control",
            "source": "hist-menabrea-1843",
            "locator": "Contingent change of cards",
            "label": "conditional sequencing"
          }
        ]
      },
      "originalCandidate": "Babbage Analytical Engine (design)"
    },
    {
      "id": "queue-002",
      "name": "Zuse Z3",
      "organization": "Konrad Zuse",
      "year": 1941,
      "yearLabel": "Original Z3; engineering reconstruction account",
      "kind": "Electromechanical machine",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "configured",
        "hardwired"
      ],
      "substrates": [
        "relay"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-z3-architecture"
      ],
      "summary": "Tape-directed floating-point arithmetic with separate exponent and mantissa datapaths and a 64-cell store.",
      "config": "Original Z3 programming architecture as explained by the ZIB simulation; reconstructed internal roles are identified as such.",
      "gaps": [
        "The source describes a reconstruction model, not a surviving original netlist.",
        "No modern conditional-branch or general-purpose-completeness claim is imported."
      ],
      "insight": "Why split a floating-point operation into exponent and mantissa mechanisms?",
      "fields": {
        "state": {
          "value": "Binary floating-point values",
          "source": "hist-z3-architecture",
          "locator": "Architecture"
        },
        "compute": {
          "value": "Separate exponent and mantissa arithmetic",
          "source": "hist-z3-architecture",
          "locator": "Architecture"
        },
        "memory": {
          "value": "64 floating-point cells",
          "source": "hist-z3-architecture",
          "locator": "Architecture"
        },
        "control": {
          "value": "Punched tape; hardwired microsequencers",
          "source": "hist-z3-architecture",
          "locator": "Clock and instructions"
        },
        "io": {
          "value": "Decimal input and display conversion",
          "source": "hist-z3-architecture",
          "locator": "Read/write instructions"
        },
        "software": {
          "value": "Implicit R1/R2 arithmetic operands",
          "source": "hist-z3-architecture",
          "locator": "Instruction semantics"
        },
        "workload": {
          "value": "Arithmetic instruction sequences",
          "source": "hist-z3-architecture",
          "locator": "Instruction table"
        }
      },
      "diagram": {
        "title": "A split floating-point datapath",
        "scope": "Functional reconstruction from the source; register gating and microsequencer roles are aggregated.",
        "nodes": [
          {
            "id": "tape",
            "label": "Punched program tape",
            "subtitle": "INSTRUCTION INPUT",
            "text": "Supplies operations.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-z3-architecture",
            "locator": "Architecture",
            "control": false
          },
          {
            "id": "control",
            "label": "Microsequencers",
            "subtitle": "HARDWIRED CONTROL",
            "text": "Set gates and arithmetic modes.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-z3-architecture",
            "locator": "Clock",
            "control": true
          },
          {
            "id": "input",
            "label": "Decimal input",
            "subtitle": "CONVERSION",
            "text": "Loads an available operand register.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-z3-architecture",
            "locator": "Read instruction",
            "control": false
          },
          {
            "id": "memory",
            "label": "64-cell store",
            "subtitle": "FLOATING-POINT WORDS",
            "text": "Supports explicit loads and stores.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-z3-architecture",
            "locator": "Architecture",
            "control": false
          },
          {
            "id": "regs",
            "label": "Register pairs",
            "subtitle": "OPERANDS + TEMPORARIES",
            "text": "Separate exponent/mantissa parts.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-z3-architecture",
            "locator": "Architecture",
            "control": false
          },
          {
            "id": "output",
            "label": "Decimal display",
            "subtitle": "CONVERSION",
            "text": "Displays R1 and releases operands.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-z3-architecture",
            "locator": "Output instruction",
            "control": false
          },
          {
            "id": "exp",
            "label": "Exponent arithmetic",
            "subtitle": "PART A",
            "text": "Adder and shifts handle exponents.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-z3-architecture",
            "locator": "Architecture",
            "control": false
          },
          {
            "id": "mant",
            "label": "Mantissa arithmetic",
            "subtitle": "PART B",
            "text": "Adder and multiplexer process mantissas.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-z3-architecture",
            "locator": "Architecture",
            "control": false
          },
          {
            "id": "gates",
            "label": "Gates and shifters",
            "subtitle": "REGISTER TRANSFERS",
            "text": "Control connections and shifts.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-z3-architecture",
            "locator": "Architecture",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "tape",
            "to": "control",
            "type": "control",
            "source": "hist-z3-architecture",
            "locator": "Architecture",
            "label": ""
          },
          {
            "from": "control",
            "to": "regs",
            "type": "control",
            "source": "hist-z3-architecture",
            "locator": "Clock",
            "label": ""
          },
          {
            "from": "memory",
            "to": "regs",
            "type": "data",
            "source": "hist-z3-architecture",
            "locator": "Load instruction",
            "label": ""
          },
          {
            "from": "regs",
            "to": "memory",
            "type": "data",
            "source": "hist-z3-architecture",
            "locator": "Store instruction",
            "label": ""
          },
          {
            "from": "input",
            "to": "regs",
            "type": "data",
            "source": "hist-z3-architecture",
            "locator": "Read instruction",
            "label": ""
          },
          {
            "from": "regs",
            "to": "output",
            "type": "data",
            "source": "hist-z3-architecture",
            "locator": "Output instruction",
            "label": ""
          },
          {
            "from": "regs",
            "to": "exp",
            "type": "data",
            "source": "hist-z3-architecture",
            "locator": "Architecture",
            "label": ""
          },
          {
            "from": "exp",
            "to": "regs",
            "type": "data",
            "source": "hist-z3-architecture",
            "locator": "Architecture",
            "label": ""
          },
          {
            "from": "regs",
            "to": "mant",
            "type": "data",
            "source": "hist-z3-architecture",
            "locator": "Architecture",
            "label": ""
          },
          {
            "from": "mant",
            "to": "regs",
            "type": "data",
            "source": "hist-z3-architecture",
            "locator": "Architecture",
            "label": ""
          },
          {
            "from": "control",
            "to": "gates",
            "type": "control",
            "source": "hist-z3-architecture",
            "locator": "Clock",
            "label": ""
          },
          {
            "from": "gates",
            "to": "regs",
            "type": "association",
            "source": "hist-z3-architecture",
            "locator": "Architecture",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Zuse Z3"
    },
    {
      "id": "queue-003",
      "name": "Zuse Z4 — ETH 1952 configuration",
      "organization": "Zuse / ETH Zürich",
      "year": 1952,
      "yearLabel": "1952 ETH operating manual",
      "kind": "Electromechanical computer",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "configured",
        "hardwired"
      ],
      "substrates": [
        "relay",
        "mechanical"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-z4-eth-manual"
      ],
      "summary": "Two film readers and a film punch surround relay arithmetic, operand registers, and a 64-cell mechanical store.",
      "config": "ETH’s 1952 operating configuration; not the earlier single-reader wartime embodiment.",
      "gaps": [
        "Storage encodes an implicit mantissa bit; the manual distinguishes arithmetic and stored precision.",
        "Original German names are retained in labels where translation could obscure roles."
      ],
      "originalName": "Zuse Z4",
      "insight": "How do separate program and numerical films extend a small mechanical store?",
      "fields": {
        "state": {
          "value": "Binary floating point; 32 stored bits",
          "source": "hist-z4-eth-manual",
          "locator": "p. 1 §1; p. 2 §2"
        },
        "compute": {
          "value": "Arithmetic unit with OR I and OR II",
          "source": "hist-z4-eth-manual",
          "locator": "p. 1 organization"
        },
        "memory": {
          "value": "64 cells, addresses 0–63",
          "source": "hist-z4-eth-manual",
          "locator": "p. 2 §2"
        },
        "control": {
          "value": "Leitwerk and program-film reader At0",
          "source": "hist-z4-eth-manual",
          "locator": "p. 1 diagram; p. 2 §4"
        },
        "io": {
          "value": "At1 reader, film punch, keyboards, lamps and printer",
          "source": "hist-z4-eth-manual",
          "locator": "pp. 1–3"
        },
        "software": {
          "value": "Main/subprogram film and manual command modes",
          "source": "hist-z4-eth-manual",
          "locator": "p. 2 §3"
        },
        "workload": {
          "value": "Numerical calculation sequences",
          "source": "hist-z4-eth-manual",
          "locator": "p. 2 operating modes"
        }
      },
      "diagram": {
        "title": "The ETH Z4 organization",
        "scope": "Original manual p. 1 diagram; OR I/II and At0/At1 remain distinct. Association marks coordination rather than an undocumented physical bus.",
        "nodes": [
          {
            "id": "at0",
            "label": "Reader At0",
            "subtitle": "PROGRAM FILM",
            "text": "Feeds instructions to control.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 diagram",
            "control": false
          },
          {
            "id": "control",
            "label": "Leitwerk",
            "subtitle": "CONTROL",
            "text": "Decodes commands.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-z4-eth-manual",
            "locator": "p. 2 §4",
            "control": true
          },
          {
            "id": "memory",
            "label": "Mechanical store",
            "subtitle": "CELLS 0–63",
            "text": "Retains 32-bit numbers.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-z4-eth-manual",
            "locator": "p. 2 §2",
            "control": false
          },
          {
            "id": "keyboard",
            "label": "Numeric keyboard",
            "subtitle": "DECIMAL INPUT",
            "text": "Provides numbers to arithmetic.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 diagram; p. 3 §6",
            "control": false
          },
          {
            "id": "arithmetic",
            "label": "Arithmetic unit",
            "subtitle": "RECHENWERK",
            "text": "Performs floating-point operations.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 §1",
            "control": false
          },
          {
            "id": "operands",
            "label": "OR I / OR II",
            "subtitle": "OPERAND REGISTERS",
            "text": "Stage operands from storage.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 §1",
            "control": false
          },
          {
            "id": "at1",
            "label": "Reader At1",
            "subtitle": "SUBPROGRAM / NUMBERS",
            "text": "Reads the second film.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-z4-eth-manual",
            "locator": "p. 2 §3",
            "control": false
          },
          {
            "id": "punch",
            "label": "Film punch L",
            "subtitle": "PROGRAM / NUMBERS",
            "text": "Records commands or numbers.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-z4-eth-manual",
            "locator": "pp. 1–2",
            "control": false
          },
          {
            "id": "output",
            "label": "Lamps and printer",
            "subtitle": "READABLE RESULTS",
            "text": "Display and print results.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-z4-eth-manual",
            "locator": "p. 3 §6",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "at0",
            "to": "control",
            "type": "control",
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 diagram",
            "label": ""
          },
          {
            "from": "control",
            "to": "arithmetic",
            "type": "control",
            "source": "hist-z4-eth-manual",
            "locator": "p. 2 §4",
            "label": ""
          },
          {
            "from": "memory",
            "to": "operands",
            "type": "data",
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 diagram",
            "label": ""
          },
          {
            "from": "operands",
            "to": "arithmetic",
            "type": "data",
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 diagram",
            "label": ""
          },
          {
            "from": "arithmetic",
            "to": "operands",
            "type": "data",
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 diagram, OR I",
            "label": ""
          },
          {
            "from": "operands",
            "to": "memory",
            "type": "data",
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 diagram, OR I",
            "label": ""
          },
          {
            "from": "keyboard",
            "to": "arithmetic",
            "type": "data",
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 diagram",
            "label": ""
          },
          {
            "from": "at1",
            "to": "arithmetic",
            "type": "data",
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 diagram",
            "label": ""
          },
          {
            "from": "at1",
            "to": "control",
            "type": "control",
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 diagram",
            "label": ""
          },
          {
            "from": "arithmetic",
            "to": "punch",
            "type": "data",
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 diagram",
            "label": ""
          },
          {
            "from": "arithmetic",
            "to": "output",
            "type": "data",
            "source": "hist-z4-eth-manual",
            "locator": "p. 1 diagram",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Zuse Z4"
    },
    {
      "id": "queue-004",
      "name": "Harvard Mark I / IBM ASCC",
      "organization": "IBM / Harvard Computation Laboratory",
      "year": 1946,
      "yearLabel": "1946 manual organization",
      "kind": "Electromechanical system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "configured",
        "accumulator",
        "mechanical"
      ],
      "substrates": [
        "relay",
        "mechanical"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-mark1-function",
        "hist-mark1-manual"
      ],
      "summary": "Sequence-tape control directs mechanical storage counters, interpolators, and card or typewriter interfaces.",
      "config": "Mark I as documented by Harvard’s functional explanation and 1946 manual section index. Later modifications are not generalized.",
      "gaps": [
        "Complete manual scan was not retrieved; detailed multiplier wiring remains outside this diagram.",
        "The motor/shaft relationship denotes synchronization, not numerical data flow."
      ],
      "originalName": "Harvard Mark I",
      "insight": "What can a sequence tape control without placing instructions in numerical storage?",
      "fields": {
        "state": {
          "value": "Decimal mechanical counters",
          "source": "hist-mark1-function",
          "locator": "Storage counters"
        },
        "compute": {
          "value": "Adding-machine storage counters",
          "source": "hist-mark1-function",
          "locator": "Storage counters"
        },
        "memory": {
          "value": "72 original storage-counter units",
          "source": "hist-mark1-function",
          "locator": "Storage counters"
        },
        "control": {
          "value": "Sequence tape and interpolators",
          "source": "hist-mark1-function",
          "locator": "Sequence control and interpolators"
        },
        "io": {
          "value": "Constant dials, cards, punches and typewriters",
          "source": "hist-mark1-function",
          "locator": "Constant switches; card equipment"
        },
        "software": {
          "value": "Tape instructions read one line at a time",
          "source": "hist-mark1-function",
          "locator": "Sequence control"
        },
        "workload": {
          "value": "Military mathematical tables",
          "source": "hist-mark1-function",
          "locator": "How did it work?"
        }
      },
      "diagram": {
        "title": "Sequence control over electromechanical resources",
        "scope": "Institutional functional components; mechanical synchronization is shown as association.",
        "nodes": [
          {
            "id": "seq",
            "label": "Sequence tape",
            "subtitle": "ORDER STREAM",
            "text": "Encodes the instruction sequence.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-mark1-function",
            "locator": "Sequence control",
            "control": false
          },
          {
            "id": "control",
            "label": "Sequence control",
            "subtitle": "ONE LINE PER STEP",
            "text": "Reads and executes orders.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-mark1-function",
            "locator": "Sequence control",
            "control": true
          },
          {
            "id": "interp",
            "label": "Interpolators",
            "subtitle": "VALUES / FUNCTIONS",
            "text": "Read encoded values and functions.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-mark1-function",
            "locator": "Interpolators",
            "control": false
          },
          {
            "id": "constant",
            "label": "Constant dials",
            "subtitle": "PRESET NUMBERS",
            "text": "Hold values for a problem run.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-mark1-function",
            "locator": "Constant switches",
            "control": false
          },
          {
            "id": "counters",
            "label": "Storage counters",
            "subtitle": "72 ORIGINAL UNITS",
            "text": "Store and operate on numbers.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-mark1-function",
            "locator": "Storage counters",
            "control": false
          },
          {
            "id": "cards",
            "label": "Card equipment",
            "subtitle": "INPUT / OUTPUT",
            "text": "Reads and punches problem data.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-mark1-function",
            "locator": "Card feeds, card punch",
            "control": false
          },
          {
            "id": "shaft",
            "label": "Motor and drive shaft",
            "subtitle": "SYNCHRONIZATION",
            "text": "Keeps mechanical components in step.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-mark1-function",
            "locator": "Drive shaft",
            "control": false
          },
          {
            "id": "type",
            "label": "Typewriters",
            "subtitle": "READABLE OUTPUT",
            "text": "Print numerical output.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-mark1-function",
            "locator": "Card feeds, card punch",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "seq",
            "to": "control",
            "type": "control",
            "source": "hist-mark1-function",
            "locator": "Sequence control",
            "label": ""
          },
          {
            "from": "control",
            "to": "counters",
            "type": "control",
            "source": "hist-mark1-function",
            "locator": "Storage counters",
            "label": ""
          },
          {
            "from": "control",
            "to": "interp",
            "type": "control",
            "source": "hist-mark1-function",
            "locator": "Sequence control and interpolators",
            "label": ""
          },
          {
            "from": "constant",
            "to": "counters",
            "type": "data",
            "source": "hist-mark1-function",
            "locator": "Constant switches",
            "label": ""
          },
          {
            "from": "interp",
            "to": "counters",
            "type": "data",
            "source": "hist-mark1-function",
            "locator": "Interpolators",
            "label": ""
          },
          {
            "from": "cards",
            "to": "counters",
            "type": "data",
            "source": "hist-mark1-function",
            "locator": "Card feeds",
            "label": ""
          },
          {
            "from": "counters",
            "to": "cards",
            "type": "data",
            "source": "hist-mark1-function",
            "locator": "Card punch",
            "label": ""
          },
          {
            "from": "counters",
            "to": "type",
            "type": "data",
            "source": "hist-mark1-function",
            "locator": "Typewriters",
            "label": ""
          },
          {
            "from": "shaft",
            "to": "counters",
            "type": "association",
            "source": "hist-mark1-function",
            "locator": "Drive shaft",
            "label": ""
          },
          {
            "from": "shaft",
            "to": "control",
            "type": "association",
            "source": "hist-mark1-function",
            "locator": "Drive shaft",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Harvard Mark I"
    },
    {
      "id": "queue-005",
      "name": "Atanasoff–Berry Computer",
      "organization": "Iowa State College / Atanasoff and Berry",
      "year": 1942,
      "yearLabel": "Original design; reconstruction-assisted account",
      "kind": "Special-purpose electronic machine",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "configured"
      ],
      "substrates": [
        "vacuum-tube",
        "mechanical"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-abc-manual",
        "hist-abc-reconstruction"
      ],
      "summary": "Parallel bit-serial add/subtract units operate on regenerated capacitor-drum state for linear-equation elimination.",
      "config": "Original ABC architecture, interpreted using Berry’s manual and the reconstruction team’s account. Replica frame and wiring changes are not original features.",
      "gaps": [
        "Reliability of original scratch-card operation must not be inferred from the later working replica.",
        "No stored-program instruction memory is assigned."
      ],
      "insight": "How can many numbers be processed in parallel while each number is processed one bit at a time?",
      "fields": {
        "state": {
          "value": "Binary, bit-serial numbers",
          "source": "hist-abc-reconstruction",
          "locator": "§2 Block Diagram"
        },
        "compute": {
          "value": "30 parallel add/subtract modules",
          "source": "hist-abc-reconstruction",
          "locator": "§2; Figure 1"
        },
        "memory": {
          "value": "Two 30 × 50-bit dynamic stores",
          "source": "hist-abc-reconstruction",
          "locator": "Figure 1"
        },
        "control": {
          "value": "Operator switches and buttons",
          "source": "hist-abc-reconstruction",
          "locator": "§7 Instruction Set"
        },
        "io": {
          "value": "Decimal conversion and binary scratch cards",
          "source": "hist-abc-reconstruction",
          "locator": "§2; §6"
        },
        "software": {
          "value": "Operator-invoked elimination operations",
          "source": "hist-abc-reconstruction",
          "locator": "§7"
        },
        "workload": {
          "value": "Systems of linear equations",
          "source": "hist-abc-reconstruction",
          "locator": "§1 Motivation"
        }
      },
      "diagram": {
        "title": "Parallel arithmetic between dynamic stores",
        "scope": "Functional paths from the reconstruction paper Figure 1 and Berry’s manuscript; no replica-only physical dimensions.",
        "nodes": [
          {
            "id": "decimal",
            "label": "Decimal input",
            "subtitle": "EXTERNAL DATA",
            "text": "Introduces coefficients.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-abc-reconstruction",
            "locator": "Figure 1",
            "control": false
          },
          {
            "id": "convert",
            "label": "Conversion table",
            "subtitle": "BASE CONVERSION",
            "text": "Works with arithmetic modules.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-abc-reconstruction",
            "locator": "Figure 1",
            "control": false
          },
          {
            "id": "operator",
            "label": "Operator controls",
            "subtitle": "PROCEDURE",
            "text": "Select operations and coefficients.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-abc-reconstruction",
            "locator": "§7",
            "control": true
          },
          {
            "id": "mem1",
            "label": "Dynamic memory 1",
            "subtitle": "30 × 50 BITS",
            "text": "Retains one coefficient vector.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-abc-reconstruction",
            "locator": "Figure 1",
            "control": false
          },
          {
            "id": "alu",
            "label": "Add/subtract modules",
            "subtitle": "30 PARALLEL LANES",
            "text": "Operate one bit per number at a time.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-abc-reconstruction",
            "locator": "§2",
            "control": false
          },
          {
            "id": "mem2",
            "label": "Dynamic memory 2",
            "subtitle": "30 × 50 BITS",
            "text": "Retains the second vector.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-abc-reconstruction",
            "locator": "Figure 1",
            "control": false
          },
          {
            "id": "scratch",
            "label": "Binary scratch cards",
            "subtitle": "INTERMEDIATE STATE",
            "text": "Record and reload a vector.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-abc-reconstruction",
            "locator": "§6",
            "control": false
          },
          {
            "id": "carry",
            "label": "Carry/borrow state",
            "subtitle": "CAPACITOR COUNTERS",
            "text": "Retains carry between bit times.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-abc-manual",
            "locator": "Counters; computer circuit",
            "control": false
          },
          {
            "id": "decimalout",
            "label": "Decimal output",
            "subtitle": "READOUT",
            "text": "Shows converted results.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-abc-reconstruction",
            "locator": "Figure 1; §7",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "decimal",
            "to": "mem1",
            "type": "data",
            "source": "hist-abc-reconstruction",
            "locator": "§7 decimal read",
            "label": ""
          },
          {
            "from": "convert",
            "to": "alu",
            "type": "data",
            "source": "hist-abc-reconstruction",
            "locator": "§2 base conversion",
            "label": ""
          },
          {
            "from": "mem1",
            "to": "alu",
            "type": "data",
            "source": "hist-abc-reconstruction",
            "locator": "Figure 1",
            "label": ""
          },
          {
            "from": "mem2",
            "to": "alu",
            "type": "data",
            "source": "hist-abc-reconstruction",
            "locator": "Figure 1",
            "label": ""
          },
          {
            "from": "alu",
            "to": "mem1",
            "type": "data",
            "source": "hist-abc-manual",
            "locator": "Computer circuit",
            "label": ""
          },
          {
            "from": "alu",
            "to": "carry",
            "type": "data",
            "source": "hist-abc-manual",
            "locator": "Computer circuit",
            "label": ""
          },
          {
            "from": "carry",
            "to": "alu",
            "type": "data",
            "source": "hist-abc-manual",
            "locator": "Computer circuit",
            "label": ""
          },
          {
            "from": "scratch",
            "to": "mem1",
            "type": "data",
            "source": "hist-abc-reconstruction",
            "locator": "§7 binary read",
            "label": ""
          },
          {
            "from": "mem1",
            "to": "scratch",
            "type": "data",
            "source": "hist-abc-reconstruction",
            "locator": "§6",
            "label": ""
          },
          {
            "from": "alu",
            "to": "decimalout",
            "type": "data",
            "source": "hist-abc-reconstruction",
            "locator": "§7 output",
            "label": ""
          },
          {
            "from": "operator",
            "to": "alu",
            "type": "control",
            "source": "hist-abc-reconstruction",
            "locator": "§7",
            "label": ""
          },
          {
            "from": "operator",
            "to": "mem2",
            "type": "control",
            "source": "hist-abc-reconstruction",
            "locator": "§7",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Atanasoff–Berry Computer"
    },
    {
      "id": "queue-006",
      "name": "Colossus Mark II organization",
      "organization": "British Post Office / GC&CS Newmanry",
      "year": 1945,
      "yearLabel": "1945 operational report",
      "kind": "Special-purpose electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "configured"
      ],
      "substrates": [
        "vacuum-tube",
        "relay"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-tunny-colossus",
        "hist-tunny-colossus-intro"
      ],
      "summary": "Tape-timed generated streams feed configurable conditions and parallel counters, with buffered score printing.",
      "config": "Chapter 53 operational organization of the later Colossi; machine-specific differences such as Colossus 10 SIP remain separate.",
      "gaps": [
        "Later machines varied; features explicitly limited to one Colossus are not generalized.",
        "The diagram depicts statistical data/control roles, not a full valve circuit or a Lorenz machine."
      ],
      "originalName": "Colossus Mark II",
      "insight": "How can repeated statistical tests be accelerated without a stored instruction program?",
      "fields": {
        "state": {
          "value": "Teleprinter streams and wheel-pattern states",
          "source": "hist-tunny-colossus",
          "locator": "§53A–C"
        },
        "compute": {
          "value": "Five condition counters",
          "source": "hist-tunny-colossus",
          "locator": "§53F"
        },
        "memory": {
          "value": "Limited differencing memory and score relays",
          "source": "hist-tunny-colossus",
          "locator": "§53E; §53G(c)"
        },
        "control": {
          "value": "Tape timing, stepping and configured panels",
          "source": "hist-tunny-colossus",
          "locator": "§53B; §53D; §53J–K"
        },
        "io": {
          "value": "Looped five-impulse tape; display and printer",
          "source": "hist-tunny-colossus",
          "locator": "§53B; §53G"
        },
        "software": {
          "value": "Switch/plug configurations for runs",
          "source": "hist-tunny-colossus",
          "locator": "§53J–L"
        },
        "workload": {
          "value": "Counts used in Tunny cryptanalysis",
          "source": "hist-tunny-colossus",
          "locator": "§53A"
        }
      },
      "diagram": {
        "title": "Tape-driven statistical testing and score recording",
        "scope": "Selected Mark II-era operational roles from Chapter 53. The tape is also the timing source; score relays decouple printing.",
        "nodes": [
          {
            "id": "tape",
            "label": "Z tape and reader",
            "subtitle": "5-IMPULSE LOOP",
            "text": "Supplies Z and sprocket timing.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-tunny-colossus-intro",
            "locator": "§53B",
            "control": false
          },
          {
            "id": "wheels",
            "label": "X / Mu / PSI states",
            "subtitle": "GENERATED STREAMS",
            "text": "Represent configured wheel patterns.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-tunny-colossus-intro",
            "locator": "§53A",
            "control": false
          },
          {
            "id": "stepping",
            "label": "Stepping controls",
            "subtitle": "SETTINGS",
            "text": "Vary wheel-relative positions.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-tunny-colossus",
            "locator": "§53D",
            "control": true
          },
          {
            "id": "delta",
            "label": "Differencing memory",
            "subtitle": "ADJACENT SYMBOLS",
            "text": "Provides selected delta streams.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-tunny-colossus",
            "locator": "§53E",
            "control": false
          },
          {
            "id": "q",
            "label": "Q / plug panels",
            "subtitle": "LOGICAL CONDITIONS",
            "text": "Select streams and impose conditions.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-tunny-colossus",
            "locator": "§53J–K",
            "control": false
          },
          {
            "id": "counters",
            "label": "Five counters",
            "subtitle": "STATISTICAL COUNTS",
            "text": "Count qualifying positions.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-tunny-colossus",
            "locator": "§53F",
            "control": false
          },
          {
            "id": "limit",
            "label": "Set-total controls",
            "subtitle": "SCORE FILTER",
            "text": "Choose which scores are retained.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-tunny-colossus",
            "locator": "§53G(a)",
            "control": true
          },
          {
            "id": "score",
            "label": "Score relays",
            "subtitle": "BUFFERED STATE",
            "text": "Retain score and settings.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-tunny-colossus",
            "locator": "§53G(c)",
            "control": false
          },
          {
            "id": "print",
            "label": "Display and printer",
            "subtitle": "RECORDED SCORES",
            "text": "Expose retained test results.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-tunny-colossus",
            "locator": "§53G",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "tape",
            "to": "wheels",
            "type": "control",
            "source": "hist-tunny-colossus-intro",
            "locator": "§53B sprocket timing",
            "label": ""
          },
          {
            "from": "stepping",
            "to": "wheels",
            "type": "control",
            "source": "hist-tunny-colossus",
            "locator": "§53D",
            "label": ""
          },
          {
            "from": "tape",
            "to": "delta",
            "type": "data",
            "source": "hist-tunny-colossus",
            "locator": "§53E",
            "label": ""
          },
          {
            "from": "wheels",
            "to": "delta",
            "type": "data",
            "source": "hist-tunny-colossus",
            "locator": "§53E",
            "label": ""
          },
          {
            "from": "delta",
            "to": "q",
            "type": "data",
            "source": "hist-tunny-colossus",
            "locator": "§53J(a)",
            "label": ""
          },
          {
            "from": "tape",
            "to": "q",
            "type": "data",
            "source": "hist-tunny-colossus-intro",
            "locator": "§53A",
            "label": ""
          },
          {
            "from": "wheels",
            "to": "q",
            "type": "data",
            "source": "hist-tunny-colossus-intro",
            "locator": "§53A",
            "label": ""
          },
          {
            "from": "q",
            "to": "counters",
            "type": "data",
            "source": "hist-tunny-colossus",
            "locator": "§53F(b)",
            "label": ""
          },
          {
            "from": "counters",
            "to": "score",
            "type": "data",
            "source": "hist-tunny-colossus",
            "locator": "§53G(c)",
            "label": ""
          },
          {
            "from": "limit",
            "to": "score",
            "type": "control",
            "source": "hist-tunny-colossus",
            "locator": "§53G(a)",
            "label": ""
          },
          {
            "from": "score",
            "to": "print",
            "type": "data",
            "source": "hist-tunny-colossus",
            "locator": "§53G(c)",
            "label": ""
          },
          {
            "from": "score",
            "to": "stepping",
            "type": "control",
            "source": "hist-tunny-colossus",
            "locator": "§53G(c)",
            "label": "printing backpressure"
          }
        ]
      },
      "originalCandidate": "Colossus Mark II"
    },
    {
      "id": "queue-007",
      "name": "Manchester Baby / SSEM",
      "organization": "University of Manchester",
      "year": 1948,
      "yearLabel": "June 1948 machine; 1951 designer paper",
      "kind": "Experimental electronic computer",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator"
      ],
      "substrates": [
        "vacuum-tube"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-baby-iee",
        "hist-baby-manchester"
      ],
      "summary": "A small CRT-store computer that tests memory through stored instructions and a serial subtraction datapath.",
      "config": "Original SSEM described by Williams, Kilburn and Tootill. Later Manchester Mark 1 facilities are excluded.",
      "gaps": [
        "The paper discusses possible expansions; those are not installed SSEM capabilities.",
        "Physical CRT feedback details and timing waveforms are linked, not redrawn as a complete circuit."
      ],
      "originalName": "Manchester Baby",
      "insight": "How does regeneration coexist with instruction fetch and arithmetic access?",
      "fields": {
        "state": {
          "value": "Serial 32-bit binary pulse trains",
          "source": "hist-baby-iee",
          "locator": "§3.1"
        },
        "compute": {
          "value": "Accumulator and subtractor",
          "source": "hist-baby-iee",
          "locator": "§3.2"
        },
        "memory": {
          "value": "32 lines of 32 bits in the main store",
          "source": "hist-baby-iee",
          "locator": "§3.1"
        },
        "control": {
          "value": "CI, PI and staticisor; four-beat rhythm",
          "source": "hist-baby-iee",
          "locator": "§3.3–3.5"
        },
        "io": {
          "value": "Manual typewriter keys and CRT observation",
          "source": "hist-baby-iee",
          "locator": "§4.3"
        },
        "software": {
          "value": "Instructions and numbers share main storage",
          "source": "hist-baby-iee",
          "locator": "§3.1"
        },
        "workload": {
          "value": "Memory testing; highest-factor example",
          "source": "hist-baby-iee",
          "locator": "§1; §2.2"
        }
      },
      "diagram": {
        "title": "Store, transfer gates, and control rhythm",
        "scope": "Functional transfers in Figures 5, 6, 8 and 9; distinct data paths and instruction-controlled gating.",
        "nodes": [
          {
            "id": "keys",
            "label": "Manual keys",
            "subtitle": "BITWISE INPUT",
            "text": "Write or erase selected digits.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-baby-iee",
            "locator": "§4.3",
            "control": false
          },
          {
            "id": "ci",
            "label": "CI / PI storage",
            "subtitle": "CONTROL TUBE",
            "text": "Hold instruction address and instruction.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-baby-iee",
            "locator": "§3.3",
            "control": false
          },
          {
            "id": "static",
            "label": "Staticisor",
            "subtitle": "DECODED CONTROL",
            "text": "Selects line and operation.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-baby-iee",
            "locator": "§3.4",
            "control": true
          },
          {
            "id": "inward",
            "label": "Inward-transfer gate",
            "subtitle": "WRITE PATH",
            "text": "Accepts accumulator or key pulses.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-baby-iee",
            "locator": "§4.1; §7.7",
            "control": false
          },
          {
            "id": "store",
            "label": "Main store S",
            "subtitle": "32 × 32 BITS",
            "text": "Regenerates shared instructions/data.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-baby-iee",
            "locator": "§3.1",
            "control": false
          },
          {
            "id": "outward",
            "label": "Outward-transfer gate",
            "subtitle": "READ PATH",
            "text": "Passes selected store output.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-baby-iee",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "acc",
            "label": "Accumulator A",
            "subtitle": "ONE 32-BIT LINE",
            "text": "Retains arithmetic state.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-baby-iee",
            "locator": "§3.2",
            "control": false
          },
          {
            "id": "sub",
            "label": "Subtractor",
            "subtitle": "SERIAL ARITHMETIC",
            "text": "Forms accumulator updates.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-baby-iee",
            "locator": "§3.2",
            "control": false
          },
          {
            "id": "rhythm",
            "label": "Rhythm / pre-pulse",
            "subtitle": "SCAN AND ACTION",
            "text": "Sequences control and execution.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-baby-iee",
            "locator": "§3.5",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "keys",
            "to": "inward",
            "type": "data",
            "source": "hist-baby-iee",
            "locator": "§4.3",
            "label": ""
          },
          {
            "from": "acc",
            "to": "inward",
            "type": "data",
            "source": "hist-baby-iee",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "inward",
            "to": "store",
            "type": "data",
            "source": "hist-baby-iee",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "store",
            "to": "outward",
            "type": "data",
            "source": "hist-baby-iee",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "outward",
            "to": "ci",
            "type": "data",
            "source": "hist-baby-iee",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "outward",
            "to": "sub",
            "type": "data",
            "source": "hist-baby-iee",
            "locator": "§3.2",
            "label": ""
          },
          {
            "from": "acc",
            "to": "sub",
            "type": "data",
            "source": "hist-baby-iee",
            "locator": "§3.2",
            "label": ""
          },
          {
            "from": "sub",
            "to": "acc",
            "type": "data",
            "source": "hist-baby-iee",
            "locator": "§3.2",
            "label": ""
          },
          {
            "from": "ci",
            "to": "static",
            "type": "control",
            "source": "hist-baby-iee",
            "locator": "§3.3–3.4",
            "label": ""
          },
          {
            "from": "static",
            "to": "store",
            "type": "control",
            "source": "hist-baby-iee",
            "locator": "§3.4",
            "label": ""
          },
          {
            "from": "rhythm",
            "to": "static",
            "type": "control",
            "source": "hist-baby-iee",
            "locator": "§3.5",
            "label": ""
          },
          {
            "from": "rhythm",
            "to": "outward",
            "type": "control",
            "source": "hist-baby-iee",
            "locator": "§4.1",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Manchester Baby"
    },
    {
      "id": "queue-008",
      "name": "Manchester Mark 1 — final 1949 version",
      "organization": "University of Manchester",
      "year": 1949,
      "yearLabel": "Autumn 1949 configuration",
      "kind": "Experimental electronic computer",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator"
      ],
      "substrates": [
        "vacuum-tube",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-manchester-series",
        "hist-manchester-mark1"
      ],
      "summary": "CRT working storage, synchronized drum backing storage, address-modification lines, and programmed teleprinter I/O.",
      "config": "Final 1949 Manchester Mark 1. The earlier intermediary version required manual drum transfers and had no programmed tape I/O.",
      "gaps": [
        "The April intermediary and autumn final machine are not merged.",
        "The schematic aggregates transfer gates and does not claim a physical floorplan."
      ],
      "originalName": "Manchester Mark 1",
      "insight": "How can address modification and backing-store transfers enter the normal instruction rhythm?",
      "fields": {
        "state": {
          "value": "40-bit numbers; two 20-bit instructions per line",
          "source": "hist-manchester-mark1",
          "locator": "Intermediary specification"
        },
        "compute": {
          "value": "Serial arithmetic and hardware multiply; 80-bit accumulator",
          "source": "hist-manchester-mark1",
          "locator": "Intermediary specification"
        },
        "memory": {
          "value": "CRT pages plus magnetic drum backing store",
          "source": "hist-manchester-mark1",
          "locator": "Final specification"
        },
        "control": {
          "value": "Control tube and B-line address modification",
          "source": "hist-manchester-mark1",
          "locator": "Auxiliary tubes; B-lines"
        },
        "io": {
          "value": "Programmed five-hole teleprinter tape",
          "source": "hist-manchester-mark1",
          "locator": "Final-version background"
        },
        "software": {
          "value": "Single-address orders with modifiers",
          "source": "hist-manchester-mark1",
          "locator": "Intermediary specification"
        },
        "workload": {
          "value": "Riemann-function and optics calculations",
          "source": "hist-manchester-mark1",
          "locator": "Background"
        }
      },
      "diagram": {
        "title": "Address modification and automatic drum transfers",
        "scope": "Final-1949 functional roles from the designer conference paper. Auxiliary staticisor governs long transfers.",
        "nodes": [
          {
            "id": "drum",
            "label": "Magnetic drum",
            "subtitle": "BACKING STORE",
            "text": "Transfers selected tracks/pages.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-manchester-series",
            "locator": "A Magnetic Store",
            "control": false
          },
          {
            "id": "crt",
            "label": "CRT main store S",
            "subtitle": "WORKING PAGES",
            "text": "Holds instructions and numbers.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-manchester-series",
            "locator": "A Large-scale Machine",
            "control": false
          },
          {
            "id": "control",
            "label": "Control / PI",
            "subtitle": "INSTRUCTION RHYTHM",
            "text": "Presents instructions for decoding.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-manchester-series",
            "locator": "An Improved Machine",
            "control": true
          },
          {
            "id": "aux",
            "label": "Auxiliary staticisor",
            "subtitle": "TRANSFER KEY WORD",
            "text": "Selects track, CRT, direction.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-manchester-series",
            "locator": "A Large-scale Machine",
            "control": true
          },
          {
            "id": "acc",
            "label": "Accumulator A",
            "subtitle": "80-BIT RESULT",
            "text": "Retains arithmetic and I/O digits.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-manchester-series",
            "locator": "An Improved Machine",
            "control": false
          },
          {
            "id": "b",
            "label": "B tube",
            "subtitle": "ADDRESS MODIFIERS",
            "text": "Adds selected B-line to PI.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-manchester-series",
            "locator": "An Improved Machine",
            "control": false
          },
          {
            "id": "mult",
            "label": "M / D / R lines",
            "subtitle": "HARDWARE MULTIPLY",
            "text": "Retain multiplicand and multiplier.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-manchester-series",
            "locator": "An Improved Machine",
            "control": false
          },
          {
            "id": "arith",
            "label": "Arithmetic circuits",
            "subtitle": "ADD / SUBTRACT / LOGIC",
            "text": "Update the accumulator.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-manchester-series",
            "locator": "An Improved Machine",
            "control": false
          },
          {
            "id": "tape",
            "label": "Teleprinter I/O",
            "subtitle": "5-DIGIT TRANSFERS",
            "text": "Programmed transfer through A.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-manchester-series",
            "locator": "A Large-scale Machine",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "drum",
            "to": "crt",
            "type": "data",
            "source": "hist-manchester-series",
            "locator": "A Magnetic Store",
            "label": ""
          },
          {
            "from": "crt",
            "to": "drum",
            "type": "data",
            "source": "hist-manchester-series",
            "locator": "A Magnetic Store",
            "label": ""
          },
          {
            "from": "crt",
            "to": "control",
            "type": "data",
            "source": "hist-manchester-series",
            "locator": "An Improved Machine",
            "label": ""
          },
          {
            "from": "b",
            "to": "control",
            "type": "data",
            "source": "hist-manchester-series",
            "locator": "B tube modification",
            "label": ""
          },
          {
            "from": "crt",
            "to": "b",
            "type": "data",
            "source": "hist-manchester-series",
            "locator": "An Improved Machine",
            "label": ""
          },
          {
            "from": "control",
            "to": "aux",
            "type": "control",
            "source": "hist-manchester-series",
            "locator": "A Large-scale Machine",
            "label": ""
          },
          {
            "from": "aux",
            "to": "drum",
            "type": "control",
            "source": "hist-manchester-series",
            "locator": "Transfer key word",
            "label": ""
          },
          {
            "from": "crt",
            "to": "arith",
            "type": "data",
            "source": "hist-manchester-series",
            "locator": "An Improved Machine",
            "label": ""
          },
          {
            "from": "arith",
            "to": "acc",
            "type": "data",
            "source": "hist-manchester-series",
            "locator": "An Improved Machine",
            "label": ""
          },
          {
            "from": "mult",
            "to": "acc",
            "type": "data",
            "source": "hist-manchester-series",
            "locator": "An Improved Machine",
            "label": ""
          },
          {
            "from": "acc",
            "to": "tape",
            "type": "data",
            "source": "hist-manchester-series",
            "locator": "Programmed I/O",
            "label": ""
          },
          {
            "from": "tape",
            "to": "acc",
            "type": "data",
            "source": "hist-manchester-series",
            "locator": "Programmed I/O",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Manchester Mark 1"
    },
    {
      "id": "queue-009",
      "name": "EDSAC — full-store, Initial Orders 2 organization",
      "organization": "University of Cambridge Mathematical Laboratory",
      "year": 1949,
      "yearLabel": "Initial Orders 2 introduced September 1949",
      "kind": "Research electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator"
      ],
      "substrates": [
        "vacuum-tube"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-edsac-engineering",
        "hist-edsac-log"
      ],
      "summary": "Serial arithmetic uses unequal-length delay-line registers; Initial Orders translate symbolic paper tape into stored instructions.",
      "config": "Full 1,024-short-word organization documented by the simulator engineer; not the partly commissioned May 6 installation.",
      "gaps": [
        "Architecture evidence is reconstruction/simulator engineering documentation; the original 1951 textbook was not retrieved.",
        "Commissioning log confirms the first run used only four tanks."
      ],
      "originalName": "EDSAC",
      "insight": "Why do 18 physical bits provide only 17 useful short-word bits?",
      "fields": {
        "state": {
          "value": "17-bit short / 35-bit long numbers",
          "source": "hist-edsac-engineering",
          "locator": "pp. 14–15"
        },
        "compute": {
          "value": "71-bit accumulator; two 35-bit multiply registers",
          "source": "hist-edsac-engineering",
          "locator": "p. 15"
        },
        "memory": {
          "value": "32 mercury tanks; 1,024 physical 18-bit words",
          "source": "hist-edsac-engineering",
          "locator": "pp. 5–6; Figure 4"
        },
        "control": {
          "value": "Sequence Control and Order tanks",
          "source": "hist-edsac-engineering",
          "locator": "pp. 13–14"
        },
        "io": {
          "value": "Five-track tape reader and teleprinter",
          "source": "hist-edsac-engineering",
          "locator": "p. 5"
        },
        "software": {
          "value": "Initial Orders 2 and reusable subroutines",
          "source": "hist-edsac-engineering",
          "locator": "p. 13; Chapter 3"
        },
        "workload": {
          "value": "Numerical programs including squares and primes",
          "source": "hist-edsac-engineering",
          "locator": "pp. 8–11"
        }
      },
      "diagram": {
        "title": "Delay-line registers and symbolic program loading",
        "scope": "Architectural roles and instruction effects, not a recreation of the modern simulator UI.",
        "nodes": [
          {
            "id": "tape",
            "label": "Tape reader",
            "subtitle": "5-TRACK INPUT",
            "text": "Provides coded program characters.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-edsac-engineering",
            "locator": "p. 5",
            "control": false
          },
          {
            "id": "initial",
            "label": "Initial Orders 2",
            "subtitle": "LOADING ROUTINE",
            "text": "Translates symbolic tape into orders.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-edsac-engineering",
            "locator": "p. 13; Chapter 3",
            "control": false
          },
          {
            "id": "seq",
            "label": "Sequence Control",
            "subtitle": "ADDRESS STATE",
            "text": "Holds the current instruction address.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-edsac-engineering",
            "locator": "p. 14",
            "control": true
          },
          {
            "id": "store",
            "label": "Mercury store",
            "subtitle": "1,024 SHORT WORDS",
            "text": "Retains both orders and numbers.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-edsac-engineering",
            "locator": "Figure 4",
            "control": false
          },
          {
            "id": "order",
            "label": "Order tank",
            "subtitle": "INSTRUCTION STATE",
            "text": "Retains the current operation.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-edsac-engineering",
            "locator": "p. 14",
            "control": true
          },
          {
            "id": "multiply",
            "label": "Multiplier / multiplicand",
            "subtitle": "35 BITS EACH",
            "text": "Retain multiplication operands.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-edsac-engineering",
            "locator": "p. 15",
            "control": false
          },
          {
            "id": "acc",
            "label": "Accumulator",
            "subtitle": "71 BITS",
            "text": "Accumulates long products and sums.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-edsac-engineering",
            "locator": "p. 15",
            "control": false
          },
          {
            "id": "transfer",
            "label": "T / U order effects",
            "subtitle": "STORE RESULT",
            "text": "Write accumulator portions into store.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-edsac-engineering",
            "locator": "Appendix Table 1",
            "control": false
          },
          {
            "id": "print",
            "label": "Teleprinter",
            "subtitle": "OUTPUT CHARACTERS",
            "text": "Prints code selected by output orders.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-edsac-engineering",
            "locator": "p. 5; Appendix Table 1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "tape",
            "to": "initial",
            "type": "data",
            "source": "hist-edsac-engineering",
            "locator": "Chapter 3",
            "label": ""
          },
          {
            "from": "initial",
            "to": "store",
            "type": "data",
            "source": "hist-edsac-engineering",
            "locator": "Chapter 3",
            "label": ""
          },
          {
            "from": "seq",
            "to": "store",
            "type": "control",
            "source": "hist-edsac-engineering",
            "locator": "Figure 4; p. 14",
            "label": ""
          },
          {
            "from": "store",
            "to": "order",
            "type": "data",
            "source": "hist-edsac-engineering",
            "locator": "Figure 4",
            "label": ""
          },
          {
            "from": "order",
            "to": "seq",
            "type": "control",
            "source": "hist-edsac-engineering",
            "locator": "Appendix Table 1 E/G",
            "label": ""
          },
          {
            "from": "order",
            "to": "multiply",
            "type": "control",
            "source": "hist-edsac-engineering",
            "locator": "Appendix Table 1 H/V/N",
            "label": ""
          },
          {
            "from": "store",
            "to": "multiply",
            "type": "data",
            "source": "hist-edsac-engineering",
            "locator": "Appendix Table 1 H/V/N",
            "label": ""
          },
          {
            "from": "multiply",
            "to": "acc",
            "type": "data",
            "source": "hist-edsac-engineering",
            "locator": "Appendix Table 1 V/N",
            "label": ""
          },
          {
            "from": "store",
            "to": "acc",
            "type": "data",
            "source": "hist-edsac-engineering",
            "locator": "Appendix Table 1 A/S",
            "label": ""
          },
          {
            "from": "acc",
            "to": "transfer",
            "type": "data",
            "source": "hist-edsac-engineering",
            "locator": "Appendix Table 1 T/U",
            "label": ""
          },
          {
            "from": "transfer",
            "to": "store",
            "type": "data",
            "source": "hist-edsac-engineering",
            "locator": "Appendix Table 1 T/U",
            "label": ""
          },
          {
            "from": "store",
            "to": "print",
            "type": "data",
            "source": "hist-edsac-engineering",
            "locator": "Appendix Table 1 O",
            "label": ""
          }
        ]
      },
      "originalCandidate": "EDSAC"
    },
    {
      "id": "queue-010",
      "name": "EDVAC — BRL 1961 configuration",
      "organization": "Moore School / Ballistic Research Laboratories",
      "year": 1961,
      "yearLabel": "March 1961 operational survey",
      "kind": "Research electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified"
      ],
      "substrates": [
        "vacuum-tube",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-edvac-brl1961"
      ],
      "summary": "Four-address words identify two operands, a result and the next instruction in an upgraded serial delay-line machine.",
      "config": "BRL survey configuration with installed floating-point equipment and 4,608-word drum; planned second drum excluded.",
      "gaps": [
        "Survey OCR has typographic errors; physical wiring is not reconstructed.",
        "Magnetic tape storage was under investigation; its proposed capacity is not installed hardware."
      ],
      "originalName": "EDVAC",
      "insight": "How does an explicit next-instruction address change sequencing?",
      "fields": {
        "state": {
          "value": "44-bit words; four 10-bit addresses",
          "source": "hist-edvac-brl1961",
          "locator": "pp. 236–237"
        },
        "compute": {
          "value": "Sequential serial fixed/floating arithmetic",
          "source": "hist-edvac-brl1961",
          "locator": "p. 237"
        },
        "memory": {
          "value": "1,024-word mercury store; 4,608-word drum",
          "source": "hist-edvac-brl1961",
          "locator": "p. 237"
        },
        "control": {
          "value": "Four-address instructions; 4-bit operation",
          "source": "hist-edvac-brl1961",
          "locator": "pp. 236–237"
        },
        "io": {
          "value": "Photoelectric tape and IBM cards",
          "source": "hist-edvac-brl1961",
          "locator": "p. 238"
        },
        "software": {
          "value": "Stored code and instruction/address tracing",
          "source": "hist-edvac-brl1961",
          "locator": "p. 239"
        },
        "workload": {
          "value": "Ballistics and scientific calculations",
          "source": "hist-edvac-brl1961",
          "locator": "p. 236"
        }
      },
      "diagram": {
        "title": "Four-address execution and operational diagnostics",
        "scope": "Semantic roles of the instruction fields and documented storage/I/O. Address nodes are decoded fields, not claimed separate hardware registers.",
        "nodes": [
          {
            "id": "instruction",
            "label": "Current instruction",
            "subtitle": "44 BITS",
            "text": "Contains A, B, C, D and operation.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-edvac-brl1961",
            "locator": "p. 237",
            "control": false
          },
          {
            "id": "operands",
            "label": "A / B addresses",
            "subtitle": "OPERAND SELECTION",
            "text": "Name two input locations.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-edvac-brl1961",
            "locator": "p. 237",
            "control": false
          },
          {
            "id": "next",
            "label": "D address",
            "subtitle": "NEXT INSTRUCTION",
            "text": "Names the following instruction.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-edvac-brl1961",
            "locator": "p. 237",
            "control": true
          },
          {
            "id": "mercury",
            "label": "Mercury delay store",
            "subtitle": "1,024 WORDS",
            "text": "Retains working instructions and numbers.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-edvac-brl1961",
            "locator": "p. 237",
            "control": false
          },
          {
            "id": "arithmetic",
            "label": "Serial arithmetic",
            "subtitle": "FIXED / FLOATING",
            "text": "Uses four rapid-access registers.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-edvac-brl1961",
            "locator": "p. 237",
            "control": false
          },
          {
            "id": "destination",
            "label": "C address",
            "subtitle": "RESULT SELECTION",
            "text": "Names the result location.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-edvac-brl1961",
            "locator": "p. 237",
            "control": false
          },
          {
            "id": "drum",
            "label": "Installed magnetic drum",
            "subtitle": "4,608 WORDS",
            "text": "Transfers variable-length word blocks.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-edvac-brl1961",
            "locator": "p. 237",
            "control": false
          },
          {
            "id": "io",
            "label": "Cards / paper tape",
            "subtitle": "INPUT / OUTPUT",
            "text": "Reads and records external data.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-edvac-brl1961",
            "locator": "p. 238",
            "control": false
          },
          {
            "id": "trace",
            "label": "Instruction trace",
            "subtitle": "DIAGNOSTIC STATE",
            "text": "Retains current and previous order locations.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-edvac-brl1961",
            "locator": "p. 239",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "mercury",
            "to": "instruction",
            "type": "data",
            "source": "hist-edvac-brl1961",
            "locator": "pp. 236–237",
            "label": ""
          },
          {
            "from": "instruction",
            "to": "operands",
            "type": "control",
            "source": "hist-edvac-brl1961",
            "locator": "p. 237 instruction format",
            "label": ""
          },
          {
            "from": "instruction",
            "to": "next",
            "type": "control",
            "source": "hist-edvac-brl1961",
            "locator": "p. 237 instruction format",
            "label": ""
          },
          {
            "from": "instruction",
            "to": "destination",
            "type": "control",
            "source": "hist-edvac-brl1961",
            "locator": "p. 237 instruction format",
            "label": ""
          },
          {
            "from": "operands",
            "to": "mercury",
            "type": "control",
            "source": "hist-edvac-brl1961",
            "locator": "p. 237 instruction format",
            "label": ""
          },
          {
            "from": "mercury",
            "to": "arithmetic",
            "type": "data",
            "source": "hist-edvac-brl1961",
            "locator": "p. 237 arithmetic unit",
            "label": ""
          },
          {
            "from": "arithmetic",
            "to": "mercury",
            "type": "data",
            "source": "hist-edvac-brl1961",
            "locator": "p. 237 instruction format",
            "label": ""
          },
          {
            "from": "destination",
            "to": "mercury",
            "type": "control",
            "source": "hist-edvac-brl1961",
            "locator": "p. 237 instruction format",
            "label": ""
          },
          {
            "from": "next",
            "to": "mercury",
            "type": "control",
            "source": "hist-edvac-brl1961",
            "locator": "p. 237 instruction format",
            "label": ""
          },
          {
            "from": "drum",
            "to": "mercury",
            "type": "data",
            "source": "hist-edvac-brl1961",
            "locator": "p. 237 storage",
            "label": ""
          },
          {
            "from": "mercury",
            "to": "drum",
            "type": "data",
            "source": "hist-edvac-brl1961",
            "locator": "p. 237 storage",
            "label": ""
          },
          {
            "from": "io",
            "to": "mercury",
            "type": "data",
            "source": "hist-edvac-brl1961",
            "locator": "p. 238 input",
            "label": ""
          },
          {
            "from": "mercury",
            "to": "io",
            "type": "data",
            "source": "hist-edvac-brl1961",
            "locator": "p. 238 output",
            "label": ""
          },
          {
            "from": "instruction",
            "to": "trace",
            "type": "association",
            "source": "hist-edvac-brl1961",
            "locator": "p. 239 diagnostic features",
            "label": ""
          }
        ]
      },
      "originalCandidate": "EDVAC"
    },
    {
      "id": "queue-011",
      "name": "IAS computer — Estrin’s built-machine description",
      "organization": "Institute for Advanced Study",
      "year": 1952,
      "yearLabel": "1952 designer report",
      "kind": "Electronic computer",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator",
        "hardwired"
      ],
      "substrates": [
        "vacuum-tube"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-ias-estrin"
      ],
      "summary": "Parallel arithmetic and CRT storage coordinated by asynchronous main, shift, address, and memory controls.",
      "config": "The actual machine in Estrin’s report, not a modern educational IAS simulator or every detail of the 1946 proposal.",
      "gaps": [
        "The proposed 4,000-word memory is not asserted as installed capacity.",
        "Added I/O facilities postdate the initial machine; the report states this explicitly."
      ],
      "originalName": "IAS computer",
      "insight": "How can completion signals replace a fixed instruction timing schedule?",
      "fields": {
        "state": {
          "value": "40-bit parallel fixed-point arithmetic",
          "source": "hist-ias-estrin",
          "locator": "pp. 95–96"
        },
        "compute": {
          "value": "RI accumulator, RII arithmetic register, parallel adder",
          "source": "hist-ias-estrin",
          "locator": "p. 96; Figure 3"
        },
        "memory": {
          "value": "Williams-tube memory via RIII",
          "source": "hist-ias-estrin",
          "locator": "p. 96; Figure 3"
        },
        "control": {
          "value": "Asynchronous main control and memory routines",
          "source": "hist-ias-estrin",
          "locator": "pp. 96–100"
        },
        "io": {
          "value": "Added drum/card I/O order",
          "source": "hist-ias-estrin",
          "locator": "p. 103"
        },
        "software": {
          "value": "Paired orders with conditional transfers",
          "source": "hist-ias-estrin",
          "locator": "pp. 102–103"
        },
        "workload": {
          "value": "Meteorological calculations",
          "source": "hist-ias-estrin",
          "locator": "p. 95"
        }
      },
      "diagram": {
        "title": "Asynchronous control around three register organs",
        "scope": "Figures 3, 11 and 12; numerical transfers and completion-driven control are distinguished.",
        "nodes": [
          {
            "id": "memory",
            "label": "CRT memory",
            "subtitle": "PARALLEL STORAGE",
            "text": "Supplies numbers and order pairs.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ias-estrin",
            "locator": "Figure 3",
            "control": false
          },
          {
            "id": "r3",
            "label": "Memory register RIII",
            "subtitle": "OPERAND / ORDER PAIR",
            "text": "Stages memory output.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ias-estrin",
            "locator": "p. 96",
            "control": false
          },
          {
            "id": "main",
            "label": "Main control",
            "subtitle": "ASYNCHRONOUS",
            "text": "Decodes orders and requests action.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ias-estrin",
            "locator": "pp. 96–97",
            "control": true
          },
          {
            "id": "r2",
            "label": "Arithmetic register RII",
            "subtitle": "MULTIPLIER / QUOTIENT",
            "text": "Shifts arithmetic state.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ias-estrin",
            "locator": "p. 96",
            "control": false
          },
          {
            "id": "adder",
            "label": "Adder and resolver",
            "subtitle": "40 PARALLEL STAGES",
            "text": "Combines resident and incident digits.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ias-estrin",
            "locator": "p. 96",
            "control": false
          },
          {
            "id": "memctl",
            "label": "Memory control",
            "subtitle": "REGENERATE / READ / WRITE",
            "text": "Sequences CRT operations.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ias-estrin",
            "locator": "p. 97",
            "control": true
          },
          {
            "id": "r1",
            "label": "Accumulator RI",
            "subtitle": "RESIDENT / RESULT",
            "text": "Holds sums and partial products.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ias-estrin",
            "locator": "p. 96",
            "control": false
          },
          {
            "id": "shift",
            "label": "Shift counter / chain",
            "subtitle": "COMPLETION CONTROL",
            "text": "Terminates requested shifts.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ias-estrin",
            "locator": "pp. 97, 100",
            "control": true
          },
          {
            "id": "addr",
            "label": "Address counter",
            "subtitle": "MEMORY LOCATION",
            "text": "Retains regeneration/order addresses.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ias-estrin",
            "locator": "p. 97",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "memory",
            "to": "r3",
            "type": "data",
            "source": "hist-ias-estrin",
            "locator": "Figure 3",
            "label": ""
          },
          {
            "from": "r3",
            "to": "adder",
            "type": "data",
            "source": "hist-ias-estrin",
            "locator": "p. 96 complement gates",
            "label": ""
          },
          {
            "from": "r1",
            "to": "adder",
            "type": "data",
            "source": "hist-ias-estrin",
            "locator": "p. 96",
            "label": ""
          },
          {
            "from": "adder",
            "to": "r1",
            "type": "data",
            "source": "hist-ias-estrin",
            "locator": "p. 96 digit resolver",
            "label": ""
          },
          {
            "from": "r2",
            "to": "r1",
            "type": "data",
            "source": "hist-ias-estrin",
            "locator": "pp. 102–103 shifting/register order",
            "label": ""
          },
          {
            "from": "r3",
            "to": "main",
            "type": "control",
            "source": "hist-ias-estrin",
            "locator": "p. 97 order decoding",
            "label": ""
          },
          {
            "from": "main",
            "to": "memctl",
            "type": "control",
            "source": "hist-ias-estrin",
            "locator": "p. 100 summation",
            "label": ""
          },
          {
            "from": "memctl",
            "to": "memory",
            "type": "control",
            "source": "hist-ias-estrin",
            "locator": "p. 97",
            "label": ""
          },
          {
            "from": "memctl",
            "to": "main",
            "type": "control",
            "source": "hist-ias-estrin",
            "locator": "p. 100 completion",
            "label": ""
          },
          {
            "from": "main",
            "to": "shift",
            "type": "control",
            "source": "hist-ias-estrin",
            "locator": "p. 100",
            "label": ""
          },
          {
            "from": "shift",
            "to": "r1",
            "type": "control",
            "source": "hist-ias-estrin",
            "locator": "p. 100",
            "label": ""
          },
          {
            "from": "shift",
            "to": "main",
            "type": "control",
            "source": "hist-ias-estrin",
            "locator": "p. 101 counter satisfaction",
            "label": ""
          },
          {
            "from": "addr",
            "to": "memctl",
            "type": "control",
            "source": "hist-ias-estrin",
            "locator": "p. 97",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IAS computer"
    },
    {
      "id": "queue-012",
      "name": "UNIVAC I — 1954 operations configuration",
      "organization": "Remington Rand",
      "year": 1954,
      "yearLabel": "1954 operating manual",
      "kind": "Commercial electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator"
      ],
      "substrates": [
        "vacuum-tube"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-univac-1954"
      ],
      "summary": "Character-word computation with paired instructions, arithmetic registers, and buffered 60-word magnetic-tape transfers.",
      "config": "UNIVAC I described by the 1954 operations manual; its instructional toy computer is excluded from the architecture.",
      "gaps": [
        "Buffer capacity is not the same as main-memory capacity.",
        "No timings from Chapter II’s simplified computer are attributed to UNIVAC I."
      ],
      "originalName": "UNIVAC I",
      "insight": "How do block buffers permit slow tape mechanisms to coexist with central computation?",
      "fields": {
        "state": {
          "value": "12 characters per word",
          "source": "hist-univac-1954",
          "locator": "Chapter I §2"
        },
        "compute": {
          "value": "rA/rX/rL/rF arithmetic registers",
          "source": "hist-univac-1954",
          "locator": "Chapter I §2; Chapter III"
        },
        "memory": {
          "value": "1,000-word main memory",
          "source": "hist-univac-1954",
          "locator": "Chapter I §2"
        },
        "control": {
          "value": "CC, CR and half-word SR",
          "source": "hist-univac-1954",
          "locator": "Chapter I §2; Chapter III"
        },
        "io": {
          "value": "Uniservo tape via rI/rO; console keyboard/typewriter",
          "source": "hist-univac-1954",
          "locator": "Chapter IV"
        },
        "software": {
          "value": "Two six-character instructions per word",
          "source": "hist-univac-1954",
          "locator": "Chapter I §2"
        },
        "workload": {
          "value": "Clerical and mathematical processing",
          "source": "hist-univac-1954",
          "locator": "Chapter I §1"
        }
      },
      "diagram": {
        "title": "Central computation and block-buffered tape",
        "scope": "Actual register transfers in Chapters III–IV; off-line card/tape conversion is outside the central computer.",
        "nodes": [
          {
            "id": "tape",
            "label": "Uniservo tape",
            "subtitle": "MAGNETIC BLOCKS",
            "text": "Reads or writes 60-word blocks.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-univac-1954",
            "locator": "Chapter IV §§2–3",
            "control": false
          },
          {
            "id": "input",
            "label": "Input register rI",
            "subtitle": "60-WORD BUFFER",
            "text": "Assembles a complete read block.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-univac-1954",
            "locator": "Chapter IV tape reading",
            "control": false
          },
          {
            "id": "control",
            "label": "CC / CR / SR",
            "subtitle": "PAIRED INSTRUCTIONS",
            "text": "Select and sequence instructions.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-univac-1954",
            "locator": "Chapter I §2",
            "control": true
          },
          {
            "id": "out",
            "label": "Output register rO",
            "subtitle": "60-WORD BUFFER",
            "text": "Holds a block while it is written.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-univac-1954",
            "locator": "Chapter IV tape writing",
            "control": false
          },
          {
            "id": "memory",
            "label": "Main memory",
            "subtitle": "1,000 WORDS",
            "text": "Retains instructions and data.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-univac-1954",
            "locator": "Chapter I §2",
            "control": false
          },
          {
            "id": "rx",
            "label": "rX / rL / rF",
            "subtitle": "ARITHMETIC STATE",
            "text": "Stage operands and multiply state.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-univac-1954",
            "locator": "Chapter III instructions",
            "control": false
          },
          {
            "id": "console",
            "label": "Console equipment",
            "subtitle": "KEYBOARD / TYPEWRITER",
            "text": "Provides direct maintenance/user I/O.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-univac-1954",
            "locator": "Chapter IV §8",
            "control": false
          },
          {
            "id": "ra",
            "label": "Accumulator rA",
            "subtitle": "ARITHMETIC RESULT",
            "text": "Receives sums and products.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-univac-1954",
            "locator": "Chapter III arithmetic",
            "control": false
          },
          {
            "id": "interlock",
            "label": "I/O interlocks",
            "subtitle": "BUFFER AVAILABILITY",
            "text": "Prevent premature overlapping transfers.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-univac-1954",
            "locator": "Chapter IV interlocks",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "tape",
            "to": "input",
            "type": "data",
            "source": "hist-univac-1954",
            "locator": "Chapter IV tape reading",
            "label": ""
          },
          {
            "from": "input",
            "to": "memory",
            "type": "data",
            "source": "hist-univac-1954",
            "locator": "Chapter IV input transfer",
            "label": ""
          },
          {
            "from": "memory",
            "to": "out",
            "type": "data",
            "source": "hist-univac-1954",
            "locator": "Chapter IV tape writing",
            "label": ""
          },
          {
            "from": "out",
            "to": "tape",
            "type": "data",
            "source": "hist-univac-1954",
            "locator": "Chapter IV tape writing",
            "label": ""
          },
          {
            "from": "memory",
            "to": "control",
            "type": "data",
            "source": "hist-univac-1954",
            "locator": "Chapter III order sequencing",
            "label": ""
          },
          {
            "from": "control",
            "to": "memory",
            "type": "control",
            "source": "hist-univac-1954",
            "locator": "Chapter III",
            "label": ""
          },
          {
            "from": "memory",
            "to": "rx",
            "type": "data",
            "source": "hist-univac-1954",
            "locator": "Chapter III arithmetic",
            "label": ""
          },
          {
            "from": "rx",
            "to": "ra",
            "type": "data",
            "source": "hist-univac-1954",
            "locator": "Chapter III arithmetic",
            "label": ""
          },
          {
            "from": "ra",
            "to": "memory",
            "type": "data",
            "source": "hist-univac-1954",
            "locator": "Chapter III transfer instructions",
            "label": ""
          },
          {
            "from": "console",
            "to": "memory",
            "type": "data",
            "source": "hist-univac-1954",
            "locator": "Chapter IV §8",
            "label": ""
          },
          {
            "from": "memory",
            "to": "console",
            "type": "data",
            "source": "hist-univac-1954",
            "locator": "Chapter IV §8",
            "label": ""
          },
          {
            "from": "interlock",
            "to": "input",
            "type": "control",
            "source": "hist-univac-1954",
            "locator": "Chapter IV interlocks",
            "label": ""
          },
          {
            "from": "interlock",
            "to": "out",
            "type": "control",
            "source": "hist-univac-1954",
            "locator": "Chapter IV interlocks",
            "label": ""
          }
        ]
      },
      "originalCandidate": "UNIVAC I"
    },
    {
      "id": "queue-013",
      "name": "Ferranti Mark 1 — eight-CRT configuration",
      "organization": "Ferranti / University of Manchester",
      "year": 1951,
      "yearLabel": "1951 designer account",
      "kind": "Commercial electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator"
      ],
      "substrates": [
        "vacuum-tube",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-ferranti-designers",
        "hist-ferranti-turing-b"
      ],
      "summary": "B-lines modify instructions while keyword-controlled drum and teleprinter transfers complement an 80-bit accumulator.",
      "config": "Eight-CRT machine in the designer account; anticipated maximum drum/CRT capacities in other descriptions are excluded.",
      "gaps": [
        "Turing’s handbook describes some anticipated capacities; this record follows the designer paper’s installed eight-CRT statement."
      ],
      "originalName": "Ferranti Mark 1",
      "insight": "How can an index register modify an instruction before execution?",
      "fields": {
        "state": {
          "value": "40-bit numbers; 20-bit orders; 80-bit accumulator",
          "source": "hist-ferranti-designers",
          "locator": "Present Machine"
        },
        "compute": {
          "value": "Serial arithmetic with faster electronic multiplier",
          "source": "hist-ferranti-designers",
          "locator": "Accumulator"
        },
        "memory": {
          "value": "10,240 CRT bits; about 150,000 installed drum bits",
          "source": "hist-ferranti-designers",
          "locator": "Storage"
        },
        "control": {
          "value": "Eight B-lines and keyword staticisor",
          "source": "hist-ferranti-designers",
          "locator": "B Tube; Input and Output"
        },
        "io": {
          "value": "Photoelectric tape; punch and teleprinter",
          "source": "hist-ferranti-designers",
          "locator": "Input and Output"
        },
        "software": {
          "value": "Programmed I/O and drum-held subprograms",
          "source": "hist-ferranti-designers",
          "locator": "Storage; Input and Output"
        },
        "workload": {
          "value": "Diverse mathematical and engineering programs",
          "source": "hist-ferranti-designers",
          "locator": "Programme of Work"
        }
      },
      "diagram": {
        "title": "B modification and keyword-directed transfers",
        "scope": "Functional organization of the present Ferranti machine, distinct from the 1949 experimental machines.",
        "nodes": [
          {
            "id": "crt",
            "label": "Eight CRT pages",
            "subtitle": "WORKING STORE",
            "text": "Retain numbers, orders and keywords.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ferranti-designers",
            "locator": "Storage",
            "control": false
          },
          {
            "id": "b",
            "label": "Eight B-lines",
            "subtitle": "20-BIT MODIFIERS",
            "text": "Modify orders and count loops.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ferranti-designers",
            "locator": "B Tube",
            "control": false
          },
          {
            "id": "control",
            "label": "Instruction control",
            "subtitle": "20-BIT ORDERS",
            "text": "Selects and interprets operations.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ferranti-designers",
            "locator": "Present Machine; B Tube",
            "control": true
          },
          {
            "id": "drum",
            "label": "Magnetic drum",
            "subtitle": "SUBPROGRAM STORE",
            "text": "Transfers pages or whole tracks.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ferranti-designers",
            "locator": "Storage",
            "control": false
          },
          {
            "id": "keyword",
            "label": "Magnetic staticisor",
            "subtitle": "TRANSFER CONTROL",
            "text": "Interprets storage and I/O keywords.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ferranti-designers",
            "locator": "Storage; Input and Output",
            "control": true
          },
          {
            "id": "mult",
            "label": "Electronic multiplier",
            "subtitle": "PARALLEL SUBPRODUCTS",
            "text": "Combines delayed partial products.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ferranti-designers",
            "locator": "Accumulator",
            "control": false
          },
          {
            "id": "a",
            "label": "Accumulator",
            "subtitle": "80 BITS",
            "text": "Retains sums and signed products.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ferranti-designers",
            "locator": "Accumulator",
            "control": false
          },
          {
            "id": "input",
            "label": "Tape reader",
            "subtitle": "200 CHARACTERS/S",
            "text": "Supplies five-bit characters.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ferranti-designers",
            "locator": "Input and Output",
            "control": false
          },
          {
            "id": "output",
            "label": "Punch / teleprinter",
            "subtitle": "10 CHARACTERS/S",
            "text": "Records programmed output.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ferranti-designers",
            "locator": "Input and Output",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "crt",
            "to": "control",
            "type": "data",
            "source": "hist-ferranti-designers",
            "locator": "Present Machine",
            "label": ""
          },
          {
            "from": "b",
            "to": "control",
            "type": "data",
            "source": "hist-ferranti-designers",
            "locator": "B Tube",
            "label": ""
          },
          {
            "from": "crt",
            "to": "b",
            "type": "data",
            "source": "hist-ferranti-designers",
            "locator": "B Tube",
            "label": ""
          },
          {
            "from": "b",
            "to": "crt",
            "type": "data",
            "source": "hist-ferranti-designers",
            "locator": "B Tube",
            "label": ""
          },
          {
            "from": "crt",
            "to": "keyword",
            "type": "data",
            "source": "hist-ferranti-designers",
            "locator": "Present Machine; Storage",
            "label": ""
          },
          {
            "from": "keyword",
            "to": "drum",
            "type": "control",
            "source": "hist-ferranti-designers",
            "locator": "Storage",
            "label": ""
          },
          {
            "from": "drum",
            "to": "crt",
            "type": "data",
            "source": "hist-ferranti-designers",
            "locator": "Storage",
            "label": ""
          },
          {
            "from": "crt",
            "to": "drum",
            "type": "data",
            "source": "hist-ferranti-designers",
            "locator": "Storage",
            "label": ""
          },
          {
            "from": "crt",
            "to": "mult",
            "type": "data",
            "source": "hist-ferranti-designers",
            "locator": "Accumulator",
            "label": ""
          },
          {
            "from": "mult",
            "to": "a",
            "type": "data",
            "source": "hist-ferranti-designers",
            "locator": "Accumulator",
            "label": ""
          },
          {
            "from": "keyword",
            "to": "input",
            "type": "control",
            "source": "hist-ferranti-designers",
            "locator": "Input and Output",
            "label": ""
          },
          {
            "from": "keyword",
            "to": "output",
            "type": "control",
            "source": "hist-ferranti-designers",
            "locator": "Input and Output",
            "label": ""
          },
          {
            "from": "input",
            "to": "a",
            "type": "data",
            "source": "hist-ferranti-designers",
            "locator": "final experimental machine I/O retained by Present Machine item 7",
            "label": ""
          },
          {
            "from": "a",
            "to": "output",
            "type": "data",
            "source": "hist-ferranti-designers",
            "locator": "final experimental machine I/O retained by Present Machine item 7",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Ferranti Mark 1"
    },
    {
      "id": "queue-014",
      "name": "Whirlwind I — R-221 core-memory system",
      "organization": "MIT Digital Computer Laboratory",
      "year": 1954,
      "yearLabel": "May 1954 operational logic",
      "kind": "Research electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator",
        "hardwired"
      ],
      "substrates": [
        "vacuum-tube",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-whirlwind-r221"
      ],
      "summary": "A parallel 16-wire bus links gated registers; core memory uses a separate controller and parity-register interface.",
      "config": "R-221’s two-bank core store; test storage substitutes for the lowest 32 core addresses.",
      "gaps": [
        "The earlier electrostatic store and later memory expansion are outside this revision."
      ],
      "originalName": "Whirlwind I",
      "insight": "Why does core memory hand control back after its own access cycle?",
      "fields": {
        "state": {
          "value": "16-bit binary, normally fixed-point",
          "source": "hist-whirlwind-r221",
          "locator": "§1.3"
        },
        "compute": {
          "value": "Accumulator-centered arithmetic element",
          "source": "hist-whirlwind-r221",
          "locator": "§2.23"
        },
        "memory": {
          "value": "2,048 core words with 32 addresses overlaid by test storage",
          "source": "hist-whirlwind-r221",
          "locator": "§2.21"
        },
        "control": {
          "value": "Program counter, control switch and time-pulse matrix",
          "source": "hist-whirlwind-r221",
          "locator": "§2.22"
        },
        "io": {
          "value": "Paper/magnetic tape, drum, typewriter and display",
          "source": "hist-whirlwind-r221",
          "locator": "§1.2"
        },
        "software": {
          "value": "Stored instructions; programmed number conversion",
          "source": "hist-whirlwind-r221",
          "locator": "§1.31; §2.1"
        },
        "workload": {
          "value": "Numerical computation and asynchronous terminal data",
          "source": "hist-whirlwind-r221",
          "locator": "§1.2"
        }
      },
      "diagram": {
        "title": "Gated bus transfers with an independent core-memory cycle",
        "scope": "R-221’s actual storage distinction: test registers attach to the bus; core words pass through parity register.",
        "nodes": [
          {
            "id": "core",
            "label": "Magnetic-core banks",
            "subtitle": "2 × 1,024 WORDS",
            "text": "Readout requires restoration.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-whirlwind-r221",
            "locator": "§2.21",
            "control": false
          },
          {
            "id": "par",
            "label": "Parity register",
            "subtitle": "16 BITS",
            "text": "Stages and checks core transfers.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-whirlwind-r221",
            "locator": "§2.212",
            "control": false
          },
          {
            "id": "ms",
            "label": "MS control",
            "subtitle": "MEMORY CYCLE",
            "text": "Returns control after access.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-whirlwind-r221",
            "locator": "§2.21",
            "control": true
          },
          {
            "id": "test",
            "label": "Test storage",
            "subtitle": "32 OVERLAID WORDS",
            "text": "Provides initial instructions.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-whirlwind-r221",
            "locator": "§2.21",
            "control": false
          },
          {
            "id": "bus",
            "label": "Digit-transfer bus",
            "subtitle": "16 PARALLEL LINES",
            "text": "Carries one number at a time.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-whirlwind-r221",
            "locator": "§1.4",
            "control": false
          },
          {
            "id": "ae",
            "label": "Arithmetic element",
            "subtitle": "AC / A / B",
            "text": "Retains operands and results.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-whirlwind-r221",
            "locator": "§2.23",
            "control": false
          },
          {
            "id": "pc",
            "label": "Program counter",
            "subtitle": "11 ADDRESS BITS",
            "text": "Selects successive instructions.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-whirlwind-r221",
            "locator": "§2.222",
            "control": false
          },
          {
            "id": "matrix",
            "label": "Control switch / TPD",
            "subtitle": "CONTROL MATRIX",
            "text": "Gates transfers in pulse order.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-whirlwind-r221",
            "locator": "§2.223–2.224",
            "control": true
          },
          {
            "id": "io",
            "label": "In-out system",
            "subtitle": "TERMINALS / BUFFER",
            "text": "Connects slower external equipment.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-whirlwind-r221",
            "locator": "§1.2; §2.24",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "core",
            "to": "par",
            "type": "data",
            "source": "hist-whirlwind-r221",
            "locator": "§2.21",
            "label": ""
          },
          {
            "from": "par",
            "to": "core",
            "type": "data",
            "source": "hist-whirlwind-r221",
            "locator": "§2.21",
            "label": ""
          },
          {
            "from": "par",
            "to": "bus",
            "type": "data",
            "source": "hist-whirlwind-r221",
            "locator": "§2.212",
            "label": ""
          },
          {
            "from": "bus",
            "to": "par",
            "type": "data",
            "source": "hist-whirlwind-r221",
            "locator": "§2.212",
            "label": ""
          },
          {
            "from": "test",
            "to": "bus",
            "type": "data",
            "source": "hist-whirlwind-r221",
            "locator": "§2.21",
            "label": ""
          },
          {
            "from": "bus",
            "to": "ae",
            "type": "data",
            "source": "hist-whirlwind-r221",
            "locator": "§2.23",
            "label": ""
          },
          {
            "from": "ae",
            "to": "bus",
            "type": "data",
            "source": "hist-whirlwind-r221",
            "locator": "§2.23",
            "label": ""
          },
          {
            "from": "pc",
            "to": "bus",
            "type": "data",
            "source": "hist-whirlwind-r221",
            "locator": "§2.11 Figure 2",
            "label": ""
          },
          {
            "from": "bus",
            "to": "matrix",
            "type": "data",
            "source": "hist-whirlwind-r221",
            "locator": "§2.224",
            "label": ""
          },
          {
            "from": "matrix",
            "to": "bus",
            "type": "control",
            "source": "hist-whirlwind-r221",
            "locator": "§2.223",
            "label": ""
          },
          {
            "from": "matrix",
            "to": "ms",
            "type": "control",
            "source": "hist-whirlwind-r221",
            "locator": "§2.21",
            "label": ""
          },
          {
            "from": "ms",
            "to": "matrix",
            "type": "control",
            "source": "hist-whirlwind-r221",
            "locator": "§2.21",
            "label": ""
          },
          {
            "from": "ms",
            "to": "core",
            "type": "control",
            "source": "hist-whirlwind-r221",
            "locator": "§2.21",
            "label": ""
          },
          {
            "from": "io",
            "to": "bus",
            "type": "data",
            "source": "hist-whirlwind-r221",
            "locator": "§1.4",
            "label": ""
          },
          {
            "from": "bus",
            "to": "io",
            "type": "data",
            "source": "hist-whirlwind-r221",
            "locator": "§1.4",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Whirlwind I"
    },
    {
      "id": "queue-015",
      "name": "IBM 701 — two-Type-706 installation",
      "organization": "IBM",
      "year": 1953,
      "yearLabel": "1953 Principles of Operation",
      "kind": "Commercial electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator"
      ],
      "substrates": [
        "vacuum-tube"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-ibm701-principles"
      ],
      "summary": "CRT storage feeds a memory register before accumulator or multiplier-quotient use, with stored-program sequencing and several peripheral media.",
      "config": "The manual’s installation with two Type 706 electrostatic units; one-unit installations have less memory.",
      "gaps": [
        "Accumulator includes extra overflow positions; it is not simply a 36-bit memory word.",
        "Peripheral device paths are aggregated at the system boundary."
      ],
      "originalName": "IBM 701",
      "insight": "Which register lies between a stored word and the arithmetic operands?",
      "fields": {
        "state": {
          "value": "36-bit words or 18-bit half-words",
          "source": "hist-ibm701-principles",
          "locator": "p. 12"
        },
        "compute": {
          "value": "Accumulator, MQ and memory registers",
          "source": "hist-ibm701-principles",
          "locator": "p. 17"
        },
        "memory": {
          "value": "2,048 full words with two storage units",
          "source": "hist-ibm701-principles",
          "locator": "p. 13"
        },
        "control": {
          "value": "Half-word instructions and instruction sequencer",
          "source": "hist-ibm701-principles",
          "locator": "p. 23"
        },
        "io": {
          "value": "Cards, printer, magnetic tape and drum",
          "source": "hist-ibm701-principles",
          "locator": "Installation list; p. 11"
        },
        "software": {
          "value": "Stored one-address program",
          "source": "hist-ibm701-principles",
          "locator": "pp. 11, 23"
        },
        "workload": {
          "value": "Binary numerical calculations",
          "source": "hist-ibm701-principles",
          "locator": "p. 11"
        }
      },
      "diagram": {
        "title": "The memory register mediates arithmetic transfers",
        "scope": "Figure 3 and pp. 11–23; peripherals are summarized separately from the register flow.",
        "nodes": [
          {
            "id": "crt",
            "label": "Type 706 CRT storage",
            "subtitle": "2,048 FULL WORDS",
            "text": "Stores instructions and numbers.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ibm701-principles",
            "locator": "p. 13",
            "control": false
          },
          {
            "id": "mr",
            "label": "Memory register",
            "subtitle": "36-BIT TRANSFER",
            "text": "Stages words before arithmetic use.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ibm701-principles",
            "locator": "p. 18; Figure 3",
            "control": false
          },
          {
            "id": "seq",
            "label": "Instruction sequencer",
            "subtitle": "HALF-WORD ORDERS",
            "text": "Controls instruction succession.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ibm701-principles",
            "locator": "p. 23",
            "control": true
          },
          {
            "id": "ac",
            "label": "Accumulator",
            "subtitle": "OVERFLOW POSITIONS",
            "text": "Retains arithmetic results.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ibm701-principles",
            "locator": "p. 17",
            "control": false
          },
          {
            "id": "mq",
            "label": "MQ register",
            "subtitle": "MULTIPLIER / QUOTIENT",
            "text": "Supports multiplication and division.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ibm701-principles",
            "locator": "p. 17",
            "control": false
          },
          {
            "id": "tape",
            "label": "Type 726 tape",
            "subtitle": "READ / RECORD",
            "text": "Provides external storage/I/O.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ibm701-principles",
            "locator": "Installation list; p. 14",
            "control": false
          },
          {
            "id": "cards",
            "label": "Card reader / recorder",
            "subtitle": "TYPES 711 / 721",
            "text": "Loads programs/data and punches output.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ibm701-principles",
            "locator": "Installation list; p. 12",
            "control": false
          },
          {
            "id": "drum",
            "label": "Type 731 drum",
            "subtitle": "SECONDARY STORAGE",
            "text": "Retains reusable blocks.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ibm701-principles",
            "locator": "p. 13",
            "control": false
          },
          {
            "id": "printer",
            "label": "Type 716 printer",
            "subtitle": "READABLE OUTPUT",
            "text": "Prints computation results.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ibm701-principles",
            "locator": "Installation list; p. 11",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "crt",
            "to": "mr",
            "type": "data",
            "source": "hist-ibm701-principles",
            "locator": "p. 18; Figure 3",
            "label": ""
          },
          {
            "from": "mr",
            "to": "ac",
            "type": "data",
            "source": "hist-ibm701-principles",
            "locator": "p. 18; Figure 3",
            "label": ""
          },
          {
            "from": "mr",
            "to": "mq",
            "type": "data",
            "source": "hist-ibm701-principles",
            "locator": "p. 18; Figure 3",
            "label": ""
          },
          {
            "from": "ac",
            "to": "crt",
            "type": "data",
            "source": "hist-ibm701-principles",
            "locator": "pp. 18–19 register-to-store instructions",
            "label": ""
          },
          {
            "from": "crt",
            "to": "seq",
            "type": "data",
            "source": "hist-ibm701-principles",
            "locator": "p. 23",
            "label": ""
          },
          {
            "from": "seq",
            "to": "crt",
            "type": "control",
            "source": "hist-ibm701-principles",
            "locator": "p. 23",
            "label": ""
          },
          {
            "from": "cards",
            "to": "crt",
            "type": "data",
            "source": "hist-ibm701-principles",
            "locator": "p. 12 program loading",
            "label": ""
          },
          {
            "from": "crt",
            "to": "cards",
            "type": "data",
            "source": "hist-ibm701-principles",
            "locator": "p. 11 output",
            "label": ""
          },
          {
            "from": "tape",
            "to": "crt",
            "type": "data",
            "source": "hist-ibm701-principles",
            "locator": "p. 11",
            "label": ""
          },
          {
            "from": "crt",
            "to": "tape",
            "type": "data",
            "source": "hist-ibm701-principles",
            "locator": "p. 11",
            "label": ""
          },
          {
            "from": "drum",
            "to": "crt",
            "type": "data",
            "source": "hist-ibm701-principles",
            "locator": "p. 11",
            "label": ""
          },
          {
            "from": "crt",
            "to": "drum",
            "type": "data",
            "source": "hist-ibm701-principles",
            "locator": "p. 11",
            "label": ""
          },
          {
            "from": "crt",
            "to": "printer",
            "type": "data",
            "source": "hist-ibm701-principles",
            "locator": "p. 11",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IBM 701"
    },
    {
      "id": "queue-016",
      "name": "IBM 650 — 2,000-word drum configuration",
      "organization": "IBM",
      "year": 1954,
      "yearLabel": "650 engineering-manual configuration",
      "kind": "Commercial electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator"
      ],
      "substrates": [
        "vacuum-tube",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-ibm650-engineering"
      ],
      "summary": "Digit-serial decimal arithmetic is organized around a rotating drum with distinct read and punch buffers.",
      "config": "2,000-word arrangement in Section I; the manual also describes a 1,000-word option, which is not silently substituted.",
      "gaps": [
        "1954 identifies the model era; no precise print date is claimed for this undated revision.",
        "Timing-track diagrams explain logical timing; the atlas does not reproduce all head circuitry."
      ],
      "originalName": "IBM 650",
      "insight": "How does drum position influence both instruction placement and peripheral overlap?",
      "fields": {
        "state": {
          "value": "Ten decimal digits plus sign per word",
          "source": "hist-ibm650-engineering",
          "locator": "p. I-1"
        },
        "compute": {
          "value": "Digit-serial arithmetic; 20-digit totals/products",
          "source": "hist-ibm650-engineering",
          "locator": "p. I-1"
        },
        "memory": {
          "value": "2,000 general-storage drum locations",
          "source": "hist-ibm650-engineering",
          "locator": "p. I-3"
        },
        "control": {
          "value": "Instruction word gives operation, data and next-instruction addresses",
          "source": "hist-ibm650-engineering",
          "locator": "p. I-1"
        },
        "io": {
          "value": "Ten-word read/punch buffers with card equipment",
          "source": "hist-ibm650-engineering",
          "locator": "p. I-9"
        },
        "software": {
          "value": "Stored decimal instruction words",
          "source": "hist-ibm650-engineering",
          "locator": "p. I-1"
        },
        "workload": {
          "value": "Technical and accounting data",
          "source": "hist-ibm650-engineering",
          "locator": "p. I-1"
        }
      },
      "diagram": {
        "title": "Drum storage, timing, and overlapping card I/O",
        "scope": "Section I’s documented drum and buffer paths; shared physical band does not mean simultaneous identical buffer contents.",
        "nodes": [
          {
            "id": "reader",
            "label": "Card reader",
            "subtitle": "INPUT CARDS",
            "text": "Loads the read buffer.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ibm650-engineering",
            "locator": "p. I-9",
            "control": false
          },
          {
            "id": "rbs",
            "label": "Read-buffer storage",
            "subtitle": "10 WORDS",
            "text": "Stages converted card data.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ibm650-engineering",
            "locator": "p. I-9",
            "control": false
          },
          {
            "id": "control",
            "label": "Program control",
            "subtitle": "INSTRUCTION FIELDS",
            "text": "Selects operations and locations.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ibm650-engineering",
            "locator": "p. I-1",
            "control": true
          },
          {
            "id": "drum",
            "label": "General drum storage",
            "subtitle": "2,000 WORDS",
            "text": "Retains instructions and data.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ibm650-engineering",
            "locator": "p. I-3",
            "control": false
          },
          {
            "id": "timing",
            "label": "Drum timing tracks",
            "subtitle": "ANGULAR POSITION",
            "text": "Supply machine timing references.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ibm650-engineering",
            "locator": "p. I-8",
            "control": true
          },
          {
            "id": "address",
            "label": "Address / head selection",
            "subtitle": "STATIC + DYNAMIC",
            "text": "Selects band and word position.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ibm650-engineering",
            "locator": "pp. I-3, I-5",
            "control": true
          },
          {
            "id": "pbs",
            "label": "Punch-buffer storage",
            "subtitle": "10 WORDS",
            "text": "Stages output card words.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ibm650-engineering",
            "locator": "p. I-9",
            "control": false
          },
          {
            "id": "arith",
            "label": "Arithmetic units",
            "subtitle": "DIGIT-SERIAL DECIMAL",
            "text": "Operate on successive digits.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ibm650-engineering",
            "locator": "p. I-1",
            "control": false
          },
          {
            "id": "punch",
            "label": "Card punch",
            "subtitle": "OUTPUT CARDS",
            "text": "Records decimal output.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ibm650-engineering",
            "locator": "p. I-9",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "reader",
            "to": "rbs",
            "type": "data",
            "source": "hist-ibm650-engineering",
            "locator": "p. I-9",
            "label": ""
          },
          {
            "from": "rbs",
            "to": "drum",
            "type": "data",
            "source": "hist-ibm650-engineering",
            "locator": "p. I-9",
            "label": ""
          },
          {
            "from": "drum",
            "to": "pbs",
            "type": "data",
            "source": "hist-ibm650-engineering",
            "locator": "p. I-9",
            "label": ""
          },
          {
            "from": "pbs",
            "to": "punch",
            "type": "data",
            "source": "hist-ibm650-engineering",
            "locator": "p. I-9",
            "label": ""
          },
          {
            "from": "drum",
            "to": "control",
            "type": "data",
            "source": "hist-ibm650-engineering",
            "locator": "p. I-1",
            "label": ""
          },
          {
            "from": "control",
            "to": "address",
            "type": "control",
            "source": "hist-ibm650-engineering",
            "locator": "pp. I-1, I-3",
            "label": ""
          },
          {
            "from": "address",
            "to": "drum",
            "type": "control",
            "source": "hist-ibm650-engineering",
            "locator": "p. I-3",
            "label": ""
          },
          {
            "from": "timing",
            "to": "address",
            "type": "control",
            "source": "hist-ibm650-engineering",
            "locator": "p. I-8",
            "label": ""
          },
          {
            "from": "timing",
            "to": "arith",
            "type": "control",
            "source": "hist-ibm650-engineering",
            "locator": "p. I-8",
            "label": ""
          },
          {
            "from": "control",
            "to": "arith",
            "type": "control",
            "source": "hist-ibm650-engineering",
            "locator": "p. I-1",
            "label": ""
          },
          {
            "from": "drum",
            "to": "arith",
            "type": "data",
            "source": "hist-ibm650-engineering",
            "locator": "p. I-1",
            "label": ""
          },
          {
            "from": "arith",
            "to": "drum",
            "type": "data",
            "source": "hist-ibm650-engineering",
            "locator": "p. I-1",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IBM 650"
    },
    {
      "id": "queue-017",
      "name": "BESM-6 — original architecture",
      "organization": "ITM and VT / Moscow SAM plant",
      "year": 1967,
      "yearLabel": "Development completed 1967; production 1968",
      "kind": "Scientific computer",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "pipelined"
      ],
      "substrates": [
        "transistor",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-besm6-institution"
      ],
      "summary": "Buffered asynchronous units overlap work while index arithmetic, associative operand storage and banked memory reduce stalls.",
      "config": "Original BESM-6 organization; later disk and capacity upgrades are excluded.",
      "gaps": [
        "English memory-capacity wording mixes KB and word counts; capacity is deliberately unasserted.",
        "The institutional overview lacks a full wiring diagram."
      ],
      "originalName": "BESM-6",
      "insight": "Which kinds of state let asynchronous units make progress independently?",
      "fields": {
        "state": {
          "value": "48-bit floating-point words plus two check bits",
          "source": "hist-besm6-institution",
          "locator": "item 14"
        },
        "compute": {
          "value": "Asynchronous arithmetic and instruction overlap",
          "source": "hist-besm6-institution",
          "locator": "item 10"
        },
        "memory": {
          "value": "Banked ferrite memory and associative operand registers",
          "source": "hist-besm6-institution",
          "locator": "item 10"
        },
        "control": {
          "value": "Separate address unit, index registers and protected modes",
          "source": "hist-besm6-institution",
          "locator": "item 10"
        },
        "io": {
          "value": "Seven high-speed storage buses; interrupt-driven peripherals",
          "source": "hist-besm6-institution",
          "locator": "item 10"
        },
        "software": {
          "value": "Multiple operating systems and language translators",
          "source": "hist-besm6-institution",
          "locator": "item 13"
        },
        "workload": {
          "value": "Scientific and engineering calculations",
          "source": "hist-besm6-institution",
          "locator": "item 9"
        }
      },
      "diagram": {
        "title": "Buffers decouple arithmetic, addressing and memory",
        "scope": "Functional dependencies summarized by the institutional design record; no undocumented bypass paths.",
        "nodes": [
          {
            "id": "commands",
            "label": "Command buffers",
            "subtitle": "INTERMEDIATE STATE",
            "text": "Decouple control from store timing.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-besm6-institution",
            "locator": "item 10",
            "control": false
          },
          {
            "id": "control",
            "label": "Control unit",
            "subtitle": "OVERLAPPED EXECUTION",
            "text": "Coordinates instruction stages.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-besm6-institution",
            "locator": "item 10",
            "control": true
          },
          {
            "id": "index",
            "label": "Index-register memory",
            "subtitle": "ADDRESS STATE",
            "text": "Supports address modification and stacks.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-besm6-institution",
            "locator": "item 10",
            "control": false
          },
          {
            "id": "operands",
            "label": "Associative registers",
            "subtitle": "OPERAND CACHE",
            "text": "Reduce repeated store accesses.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-besm6-institution",
            "locator": "item 10",
            "control": false
          },
          {
            "id": "memory",
            "label": "Banked core memory",
            "subtitle": "INDEPENDENT BANKS",
            "text": "Serves simultaneous device accesses.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-besm6-institution",
            "locator": "item 10",
            "control": false
          },
          {
            "id": "address",
            "label": "Address calculation",
            "subtitle": "SEPARATE UNIT",
            "text": "Forms indexed operand addresses.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-besm6-institution",
            "locator": "item 10",
            "control": false
          },
          {
            "id": "alu",
            "label": "Arithmetic unit",
            "subtitle": "SUM / CARRY STATE",
            "text": "Uses accelerated multiply/divide.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-besm6-institution",
            "locator": "item 10",
            "control": false
          },
          {
            "id": "channel",
            "label": "Seven storage buses",
            "subtitle": "PARALLEL EXCHANGE",
            "text": "Connect external storage.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-besm6-institution",
            "locator": "item 10",
            "control": false
          },
          {
            "id": "external",
            "label": "Drums / magnetic tape",
            "subtitle": "EXTERNAL STATE",
            "text": "Retain bulk programs and data.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-besm6-institution",
            "locator": "item 10",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "memory",
            "to": "commands",
            "type": "data",
            "source": "hist-besm6-institution",
            "locator": "item 10 intermediate command storage",
            "label": ""
          },
          {
            "from": "commands",
            "to": "control",
            "type": "data",
            "source": "hist-besm6-institution",
            "locator": "item 10",
            "label": ""
          },
          {
            "from": "index",
            "to": "address",
            "type": "data",
            "source": "hist-besm6-institution",
            "locator": "item 10 address modification",
            "label": ""
          },
          {
            "from": "control",
            "to": "address",
            "type": "control",
            "source": "hist-besm6-institution",
            "locator": "item 10 pipeline processing",
            "label": ""
          },
          {
            "from": "address",
            "to": "memory",
            "type": "control",
            "source": "hist-besm6-institution",
            "locator": "item 10 address calculation",
            "label": ""
          },
          {
            "from": "memory",
            "to": "operands",
            "type": "data",
            "source": "hist-besm6-institution",
            "locator": "item 10 associative memory",
            "label": ""
          },
          {
            "from": "operands",
            "to": "alu",
            "type": "data",
            "source": "hist-besm6-institution",
            "locator": "item 10 saved operands",
            "label": ""
          },
          {
            "from": "control",
            "to": "alu",
            "type": "control",
            "source": "hist-besm6-institution",
            "locator": "item 10 parallel asynchronous operation",
            "label": ""
          },
          {
            "from": "alu",
            "to": "memory",
            "type": "data",
            "source": "hist-besm6-institution",
            "locator": "item 10 arithmetic/data buffers",
            "label": ""
          },
          {
            "from": "memory",
            "to": "channel",
            "type": "data",
            "source": "hist-besm6-institution",
            "locator": "item 10 exchange",
            "label": ""
          },
          {
            "from": "channel",
            "to": "memory",
            "type": "data",
            "source": "hist-besm6-institution",
            "locator": "item 10 exchange",
            "label": ""
          },
          {
            "from": "channel",
            "to": "external",
            "type": "data",
            "source": "hist-besm6-institution",
            "locator": "item 10 exchange",
            "label": ""
          },
          {
            "from": "external",
            "to": "channel",
            "type": "data",
            "source": "hist-besm6-institution",
            "locator": "item 10 exchange",
            "label": ""
          }
        ]
      },
      "originalCandidate": "BESM-6"
    },
    {
      "id": "queue-018",
      "name": "MESM — commissioned 1951 system",
      "organization": "Institute of Electrical Engineering, Ukrainian Academy of Sciences",
      "year": 1951,
      "yearLabel": "Accepted for service 25 December 1951",
      "kind": "Research electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "harvard"
      ],
      "substrates": [
        "vacuum-tube"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-mesm-technical",
        "hist-mesm-makers",
        "hist-mesm-minutes"
      ],
      "summary": "Parallel fixed-point arithmetic operates with distinct number and command storage, supplemented by manually set functional information.",
      "config": "Commissioned MESM; January 1951 prototype’s planned automatic tape equipment is not treated as installed.",
      "gaps": [
        "The complete original circuit drawings were not inspected. Diagram shows documented functional roles, not physical bus topology.",
        "Magnetic-drum capability is documented; no unsupported installed capacity is assigned."
      ],
      "originalName": "MESM",
      "insight": "What is the difference between writable state and plug-set constants?",
      "fields": {
        "state": {
          "value": "16 magnitude bits and sign; binary fractions",
          "source": "hist-mesm-technical",
          "locator": "parameters 1–2"
        },
        "compute": {
          "value": "One parallel universal arithmetic unit",
          "source": "hist-mesm-technical",
          "locator": "parameters 6–8"
        },
        "memory": {
          "value": "31 number / 63 command writable locations; matching functional capacities",
          "source": "hist-mesm-technical",
          "locator": "parameters 3–5"
        },
        "control": {
          "value": "Three-address commands and control transfers",
          "source": "hist-mesm-technical",
          "locator": "parameters 6–7"
        },
        "io": {
          "value": "Cards or plug-set input; photographic/electromechanical output",
          "source": "hist-mesm-technical",
          "locator": "parameters 9, 11–12"
        },
        "software": {
          "value": "Machine-code programs and diagnostic tests",
          "source": "hist-mesm-technical",
          "locator": "parameters 13–14"
        },
        "workload": {
          "value": "Statistics, integral equations and power-system stability",
          "source": "hist-mesm-makers",
          "locator": "Operation section, examples"
        }
      },
      "diagram": {
        "title": "Separate command and number stores around parallel arithmetic",
        "scope": "Semantic storage/control relationships in the commissioned machine; input/output preparation equipment lies outside these roles.",
        "nodes": [
          {
            "id": "numbers",
            "label": "Writable number store",
            "subtitle": "31 NUMBERS",
            "text": "Retains working numeric state.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-mesm-technical",
            "locator": "parameters 3–4",
            "control": false
          },
          {
            "id": "commands",
            "label": "Writable command store",
            "subtitle": "63 COMMANDS",
            "text": "Retains executable orders.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-mesm-technical",
            "locator": "parameters 3–4",
            "control": false
          },
          {
            "id": "control",
            "label": "Control unit",
            "subtitle": "THREE-ADDRESS CODE",
            "text": "Selects arithmetic and control transfers.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-mesm-technical",
            "locator": "parameters 6–7",
            "control": true
          },
          {
            "id": "constants",
            "label": "Functional number store",
            "subtitle": "31 NUMBERS",
            "text": "Supplies plug-set numeric information.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-mesm-technical",
            "locator": "parameter 5; parameter 11",
            "control": false
          },
          {
            "id": "fixed",
            "label": "Functional command store",
            "subtitle": "63 COMMANDS",
            "text": "Supplies fixed instruction information.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-mesm-technical",
            "locator": "parameter 5",
            "control": false
          },
          {
            "id": "arith",
            "label": "Parallel arithmetic",
            "subtitle": "TRIGGER-CELL LOGIC",
            "text": "Adds, multiplies, divides and compares.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-mesm-technical",
            "locator": "parameters 6, 8",
            "control": false
          },
          {
            "id": "input",
            "label": "Card / plug input",
            "subtitle": "SERIAL NUMBER ENTRY",
            "text": "Introduces external numeric state.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-mesm-technical",
            "locator": "parameters 9, 11",
            "control": false
          },
          {
            "id": "output",
            "label": "Results readout",
            "subtitle": "PHOTO / PRINT",
            "text": "Makes results externally readable.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-mesm-technical",
            "locator": "parameter 12",
            "control": false
          },
          {
            "id": "tests",
            "label": "Diagnostic operation",
            "subtitle": "MANUAL / SEMIAUTO",
            "text": "Localizes hardware faults.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-mesm-technical",
            "locator": "parameters 13–14",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "commands",
            "to": "control",
            "type": "data",
            "source": "hist-mesm-technical",
            "locator": "parameters 4, 7",
            "label": ""
          },
          {
            "from": "fixed",
            "to": "control",
            "type": "data",
            "source": "hist-mesm-technical",
            "locator": "parameters 5, 7",
            "label": ""
          },
          {
            "from": "control",
            "to": "arith",
            "type": "control",
            "source": "hist-mesm-technical",
            "locator": "parameters 6–8",
            "label": ""
          },
          {
            "from": "numbers",
            "to": "arith",
            "type": "data",
            "source": "hist-mesm-technical",
            "locator": "parameters 4, 8",
            "label": ""
          },
          {
            "from": "constants",
            "to": "arith",
            "type": "data",
            "source": "hist-mesm-technical",
            "locator": "parameters 5, 8",
            "label": ""
          },
          {
            "from": "arith",
            "to": "numbers",
            "type": "data",
            "source": "hist-mesm-technical",
            "locator": "parameters 4, 6",
            "label": ""
          },
          {
            "from": "input",
            "to": "numbers",
            "type": "data",
            "source": "hist-mesm-technical",
            "locator": "parameters 9, 11",
            "label": ""
          },
          {
            "from": "input",
            "to": "constants",
            "type": "association",
            "source": "hist-mesm-technical",
            "locator": "parameter 11 plug-set information",
            "label": ""
          },
          {
            "from": "arith",
            "to": "output",
            "type": "association",
            "source": "hist-mesm-technical",
            "locator": "parameter 12 results readout",
            "label": ""
          },
          {
            "from": "tests",
            "to": "control",
            "type": "control",
            "source": "hist-mesm-technical",
            "locator": "parameter 14 manual/semiautomatic operation",
            "label": ""
          },
          {
            "from": "tests",
            "to": "arith",
            "type": "association",
            "source": "hist-mesm-technical",
            "locator": "parameters 13–14",
            "label": ""
          }
        ]
      },
      "originalCandidate": "MESM"
    },
    {
      "id": "queue-019",
      "name": "Setun — original ternary machine",
      "organization": "Moscow State University / Kazan computer plant",
      "year": 1958,
      "yearLabel": "Experimental machine operating by end of 1958",
      "kind": "Ternary electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator"
      ],
      "substrates": [
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-setun-designers"
      ],
      "summary": "Balanced ternary digits, a single index register and paged drum exchange support compact instructions and interpreted arithmetic.",
      "config": "Original Setun architecture with 162 short cells; both documented drum options remain explicit.",
      "gaps": [
        "This source does not detail device-level I/O paths; those are not invented.",
        "Setun 70’s two stacks are excluded."
      ],
      "originalName": "Setun",
      "insight": "How does a three-valued result sign control program branches?",
      "fields": {
        "state": {
          "value": "Balanced trits −1, 0, +1",
          "source": "hist-setun-designers",
          "locator": "§3"
        },
        "compute": {
          "value": "18-trit S accumulator and R multiplier",
          "source": "hist-setun-designers",
          "locator": "§3"
        },
        "memory": {
          "value": "162 × 9-trit cells; drum of 36 or 72 pages",
          "source": "hist-setun-designers",
          "locator": "§3"
        },
        "control": {
          "value": "9-trit orders; F index, C pointer, omega sign",
          "source": "hist-setun-designers",
          "locator": "§§2.1, 3"
        },
        "io": {
          "value": "Practical devices supported; detailed interface not specified here",
          "source": "hist-setun-designers",
          "locator": "§2"
        },
        "software": {
          "value": "IP interpreters, Poliz and program libraries",
          "source": "hist-setun-designers",
          "locator": "§2.2"
        },
        "workload": {
          "value": "University, engineering and scientific calculations",
          "source": "hist-setun-designers",
          "locator": "§2.2"
        }
      },
      "diagram": {
        "title": "Ternary registers and a paged two-level store",
        "scope": "Instruction effects and state relationships in the original Setun. Page exchange is distinct from arithmetic word access.",
        "nodes": [
          {
            "id": "c",
            "label": "Command pointer C",
            "subtitle": "SEQUENCE STATE",
            "text": "Identifies the command to fulfill.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-setun-designers",
            "locator": "§3",
            "control": false
          },
          {
            "id": "command",
            "label": "Command code",
            "subtitle": "9 TRITS",
            "text": "Selects one-address operations.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-setun-designers",
            "locator": "§§2.1, 3",
            "control": true
          },
          {
            "id": "f",
            "label": "Index F",
            "subtitle": "5 TRITS",
            "text": "Adds or subtracts address modification.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-setun-designers",
            "locator": "§§2.1, 3",
            "control": false
          },
          {
            "id": "drum",
            "label": "Magnetic drum",
            "subtitle": "36 / 72 PAGES",
            "text": "Retains paged external state.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-setun-designers",
            "locator": "§3",
            "control": false
          },
          {
            "id": "memory",
            "label": "Operating memory",
            "subtitle": "3 × 54 CELLS",
            "text": "Stores 9- or 18-trit words.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-setun-designers",
            "locator": "§3",
            "control": false
          },
          {
            "id": "r",
            "label": "Multiplier R",
            "subtitle": "18 TRITS",
            "text": "Holds a multiplication operand.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-setun-designers",
            "locator": "§3",
            "control": false
          },
          {
            "id": "s",
            "label": "Summarizer S",
            "subtitle": "18 TRITS",
            "text": "Accumulates arithmetic results.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-setun-designers",
            "locator": "§3",
            "control": false
          },
          {
            "id": "sign",
            "label": "Result sign omega",
            "subtitle": "ONE TRIT",
            "text": "Controls conditional transitions.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-setun-designers",
            "locator": "§3",
            "control": false
          },
          {
            "id": "interpret",
            "label": "IP / Poliz routines",
            "subtitle": "PROGRAM LAYER",
            "text": "Provide extended number operations.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-setun-designers",
            "locator": "§2.2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "c",
            "to": "memory",
            "type": "control",
            "source": "hist-setun-designers",
            "locator": "§3 command pointer",
            "label": ""
          },
          {
            "from": "memory",
            "to": "command",
            "type": "data",
            "source": "hist-setun-designers",
            "locator": "§3 command code",
            "label": ""
          },
          {
            "from": "command",
            "to": "f",
            "type": "control",
            "source": "hist-setun-designers",
            "locator": "§2.1 address modification",
            "label": ""
          },
          {
            "from": "f",
            "to": "memory",
            "type": "control",
            "source": "hist-setun-designers",
            "locator": "§3 index register",
            "label": ""
          },
          {
            "from": "drum",
            "to": "memory",
            "type": "data",
            "source": "hist-setun-designers",
            "locator": "§3 page exchange",
            "label": ""
          },
          {
            "from": "memory",
            "to": "drum",
            "type": "data",
            "source": "hist-setun-designers",
            "locator": "§3 page exchange",
            "label": ""
          },
          {
            "from": "memory",
            "to": "r",
            "type": "data",
            "source": "hist-setun-designers",
            "locator": "§3 word reads",
            "label": ""
          },
          {
            "from": "memory",
            "to": "s",
            "type": "data",
            "source": "hist-setun-designers",
            "locator": "§3 word reads",
            "label": ""
          },
          {
            "from": "r",
            "to": "s",
            "type": "data",
            "source": "hist-setun-designers",
            "locator": "§2.1 addition with products",
            "label": ""
          },
          {
            "from": "s",
            "to": "memory",
            "type": "data",
            "source": "hist-setun-designers",
            "locator": "§3 word recording",
            "label": ""
          },
          {
            "from": "s",
            "to": "sign",
            "type": "data",
            "source": "hist-setun-designers",
            "locator": "§3 result sign",
            "label": ""
          },
          {
            "from": "sign",
            "to": "c",
            "type": "control",
            "source": "hist-setun-designers",
            "locator": "§3 conditional transitions",
            "label": ""
          },
          {
            "from": "interpret",
            "to": "command",
            "type": "association",
            "source": "hist-setun-designers",
            "locator": "§2.2 interpretive systems",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Setun"
    },
    {
      "id": "queue-020",
      "name": "MIR-2 — symbolic engineering system",
      "organization": "Institute of Cybernetics, Ukrainian Academy of Sciences",
      "year": 1969,
      "yearLabel": "Serial production from 1969 in designer account",
      "kind": "Interactive engineering computer",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "microcoded"
      ],
      "substrates": [
        "transistor"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-mir-glushkov",
        "hist-mir-institute"
      ],
      "summary": "Analytic transformations are processor operations implemented through hierarchical microprograms, with interactive mathematical input.",
      "config": "MIR-2’s documented interpretation and symbolic-operation organization; physical memory capacities remain unspecified.",
      "gaps": [
        "No original MIR-2 hardware manual was retrieved; diagram is a sourced abstraction-layer map, not a cabinet interconnect.",
        "Numeric word length and memory size remain unasserted."
      ],
      "originalName": "MIR-2",
      "insight": "Where can a symbolic algebra operation live between language and circuitry?",
      "fields": {
        "state": {
          "value": "Numeric values and algebraic formulas",
          "source": "hist-mir-glushkov",
          "locator": "§2.4.3 pp. 53–54"
        },
        "compute": {
          "value": "Algebraic transforms, symbolic differentiation and integration",
          "source": "hist-mir-glushkov",
          "locator": "§2.4.3 p. 53"
        },
        "memory": {
          "value": "Working data plus hierarchical microprogram storage",
          "source": "hist-mir-glushkov",
          "locator": "§2.4.3 pp. 53–54"
        },
        "control": {
          "value": "Stepped organization shares microprogram fragments",
          "source": "hist-mir-glushkov",
          "locator": "§2.4.3; §1.9.2"
        },
        "io": {
          "value": "Display/light-pen dialogue",
          "source": "hist-mir-institute",
          "locator": "MIR-2 dialogue paragraph"
        },
        "software": {
          "value": "Analitik with structural interpretation",
          "source": "hist-mir-institute",
          "locator": "Final language paragraph"
        },
        "workload": {
          "value": "Engineering and analytic computation",
          "source": "hist-mir-glushkov",
          "locator": "§2.4.3"
        }
      },
      "diagram": {
        "title": "From mathematical dialogue to shared microprograms",
        "scope": "Documented layers and capabilities. Association edges identify implementation/interaction relationships rather than claimed wires.",
        "nodes": [
          {
            "id": "user",
            "label": "Engineer dialogue",
            "subtitle": "INTERACTIVE USE",
            "text": "Formulates mathematical tasks.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-mir-institute",
            "locator": "MIR-2 dialogue paragraph",
            "control": false
          },
          {
            "id": "language",
            "label": "Analitik",
            "subtitle": "INPUT LANGUAGE",
            "text": "Expresses mathematical operations.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-mir-institute",
            "locator": "Final language paragraph",
            "control": false
          },
          {
            "id": "interpret",
            "label": "Interpretation system",
            "subtitle": "LANGUAGE SUPPORT",
            "text": "Interprets the high-level representation.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-mir-institute",
            "locator": "Final language paragraph",
            "control": true
          },
          {
            "id": "formulas",
            "label": "Formula state",
            "subtitle": "SYMBOLIC DATA",
            "text": "Holds expressions to transform.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-mir-glushkov",
            "locator": "§2.4.3 p. 53",
            "control": false
          },
          {
            "id": "symbolic",
            "label": "Symbolic operations",
            "subtitle": "PROCESSOR FUNCTIONS",
            "text": "Transform, differentiate and integrate.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-mir-glushkov",
            "locator": "§2.4.3 p. 53",
            "control": false
          },
          {
            "id": "micro",
            "label": "Stepped microprograms",
            "subtitle": "CONTROL STORE",
            "text": "Implement complex operations.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-mir-glushkov",
            "locator": "§2.4.3 p. 53",
            "control": true
          },
          {
            "id": "shared",
            "label": "Common fragments",
            "subtitle": "REUSED CONTROL",
            "text": "Share lower-level microprogram sections.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-mir-glushkov",
            "locator": "§1.9.2 referenced by §2.4.3",
            "control": false
          },
          {
            "id": "working",
            "label": "Working storage",
            "subtitle": "PROGRAMS / DATA",
            "text": "Retains programs and intermediate state.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-mir-glushkov",
            "locator": "§2.4.3 p. 54",
            "control": false
          },
          {
            "id": "screen",
            "label": "Display / light pen",
            "subtitle": "DIALOGUE DEVICE",
            "text": "Supports direct user interaction.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-mir-institute",
            "locator": "MIR-2 dialogue paragraph",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "user",
            "to": "language",
            "type": "association",
            "source": "hist-mir-institute",
            "locator": "Final language paragraph",
            "label": ""
          },
          {
            "from": "language",
            "to": "interpret",
            "type": "data",
            "source": "hist-mir-institute",
            "locator": "Final language paragraph",
            "label": ""
          },
          {
            "from": "interpret",
            "to": "symbolic",
            "type": "association",
            "source": "hist-mir-glushkov",
            "locator": "§2.4.3 high-level processor operations",
            "label": ""
          },
          {
            "from": "formulas",
            "to": "symbolic",
            "type": "data",
            "source": "hist-mir-glushkov",
            "locator": "§2.4.3 algebraic transformations",
            "label": ""
          },
          {
            "from": "symbolic",
            "to": "formulas",
            "type": "data",
            "source": "hist-mir-glushkov",
            "locator": "§2.4.3 algebraic transformations",
            "label": ""
          },
          {
            "from": "micro",
            "to": "symbolic",
            "type": "control",
            "source": "hist-mir-glushkov",
            "locator": "§2.4.3 microprogram implementation",
            "label": ""
          },
          {
            "from": "shared",
            "to": "micro",
            "type": "association",
            "source": "hist-mir-glushkov",
            "locator": "§1.9.2 hierarchical sharing",
            "label": ""
          },
          {
            "from": "working",
            "to": "formulas",
            "type": "association",
            "source": "hist-mir-glushkov",
            "locator": "§2.4.3 intermediate data",
            "label": ""
          },
          {
            "from": "user",
            "to": "screen",
            "type": "association",
            "source": "hist-mir-institute",
            "locator": "MIR-2 dialogue paragraph",
            "label": ""
          },
          {
            "from": "screen",
            "to": "interpret",
            "type": "association",
            "source": "hist-mir-institute",
            "locator": "MIR-2 dialogue and language paragraphs",
            "label": ""
          }
        ]
      },
      "originalCandidate": "MIR-2"
    },
    {
      "id": "queue-021",
      "name": "CSIRAC — 1959 programming organization",
      "organization": "CSIRO / University of Melbourne",
      "year": 1959,
      "yearLabel": "August 1959 manual",
      "kind": "Research electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "transport"
      ],
      "substrates": [
        "vacuum-tube",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-csirac-manual"
      ],
      "summary": "Instructions select source and destination gates; arithmetic occurs as digit streams enter or leave particular registers.",
      "config": "Manual’s 1,024-word design organization and auxiliary-store interface; no count of installed optional drums is implied.",
      "gaps": [
        "Main-store size is the manual’s designed capacity; commissioning-era capacity is not substituted."
      ],
      "originalName": "CSIRAC",
      "insight": "How can choosing a destination also choose an arithmetic operation?",
      "fields": {
        "state": {
          "value": "20-bit serial pulse words",
          "source": "hist-csirac-manual",
          "locator": "§1.3"
        },
        "compute": {
          "value": "A/B/C, 16 D-registers and half-word H",
          "source": "hist-csirac-manual",
          "locator": "§1.4; §2"
        },
        "memory": {
          "value": "1,024-word designed main store; 1,024-word auxiliary stores",
          "source": "hist-csirac-manual",
          "locator": "§1.4"
        },
        "control": {
          "value": "S sequence and K interpreter; source/destination codes",
          "source": "hist-csirac-manual",
          "locator": "§§1.4–1.5"
        },
        "io": {
          "value": "Input register, output gates, tape and printer",
          "source": "hist-csirac-manual",
          "locator": "§1.4; Appendix 3"
        },
        "software": {
          "value": "Library routines; PK modifies next command",
          "source": "hist-csirac-manual",
          "locator": "§1.1; §3.6"
        },
        "workload": {
          "value": "General numerical and logical calculations",
          "source": "hist-csirac-manual",
          "locator": "§1.1"
        }
      },
      "diagram": {
        "title": "Source/destination selection triggers computation",
        "scope": "Functional transfer choices, not a modern bus/CPU decomposition.",
        "nodes": [
          {
            "id": "store",
            "label": "Main store M",
            "subtitle": "20-BIT WORDS",
            "text": "Provides numbers and stored commands.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-csirac-manual",
            "locator": "§1.4",
            "control": false
          },
          {
            "id": "s",
            "label": "Sequence S",
            "subtitle": "NEXT ADDRESS",
            "text": "Selects successive command cells.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-csirac-manual",
            "locator": "§1.4",
            "control": false
          },
          {
            "id": "k",
            "label": "Interpreter K / PK",
            "subtitle": "COMMAND STATE",
            "text": "Selects gates or modifies next order.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-csirac-manual",
            "locator": "§1.5; §3.6",
            "control": true
          },
          {
            "id": "abc",
            "label": "A / B / C",
            "subtitle": "ARITHMETIC STATE",
            "text": "XB forms products in A and B.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-csirac-manual",
            "locator": "§2.5; Appendix 3 XB",
            "control": false
          },
          {
            "id": "d",
            "label": "Sixteen D-registers",
            "subtitle": "INDEXABLE STATE",
            "text": "Support copy, add and subtract.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-csirac-manual",
            "locator": "§1.4; Appendix 3 D/PD/SD",
            "control": false
          },
          {
            "id": "h",
            "label": "Half-word H",
            "subtitle": "10 BITS",
            "text": "Selects upper or lower halves.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-csirac-manual",
            "locator": "§2.12",
            "control": false
          },
          {
            "id": "input",
            "label": "Input register I",
            "subtitle": "TAPE DATA",
            "text": "Transmits input and advances tape.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-csirac-manual",
            "locator": "Appendix 2 I",
            "control": false
          },
          {
            "id": "aux",
            "label": "Auxiliary stores",
            "subtitle": "MA / MB / MC / MD",
            "text": "Expose additional word sources/destinations.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-csirac-manual",
            "locator": "Appendices 2–3",
            "control": false
          },
          {
            "id": "output",
            "label": "Output destinations",
            "subtitle": "PRINTER / PUNCH / P",
            "text": "Receive codes or speaker pulse stream.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-csirac-manual",
            "locator": "Appendix 3 OT/OP/P",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "s",
            "to": "store",
            "type": "control",
            "source": "hist-csirac-manual",
            "locator": "§1.4",
            "label": ""
          },
          {
            "from": "store",
            "to": "k",
            "type": "data",
            "source": "hist-csirac-manual",
            "locator": "§1.4",
            "label": ""
          },
          {
            "from": "k",
            "to": "abc",
            "type": "control",
            "source": "hist-csirac-manual",
            "locator": "§1.5; Appendix 3",
            "label": ""
          },
          {
            "from": "store",
            "to": "abc",
            "type": "data",
            "source": "hist-csirac-manual",
            "locator": "§1.5 M A example",
            "label": ""
          },
          {
            "from": "abc",
            "to": "store",
            "type": "data",
            "source": "hist-csirac-manual",
            "locator": "§1.4",
            "label": ""
          },
          {
            "from": "abc",
            "to": "d",
            "type": "data",
            "source": "hist-csirac-manual",
            "locator": "Appendices 2–3",
            "label": ""
          },
          {
            "from": "d",
            "to": "abc",
            "type": "data",
            "source": "hist-csirac-manual",
            "locator": "Appendices 2–3",
            "label": ""
          },
          {
            "from": "h",
            "to": "abc",
            "type": "data",
            "source": "hist-csirac-manual",
            "locator": "§2.12",
            "label": ""
          },
          {
            "from": "input",
            "to": "h",
            "type": "data",
            "source": "hist-csirac-manual",
            "locator": "§4.11 I HL",
            "label": ""
          },
          {
            "from": "aux",
            "to": "abc",
            "type": "data",
            "source": "hist-csirac-manual",
            "locator": "Appendices 2–3",
            "label": ""
          },
          {
            "from": "abc",
            "to": "aux",
            "type": "data",
            "source": "hist-csirac-manual",
            "locator": "Appendices 2–3",
            "label": ""
          },
          {
            "from": "abc",
            "to": "output",
            "type": "data",
            "source": "hist-csirac-manual",
            "locator": "Appendix 3",
            "label": ""
          },
          {
            "from": "h",
            "to": "k",
            "type": "data",
            "source": "hist-csirac-manual",
            "locator": "§3.6 HU PK",
            "label": ""
          }
        ]
      },
      "originalCandidate": "CSIRAC"
    },
    {
      "id": "queue-022",
      "name": "Stantec ZEBRA — basic 1961 system",
      "organization": "Netherlands PTT / Standard Telephones and Cables",
      "year": 1961,
      "yearLabel": "1961 STC brochure configuration",
      "kind": "Commercial electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator"
      ],
      "substrates": [
        "vacuum-tube",
        "transistor",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-zebra-stc",
        "hist-zebra-designer"
      ],
      "summary": "Combinable function digits control two accumulator paths and a drum store; Simple Code provides an interpreted mathematical layer.",
      "config": "Basic drum system with one reader, punch and teleprinter; optional double I/O, ferrite and tape stores excluded.",
      "gaps": [
        "Brochure-level functional relationships; detailed gate circuitry is outside this dossier.",
        "Simple Code arithmetic is not represented as native hardware."
      ],
      "originalName": "ZEBRA",
      "insight": "Why should interpreted multiplication not be drawn as a hardware multiplier?",
      "fields": {
        "state": {
          "value": "33-bit serial binary words",
          "source": "hist-zebra-stc",
          "locator": "Brief Specification"
        },
        "compute": {
          "value": "Two accumulator/add-subtract/shift registers",
          "source": "hist-zebra-stc",
          "locator": "Brief Specification"
        },
        "memory": {
          "value": "8,192 drum words; 12 immediate-access registers",
          "source": "hist-zebra-stc",
          "locator": "Brief Specification"
        },
        "control": {
          "value": "15 combinable Normal Code function digits",
          "source": "hist-zebra-stc",
          "locator": "Normal Code"
        },
        "io": {
          "value": "Five-channel tape reader, punch and teleprinter",
          "source": "hist-zebra-stc",
          "locator": "Physical Description"
        },
        "software": {
          "value": "Normal Code and interpreted Simple Code",
          "source": "hist-zebra-stc",
          "locator": "Programming Features"
        },
        "workload": {
          "value": "Mathematical, research and industrial calculations",
          "source": "hist-zebra-stc",
          "locator": "Foreword"
        }
      },
      "diagram": {
        "title": "Combinable functions and an interpreted arithmetic layer",
        "scope": "Basic-system functional relationships. Modifier edges describe permitted instruction modification, not dedicated wires.",
        "nodes": [
          {
            "id": "drum",
            "label": "Drum store",
            "subtitle": "8,192 WORDS",
            "text": "Retains orders, routines and numbers.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-zebra-stc",
            "locator": "Brief Specification",
            "control": false
          },
          {
            "id": "normal",
            "label": "Normal Code control",
            "subtitle": "15 FUNCTION DIGITS",
            "text": "Combines elementary operations.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-zebra-stc",
            "locator": "Normal Code",
            "control": true
          },
          {
            "id": "fast",
            "label": "Immediate stores",
            "subtitle": "12 WORDS",
            "text": "Provide rapidly reusable state.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-zebra-stc",
            "locator": "Brief Specification",
            "control": false
          },
          {
            "id": "a",
            "label": "Accumulator A",
            "subtitle": "ADD / SUBTRACT / SHIFT",
            "text": "One arithmetic register path.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-zebra-stc",
            "locator": "Brief Specification",
            "control": false
          },
          {
            "id": "b",
            "label": "Accumulator B",
            "subtitle": "ADD / SUBTRACT / SHIFT",
            "text": "Second arithmetic register path.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-zebra-stc",
            "locator": "Brief Specification",
            "control": false
          },
          {
            "id": "modify",
            "label": "Instruction modification",
            "subtitle": "SELECTABLE SOURCES",
            "text": "Uses registers, accumulators or input.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-zebra-stc",
            "locator": "Normal Code",
            "control": false
          },
          {
            "id": "read",
            "label": "Paper-tape reader",
            "subtitle": "INPUT CHANNEL",
            "text": "Introduces program and numeric codes.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-zebra-stc",
            "locator": "Physical Description",
            "control": false
          },
          {
            "id": "out",
            "label": "Punch / teleprinter",
            "subtitle": "OUTPUT",
            "text": "Records computation results.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-zebra-stc",
            "locator": "Physical Description",
            "control": false
          },
          {
            "id": "simple",
            "label": "Simple Code interpreter",
            "subtitle": "PROGRAM LAYER",
            "text": "Provides decimal floating arithmetic.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-zebra-stc",
            "locator": "Simple Code",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "drum",
            "to": "normal",
            "type": "data",
            "source": "hist-zebra-stc",
            "locator": "Normal Code",
            "label": ""
          },
          {
            "from": "normal",
            "to": "a",
            "type": "control",
            "source": "hist-zebra-stc",
            "locator": "Normal Code",
            "label": ""
          },
          {
            "from": "normal",
            "to": "b",
            "type": "control",
            "source": "hist-zebra-stc",
            "locator": "Normal Code",
            "label": ""
          },
          {
            "from": "drum",
            "to": "a",
            "type": "data",
            "source": "hist-zebra-stc",
            "locator": "Normal Code address description",
            "label": ""
          },
          {
            "from": "drum",
            "to": "b",
            "type": "data",
            "source": "hist-zebra-stc",
            "locator": "Normal Code address description",
            "label": ""
          },
          {
            "from": "fast",
            "to": "modify",
            "type": "data",
            "source": "hist-zebra-stc",
            "locator": "Normal Code",
            "label": ""
          },
          {
            "from": "a",
            "to": "modify",
            "type": "data",
            "source": "hist-zebra-stc",
            "locator": "Normal Code",
            "label": ""
          },
          {
            "from": "b",
            "to": "modify",
            "type": "data",
            "source": "hist-zebra-stc",
            "locator": "Normal Code",
            "label": ""
          },
          {
            "from": "read",
            "to": "modify",
            "type": "data",
            "source": "hist-zebra-stc",
            "locator": "Normal Code",
            "label": ""
          },
          {
            "from": "modify",
            "to": "normal",
            "type": "data",
            "source": "hist-zebra-stc",
            "locator": "Normal Code",
            "label": ""
          },
          {
            "from": "read",
            "to": "drum",
            "type": "association",
            "source": "hist-zebra-stc",
            "locator": "Physical Description; Input",
            "label": ""
          },
          {
            "from": "normal",
            "to": "out",
            "type": "control",
            "source": "hist-zebra-stc",
            "locator": "Programming Features; Output",
            "label": ""
          },
          {
            "from": "simple",
            "to": "normal",
            "type": "association",
            "source": "hist-zebra-stc",
            "locator": "Simple Code interpreter",
            "label": ""
          },
          {
            "from": "simple",
            "to": "drum",
            "type": "association",
            "source": "hist-zebra-stc",
            "locator": "Simple Code storage program",
            "label": ""
          }
        ]
      },
      "originalCandidate": "ZEBRA"
    },
    {
      "id": "queue-023",
      "name": "LGP-30 — April 1957 system",
      "organization": "Librascope / Royal McBee",
      "year": 1957,
      "yearLabel": "April 1957 programming manual",
      "kind": "Commercial electronic system",
      "status": "dossier",
      "track": "early",
      "trackName": "Early digital & mechanical",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator"
      ],
      "substrates": [
        "vacuum-tube",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-lgp30-manual"
      ],
      "summary": "The drum holds both general storage and three short recirculating registers; tape stop codes coordinate input with execution.",
      "config": "Standard 4,096-word drum machine in the April 1957 manual.",
      "gaps": [
        "Spacer position is not an additional data bit.",
        "The manual’s introductory desk-calculator example is not hardware."
      ],
      "originalName": "LGP-30",
      "insight": "How can a rotating surface serve as both memory and fast registers?",
      "fields": {
        "state": {
          "value": "30 number bits, sign, and unused spacer",
          "source": "hist-lgp30-manual",
          "locator": "p. 10"
        },
        "compute": {
          "value": "Serial fixed-point arithmetic; recirculating accumulator",
          "source": "hist-lgp30-manual",
          "locator": "p. 8; specifications"
        },
        "memory": {
          "value": "64 tracks × 64 sectors; three short register tracks",
          "source": "hist-lgp30-manual",
          "locator": "p. 8"
        },
        "control": {
          "value": "Counter and instruction registers; four execution phases",
          "source": "hist-lgp30-manual",
          "locator": "pp. 8, 12"
        },
        "io": {
          "value": "Paper tape and electric typewriter",
          "source": "hist-lgp30-manual",
          "locator": "pp. 33–34"
        },
        "software": {
          "value": "16 orders; software conversion/floating point",
          "source": "hist-lgp30-manual",
          "locator": "pp. 28, 32"
        },
        "workload": {
          "value": "General numerical calculations",
          "source": "hist-lgp30-manual",
          "locator": "p. 7; specifications"
        }
      },
      "diagram": {
        "title": "Recirculating registers and the four-phase drum cycle",
        "scope": "Search, transfer, operand search and completion are control phases. Print codes come from instruction track bits.",
        "nodes": [
          {
            "id": "counter",
            "label": "Counter register",
            "subtitle": "RECIRCULATING TRACK",
            "text": "Retains the next order location.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-lgp30-manual",
            "locator": "pp. 8, 12",
            "control": false
          },
          {
            "id": "search",
            "label": "Search / transfer",
            "subtitle": "CONTROL PHASES",
            "text": "Waits for addressed drum sectors.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-lgp30-manual",
            "locator": "p. 12",
            "control": true
          },
          {
            "id": "instruction",
            "label": "Instruction register",
            "subtitle": "RECIRCULATING TRACK",
            "text": "Retains order and operand address.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-lgp30-manual",
            "locator": "pp. 8, 12",
            "control": false
          },
          {
            "id": "drum",
            "label": "General drum storage",
            "subtitle": "4,096 WORDS",
            "text": "Retains instructions and operands.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-lgp30-manual",
            "locator": "p. 8",
            "control": false
          },
          {
            "id": "arith",
            "label": "Serial arithmetic",
            "subtitle": "EXECUTION PHASE",
            "text": "Operates on selected operand.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-lgp30-manual",
            "locator": "p. 12; specifications",
            "control": false
          },
          {
            "id": "acc",
            "label": "Accumulator",
            "subtitle": "RECIRCULATING TRACK",
            "text": "Retains serial numeric results.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-lgp30-manual",
            "locator": "pp. 8, 12",
            "control": false
          },
          {
            "id": "tape",
            "label": "Tape reader",
            "subtitle": "CODE / STOP SIGNAL",
            "text": "Supplies input characters and restart.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-lgp30-manual",
            "locator": "p. 34",
            "control": false
          },
          {
            "id": "type",
            "label": "Electric typewriter",
            "subtitle": "PRINT FUNCTIONS",
            "text": "Executes six-bit track-field codes.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-lgp30-manual",
            "locator": "p. 33",
            "control": false
          },
          {
            "id": "resume",
            "label": "Input completion",
            "subtitle": "RESTART CONTROL",
            "text": "Stops reading and resumes orders.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-lgp30-manual",
            "locator": "p. 34",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "counter",
            "to": "search",
            "type": "control",
            "source": "hist-lgp30-manual",
            "locator": "p. 12 first phase",
            "label": ""
          },
          {
            "from": "search",
            "to": "drum",
            "type": "control",
            "source": "hist-lgp30-manual",
            "locator": "p. 12",
            "label": ""
          },
          {
            "from": "drum",
            "to": "instruction",
            "type": "data",
            "source": "hist-lgp30-manual",
            "locator": "p. 12 second phase",
            "label": ""
          },
          {
            "from": "instruction",
            "to": "search",
            "type": "control",
            "source": "hist-lgp30-manual",
            "locator": "p. 12 third phase",
            "label": ""
          },
          {
            "from": "drum",
            "to": "arith",
            "type": "data",
            "source": "hist-lgp30-manual",
            "locator": "p. 12 fourth phase",
            "label": ""
          },
          {
            "from": "acc",
            "to": "arith",
            "type": "data",
            "source": "hist-lgp30-manual",
            "locator": "p. 12",
            "label": ""
          },
          {
            "from": "arith",
            "to": "acc",
            "type": "data",
            "source": "hist-lgp30-manual",
            "locator": "p. 12",
            "label": ""
          },
          {
            "from": "acc",
            "to": "drum",
            "type": "data",
            "source": "hist-lgp30-manual",
            "locator": "p. 14 hold instruction",
            "label": ""
          },
          {
            "from": "instruction",
            "to": "type",
            "type": "control",
            "source": "hist-lgp30-manual",
            "locator": "p. 33 print order",
            "label": ""
          },
          {
            "from": "instruction",
            "to": "tape",
            "type": "control",
            "source": "hist-lgp30-manual",
            "locator": "p. 34 p0000/i0000",
            "label": ""
          },
          {
            "from": "tape",
            "to": "acc",
            "type": "data",
            "source": "hist-lgp30-manual",
            "locator": "p. 34 input",
            "label": ""
          },
          {
            "from": "tape",
            "to": "resume",
            "type": "control",
            "source": "hist-lgp30-manual",
            "locator": "p. 34 stop code",
            "label": ""
          },
          {
            "from": "resume",
            "to": "counter",
            "type": "control",
            "source": "hist-lgp30-manual",
            "locator": "p. 34 next instruction",
            "label": ""
          }
        ]
      },
      "originalCandidate": "LGP-30"
    },
    {
      "id": "queue-024",
      "name": "IBM 7030 Stretch — documented system organization",
      "organization": "IBM",
      "year": 1962,
      "yearLabel": "1962 designer monograph",
      "kind": "Scientific electronic system",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "pipelined"
      ],
      "substrates": [
        "transistor",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-stretch-designers"
      ],
      "summary": "Instruction indexing, operand look-ahead, arithmetic and autonomous exchange overlap, with stores committed in the required program order.",
      "config": "Chapter 3 modular 7030 organization; no claim that all optional memory/disk units were installed together.",
      "gaps": [
        "Module count is installation-dependent.",
        "Diagram uses Chapter 3’s functional boundaries rather than detailed transistor circuits."
      ],
      "originalName": "IBM 7030 Stretch",
      "insight": "Why must anticipatory operand fetch remain distinct from permanent state changes?",
      "fields": {
        "state": {
          "value": "64 data bits plus eight memory check bits",
          "source": "hist-stretch-designers",
          "locator": "§3.2"
        },
        "compute": {
          "value": "Parallel floating and serial variable-field arithmetic",
          "source": "hist-stretch-designers",
          "locator": "§3.11"
        },
        "memory": {
          "value": "16,384-word core modules; separate index core",
          "source": "hist-stretch-designers",
          "locator": "§§3.2–3.3"
        },
        "control": {
          "value": "Instruction unit and buffered look-ahead with interlocks",
          "source": "hist-stretch-designers",
          "locator": "§§3.8–3.10"
        },
        "io": {
          "value": "Autonomous exchange; optional separate disk synchronizer",
          "source": "hist-stretch-designers",
          "locator": "§§3.5–3.6"
        },
        "software": {
          "value": "Mixed full/half instructions and protected execution",
          "source": "hist-stretch-designers",
          "locator": "§3.8"
        },
        "workload": {
          "value": "Large numerical and data-processing problems",
          "source": "hist-stretch-designers",
          "locator": "§§3.6–3.11"
        }
      },
      "diagram": {
        "title": "Look-ahead overlaps access while preserving ordered stores",
        "scope": "Memory bus arbitrates requests from several autonomous roles. Serial and parallel arithmetic share registers.",
        "nodes": [
          {
            "id": "index",
            "label": "Index core",
            "subtitle": "16 INDEX WORDS",
            "text": "Supplies fast modification state.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-stretch-designers",
            "locator": "§3.3",
            "control": false
          },
          {
            "id": "instruction",
            "label": "Instruction / indexing unit",
            "subtitle": "ADDRESS ARITHMETIC",
            "text": "Fetches, indexes and branches.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-stretch-designers",
            "locator": "§§3.1, 3.9",
            "control": true
          },
          {
            "id": "look",
            "label": "Look-ahead",
            "subtitle": "BUFFERED OPERANDS",
            "text": "Fetches ahead; commits ordered stores.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-stretch-designers",
            "locator": "§3.10",
            "control": true
          },
          {
            "id": "memory",
            "label": "Core-memory modules",
            "subtitle": "64 + 8 CHECK BITS",
            "text": "Can overlap independent accesses.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-stretch-designers",
            "locator": "§3.2",
            "control": false
          },
          {
            "id": "bus",
            "label": "Memory bus unit",
            "subtitle": "TRAFFIC COORDINATION",
            "text": "Arbitrates memory traffic.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-stretch-designers",
            "locator": "§3.1",
            "control": false
          },
          {
            "id": "arith",
            "label": "Parallel / serial arithmetic",
            "subtitle": "SHARED A/B/C/D/S",
            "text": "Executes numeric and field operations.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-stretch-designers",
            "locator": "§3.11",
            "control": false
          },
          {
            "id": "exchange",
            "label": "I/O exchange",
            "subtitle": "AUTONOMOUS CHANNELS",
            "text": "Assembles/disassembles 64-bit words.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-stretch-designers",
            "locator": "§3.5",
            "control": false
          },
          {
            "id": "peripheral",
            "label": "Cards / tape / printer",
            "subtitle": "EXTERNAL DATA",
            "text": "Exchange-controlled equipment.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-stretch-designers",
            "locator": "§3.5",
            "control": false
          },
          {
            "id": "disk",
            "label": "Optional disk synchronizer",
            "subtitle": "SEPARATE CHANNEL",
            "text": "Moves disk data independently.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-stretch-designers",
            "locator": "§3.6",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "index",
            "to": "instruction",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§3.3",
            "label": ""
          },
          {
            "from": "instruction",
            "to": "look",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§3.10",
            "label": ""
          },
          {
            "from": "instruction",
            "to": "bus",
            "type": "control",
            "source": "hist-stretch-designers",
            "locator": "§§3.1, 3.10",
            "label": ""
          },
          {
            "from": "look",
            "to": "bus",
            "type": "control",
            "source": "hist-stretch-designers",
            "locator": "§3.10",
            "label": ""
          },
          {
            "from": "bus",
            "to": "memory",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§3.1 Figure 3.1",
            "label": ""
          },
          {
            "from": "memory",
            "to": "bus",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§3.1 Figure 3.1",
            "label": ""
          },
          {
            "from": "bus",
            "to": "look",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§3.10 operands",
            "label": ""
          },
          {
            "from": "look",
            "to": "arith",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§3.10",
            "label": ""
          },
          {
            "from": "arith",
            "to": "look",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§3.10 all results stored by look-ahead",
            "label": ""
          },
          {
            "from": "look",
            "to": "bus",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§3.10 ordered storage",
            "label": ""
          },
          {
            "from": "peripheral",
            "to": "exchange",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§3.5",
            "label": ""
          },
          {
            "from": "exchange",
            "to": "peripheral",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§3.5",
            "label": ""
          },
          {
            "from": "exchange",
            "to": "bus",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§§3.1, 3.5",
            "label": ""
          },
          {
            "from": "bus",
            "to": "exchange",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§§3.1, 3.5",
            "label": ""
          },
          {
            "from": "disk",
            "to": "bus",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§3.6",
            "label": ""
          },
          {
            "from": "bus",
            "to": "disk",
            "type": "data",
            "source": "hist-stretch-designers",
            "locator": "§3.6",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IBM 7030 Stretch"
    },
    {
      "id": "queue-025",
      "name": "IBM 7090 — 1960 channel organization",
      "organization": "IBM",
      "year": 1960,
      "yearLabel": "August 1960 manual revision",
      "kind": "Commercial scientific computer",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator"
      ],
      "substrates": [
        "transistor",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-ibm7090-manual"
      ],
      "summary": "Independent 7607 channels assemble peripheral words while the 7606 multiplexor switches their traffic into core storage.",
      "config": "7090-specific 32,768-word system; channel and attached-device counts remain configuration-dependent.",
      "gaps": [
        "709 data synchronizers, drum and CRT features are not assigned to the 7090."
      ],
      "originalName": "IBM 7090",
      "insight": "How does a channel continue an input transfer after the CPU resumes computing?",
      "fields": {
        "state": {
          "value": "36-bit words; 38-position accumulator",
          "source": "hist-ibm7090-manual",
          "locator": "pp. 12–13"
        },
        "compute": {
          "value": "Accumulator, MQ, storage register and adder",
          "source": "hist-ibm7090-manual",
          "locator": "pp. 12–14"
        },
        "memory": {
          "value": "32,768 core words",
          "source": "hist-ibm7090-manual",
          "locator": "p. 42 comparison table"
        },
        "control": {
          "value": "Stored instructions with indexing and indirection",
          "source": "hist-ibm7090-manual",
          "locator": "pp. 15–20"
        },
        "io": {
          "value": "7606 multiplexor and one to eight 7607 channels",
          "source": "hist-ibm7090-manual",
          "locator": "pp. 35–37"
        },
        "software": {
          "value": "SHARE system and FORTRAN",
          "source": "hist-ibm7090-manual",
          "locator": "pp. 44–46"
        },
        "workload": {
          "value": "Scientific and business data processing",
          "source": "hist-ibm7090-manual",
          "locator": "Introduction"
        }
      },
      "diagram": {
        "title": "Independent channels share storage with accumulator arithmetic",
        "scope": "CPU register paths and the 7090-specific I/O switching path; no fixed peripheral count assumed.",
        "nodes": [
          {
            "id": "core",
            "label": "Core storage",
            "subtitle": "32,768 WORDS",
            "text": "Retains instructions and operands.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ibm7090-manual",
            "locator": "p. 42",
            "control": false
          },
          {
            "id": "sr",
            "label": "Storage register",
            "subtitle": "TRANSFER STATE",
            "text": "Stages fetched instructions and numbers.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ibm7090-manual",
            "locator": "pp. 13–14",
            "control": false
          },
          {
            "id": "control",
            "label": "Instruction / address control",
            "subtitle": "INDEX / INDIRECT",
            "text": "Selects effective operand addresses.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ibm7090-manual",
            "locator": "pp. 13–20",
            "control": true
          },
          {
            "id": "adder",
            "label": "Adder",
            "subtitle": "ARITHMETIC PATH",
            "text": "Combines stored and accumulated values.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ibm7090-manual",
            "locator": "p. 14",
            "control": false
          },
          {
            "id": "acmq",
            "label": "Accumulator / MQ",
            "subtitle": "RESULT / PRODUCT STATE",
            "text": "Supports arithmetic and shifts.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ibm7090-manual",
            "locator": "pp. 12–13",
            "control": false
          },
          {
            "id": "mux",
            "label": "7606 multiplexor",
            "subtitle": "36-BIT SWITCHING",
            "text": "Routes every channel storage transfer.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ibm7090-manual",
            "locator": "p. 35",
            "control": false
          },
          {
            "id": "channel",
            "label": "7607 data channels",
            "subtitle": "AUTONOMOUS TRANSFERS",
            "text": "Assemble words independently of CPU.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ibm7090-manual",
            "locator": "p. 36",
            "control": false
          },
          {
            "id": "tape",
            "label": "729 tape units",
            "subtitle": "READ / WRITE",
            "text": "Attach through data channels.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ibm7090-manual",
            "locator": "p. 37",
            "control": false
          },
          {
            "id": "cards",
            "label": "Card / printer devices",
            "subtitle": "PERIPHERAL DATA",
            "text": "Share channel connections.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ibm7090-manual",
            "locator": "pp. 37, 39–41",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "core",
            "to": "sr",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "pp. 13–14",
            "label": ""
          },
          {
            "from": "sr",
            "to": "control",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "pp. 13–14",
            "label": ""
          },
          {
            "from": "control",
            "to": "core",
            "type": "control",
            "source": "hist-ibm7090-manual",
            "locator": "pp. 13–14",
            "label": ""
          },
          {
            "from": "sr",
            "to": "adder",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "p. 14",
            "label": ""
          },
          {
            "from": "acmq",
            "to": "adder",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "p. 14",
            "label": ""
          },
          {
            "from": "adder",
            "to": "acmq",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "p. 14",
            "label": ""
          },
          {
            "from": "acmq",
            "to": "core",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "pp. 16–17 store instructions",
            "label": ""
          },
          {
            "from": "control",
            "to": "channel",
            "type": "control",
            "source": "hist-ibm7090-manual",
            "locator": "p. 36 starts I/O",
            "label": ""
          },
          {
            "from": "channel",
            "to": "mux",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "p. 35 Figure 76",
            "label": ""
          },
          {
            "from": "mux",
            "to": "channel",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "p. 35 Figure 76",
            "label": ""
          },
          {
            "from": "mux",
            "to": "core",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "pp. 35–36",
            "label": ""
          },
          {
            "from": "core",
            "to": "mux",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "pp. 35–36",
            "label": ""
          },
          {
            "from": "tape",
            "to": "channel",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "p. 37",
            "label": ""
          },
          {
            "from": "channel",
            "to": "tape",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "p. 37",
            "label": ""
          },
          {
            "from": "cards",
            "to": "channel",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "pp. 37, 39–41",
            "label": ""
          },
          {
            "from": "channel",
            "to": "cards",
            "type": "data",
            "source": "hist-ibm7090-manual",
            "locator": "pp. 37, 39–41",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IBM 7090"
    },
    {
      "id": "queue-026",
      "name": "IBM System/360 Model 30 — C30",
      "organization": "IBM",
      "year": 1967,
      "yearLabel": "June 1967 engineering manual",
      "kind": "Commercial mainframe",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "microcoded",
        "register-memory"
      ],
      "substrates": [
        "integrated",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-36030-engineering"
      ],
      "summary": "Read-only control sequences byte-wide arithmetic and core transfers while architectural registers reside in auxiliary core storage.",
      "config": "C30 with 8,192-byte main store; optional decimal/floating features and selector-channel count are not silently fixed.",
      "gaps": [
        "Capacitor ROS implementation detail is not reproduced.",
        "Diagram labels selector channels as optional."
      ],
      "originalName": "IBM System/360 Model 30",
      "insight": "How can a 32-bit architectural register be implemented through byte-wide core accesses?",
      "fields": {
        "state": {
          "value": "Byte-wide internal data; multi-byte architectural values",
          "source": "hist-36030-engineering",
          "locator": "p. 1-4"
        },
        "compute": {
          "value": "A/B-fed eight-bit ALU",
          "source": "hist-36030-engineering",
          "locator": "p. 1-3"
        },
        "memory": {
          "value": "8,192 main bytes; auxiliary local and MPX core",
          "source": "hist-36030-engineering",
          "locator": "p. 1-4"
        },
        "control": {
          "value": "Read-only storage microprogram",
          "source": "hist-36030-engineering",
          "locator": "p. 1-3"
        },
        "io": {
          "value": "Multiplexor and optional selector channels; control units",
          "source": "hist-36030-engineering",
          "locator": "p. 1-2"
        },
        "software": {
          "value": "Stored System/360 instructions interpreted by ROS",
          "source": "hist-36030-engineering",
          "locator": "pp. 1-1–1-3"
        },
        "workload": {
          "value": "General arithmetic, logic and data formatting",
          "source": "hist-36030-engineering",
          "locator": "p. 1-1"
        }
      },
      "diagram": {
        "title": "Byte-wide execution under read-only control",
        "scope": "Architectural register width and internal transfer width are distinct.",
        "nodes": [
          {
            "id": "main",
            "label": "C30 main core",
            "subtitle": "8,192 BYTES",
            "text": "Retains programs and data.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-36030-engineering",
            "locator": "p. 1-4",
            "control": false
          },
          {
            "id": "local",
            "label": "Auxiliary local core",
            "subtitle": "ARCHITECTURAL REGISTERS",
            "text": "Holds general/floating register areas.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-36030-engineering",
            "locator": "p. 1-4",
            "control": false
          },
          {
            "id": "ros",
            "label": "Read-only control",
            "subtitle": "MICROPROGRAM",
            "text": "Selects registers and ALU functions.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-36030-engineering",
            "locator": "p. 1-3",
            "control": true
          },
          {
            "id": "a",
            "label": "A input register",
            "subtitle": "ONE BYTE",
            "text": "Supplies one ALU operand.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-36030-engineering",
            "locator": "p. 1-3",
            "control": false
          },
          {
            "id": "alu",
            "label": "Arithmetic / logic",
            "subtitle": "BYTE-WIDE",
            "text": "Adds or performs logic functions.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-36030-engineering",
            "locator": "p. 1-3",
            "control": false
          },
          {
            "id": "b",
            "label": "B input register",
            "subtitle": "ONE BYTE",
            "text": "Supplies the second operand.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-36030-engineering",
            "locator": "p. 1-3",
            "control": false
          },
          {
            "id": "mpx",
            "label": "Multiplexor channel",
            "subtitle": "UNIT CONTROL WORDS",
            "text": "Uses auxiliary MPX core state.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-36030-engineering",
            "locator": "pp. 1-2, 1-4",
            "control": false
          },
          {
            "id": "selector",
            "label": "Optional selectors",
            "subtitle": "BLOCK TRANSFERS",
            "text": "Control higher-rate I/O traffic.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-36030-engineering",
            "locator": "p. 1-2 Figure 1-2",
            "control": false
          },
          {
            "id": "devices",
            "label": "I/O control units",
            "subtitle": "STANDARD INTERFACE",
            "text": "Attach peripheral devices.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-36030-engineering",
            "locator": "p. 1-2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "main",
            "to": "a",
            "type": "data",
            "source": "hist-36030-engineering",
            "locator": "pp. 1-3–1-4; CPU data flow",
            "label": ""
          },
          {
            "from": "local",
            "to": "b",
            "type": "data",
            "source": "hist-36030-engineering",
            "locator": "pp. 1-3–1-4; CPU data flow",
            "label": ""
          },
          {
            "from": "a",
            "to": "alu",
            "type": "data",
            "source": "hist-36030-engineering",
            "locator": "p. 1-3",
            "label": ""
          },
          {
            "from": "b",
            "to": "alu",
            "type": "data",
            "source": "hist-36030-engineering",
            "locator": "p. 1-3",
            "label": ""
          },
          {
            "from": "ros",
            "to": "a",
            "type": "control",
            "source": "hist-36030-engineering",
            "locator": "p. 1-3",
            "label": ""
          },
          {
            "from": "ros",
            "to": "b",
            "type": "control",
            "source": "hist-36030-engineering",
            "locator": "p. 1-3",
            "label": ""
          },
          {
            "from": "ros",
            "to": "alu",
            "type": "control",
            "source": "hist-36030-engineering",
            "locator": "p. 1-3",
            "label": ""
          },
          {
            "from": "ros",
            "to": "main",
            "type": "control",
            "source": "hist-36030-engineering",
            "locator": "p. 1-3",
            "label": ""
          },
          {
            "from": "ros",
            "to": "local",
            "type": "control",
            "source": "hist-36030-engineering",
            "locator": "pp. 1-3–1-4",
            "label": ""
          },
          {
            "from": "mpx",
            "to": "main",
            "type": "data",
            "source": "hist-36030-engineering",
            "locator": "p. 1-2 Figure 1-2",
            "label": ""
          },
          {
            "from": "selector",
            "to": "main",
            "type": "data",
            "source": "hist-36030-engineering",
            "locator": "p. 1-2 Figure 1-2",
            "label": ""
          },
          {
            "from": "devices",
            "to": "mpx",
            "type": "data",
            "source": "hist-36030-engineering",
            "locator": "p. 1-2",
            "label": ""
          },
          {
            "from": "mpx",
            "to": "devices",
            "type": "data",
            "source": "hist-36030-engineering",
            "locator": "p. 1-2",
            "label": ""
          },
          {
            "from": "devices",
            "to": "selector",
            "type": "data",
            "source": "hist-36030-engineering",
            "locator": "p. 1-2",
            "label": ""
          },
          {
            "from": "selector",
            "to": "devices",
            "type": "data",
            "source": "hist-36030-engineering",
            "locator": "p. 1-2",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IBM System/360 Model 30"
    },
    {
      "id": "queue-027",
      "name": "IBM System/360 Model 67-1 — 24-bit DAT",
      "organization": "IBM",
      "year": 1972,
      "yearLabel": "February 1972 functional specification",
      "kind": "Time-sharing mainframe",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "register-memory"
      ],
      "substrates": [
        "integrated",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-36067-functional"
      ],
      "summary": "Hardware translates segmented virtual addresses through page tables or associative entries; channels retain real-storage addressing.",
      "config": "Single-processor 2067-1 with standard 24-bit translation. Optional 32-bit DAT and duplex controllers excluded.",
      "gaps": [
        "No installed core-unit count is asserted.",
        "Duplex partition controls are excluded from the single-processor diagram."
      ],
      "originalName": "IBM System/360 Model 67",
      "insight": "Why are channel addresses outside the CPU’s virtual-address translation path?",
      "fields": {
        "state": {
          "value": "24-bit virtual addresses; 4,096-byte pages",
          "source": "hist-36067-functional",
          "locator": "pp. 6–8"
        },
        "compute": {
          "value": "2067 processor arithmetic and logical functions",
          "source": "hist-36067-functional",
          "locator": "p. 10"
        },
        "memory": {
          "value": "2365 Model 12 core storage units",
          "source": "hist-36067-functional",
          "locator": "System Components"
        },
        "control": {
          "value": "PSW-gated DAT with segment/page lookup and associative reuse",
          "source": "hist-36067-functional",
          "locator": "pp. 8, 11–15"
        },
        "io": {
          "value": "Up to seven directly attached channels on 67-1",
          "source": "hist-36067-functional",
          "locator": "p. 10"
        },
        "software": {
          "value": "OS/360 mode or extended TSS/360 mode",
          "source": "hist-36067-functional",
          "locator": "p. 8"
        },
        "workload": {
          "value": "Time-shared programs with scattered resident pages",
          "source": "hist-36067-functional",
          "locator": "pp. 6–8"
        }
      },
      "diagram": {
        "title": "Translation cache, table walk and real-address channel access",
        "scope": "The graph follows CPU address production. Tables reside in processor storage; channels bypass DAT.",
        "nodes": [
          {
            "id": "virtual",
            "label": "CPU virtual address",
            "subtitle": "SEGMENT / PAGE / BYTE",
            "text": "Identifies a program location.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-36067-functional",
            "locator": "pp. 11–14",
            "control": false
          },
          {
            "id": "psw",
            "label": "PSW translation mode",
            "subtitle": "DAT ENABLE",
            "text": "Enables hardware translation.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-36067-functional",
            "locator": "p. 8",
            "control": true
          },
          {
            "id": "assoc",
            "label": "Associative entries",
            "subtitle": "RECENT TRANSLATIONS",
            "text": "Reuse a prior page mapping.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-36067-functional",
            "locator": "pp. 13–15",
            "control": false
          },
          {
            "id": "segment",
            "label": "Segment-table lookup",
            "subtitle": "PAGE-TABLE ORIGIN",
            "text": "Locates the relevant page table.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-36067-functional",
            "locator": "Figures 5–6",
            "control": false
          },
          {
            "id": "page",
            "label": "Page-table lookup",
            "subtitle": "REAL PAGE ADDRESS",
            "text": "Obtains the physical page mapping.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-36067-functional",
            "locator": "Figures 5–6",
            "control": false
          },
          {
            "id": "prefix",
            "label": "Prefixing",
            "subtitle": "LOW-ADDRESS REMAP",
            "text": "Applies after translation.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-36067-functional",
            "locator": "pp. 8, 13",
            "control": false
          },
          {
            "id": "bcu",
            "label": "Bus control unit",
            "subtitle": "STORAGE REQUESTS",
            "text": "Arbitrates CPU and channel access.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-36067-functional",
            "locator": "p. 10",
            "control": true
          },
          {
            "id": "core",
            "label": "Processor storage",
            "subtitle": "REAL ADDRESSES",
            "text": "Holds tables, instructions and data.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-36067-functional",
            "locator": "pp. 10–14",
            "control": false
          },
          {
            "id": "channel",
            "label": "Direct channels",
            "subtitle": "REAL ADDRESS I/O",
            "text": "Request storage without DAT.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-36067-functional",
            "locator": "pp. 8, 10",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "psw",
            "to": "virtual",
            "type": "control",
            "source": "hist-36067-functional",
            "locator": "p. 8",
            "label": ""
          },
          {
            "from": "virtual",
            "to": "assoc",
            "type": "data",
            "source": "hist-36067-functional",
            "locator": "pp. 13–15",
            "label": ""
          },
          {
            "from": "virtual",
            "to": "segment",
            "type": "data",
            "source": "hist-36067-functional",
            "locator": "Figures 5–6",
            "label": ""
          },
          {
            "from": "segment",
            "to": "page",
            "type": "data",
            "source": "hist-36067-functional",
            "locator": "Figures 5–6",
            "label": ""
          },
          {
            "from": "page",
            "to": "assoc",
            "type": "data",
            "source": "hist-36067-functional",
            "locator": "pp. 13–15 loaded translation",
            "label": ""
          },
          {
            "from": "assoc",
            "to": "prefix",
            "type": "data",
            "source": "hist-36067-functional",
            "locator": "p. 13",
            "label": ""
          },
          {
            "from": "page",
            "to": "prefix",
            "type": "data",
            "source": "hist-36067-functional",
            "locator": "p. 13",
            "label": ""
          },
          {
            "from": "prefix",
            "to": "bcu",
            "type": "data",
            "source": "hist-36067-functional",
            "locator": "pp. 10, 13",
            "label": ""
          },
          {
            "from": "bcu",
            "to": "core",
            "type": "control",
            "source": "hist-36067-functional",
            "locator": "p. 10",
            "label": ""
          },
          {
            "from": "core",
            "to": "segment",
            "type": "data",
            "source": "hist-36067-functional",
            "locator": "Figures 5–6 table lookup",
            "label": ""
          },
          {
            "from": "core",
            "to": "page",
            "type": "data",
            "source": "hist-36067-functional",
            "locator": "Figures 5–6 table lookup",
            "label": ""
          },
          {
            "from": "channel",
            "to": "bcu",
            "type": "control",
            "source": "hist-36067-functional",
            "locator": "p. 10",
            "label": ""
          },
          {
            "from": "channel",
            "to": "core",
            "type": "data",
            "source": "hist-36067-functional",
            "locator": "p. 8 bypass translation",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IBM System/360 Model 67"
    },
    {
      "id": "queue-028",
      "name": "IBM System/360 Model 91",
      "organization": "IBM",
      "year": 1967,
      "yearLabel": "January 1967 designer paper",
      "kind": "Scientific mainframe",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "pipelined",
        "superscalar"
      ],
      "substrates": [
        "integrated",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-36091-designers"
      ],
      "summary": "Interleaved storage and several kinds of queues feed separated execution units; instruction history can retain whole loops.",
      "config": "Designer paper’s 91 organization; this diagram focuses on instruction handling and buffering rather than all floating-point circuitry.",
      "gaps": [
        "Out-of-order floating execution is supported by this paper; detailed reservation-station circuits require the companion floating-point paper."
      ],
      "insight": "Which buffers separate instruction issue, operand arrival and result storage?",
      "fields": {
        "state": {
          "value": "64-bit doubleword instruction buffers; 32/64-bit operand buffers",
          "source": "hist-36091-designers",
          "locator": "p. 11 Figure 5 footnote"
        },
        "compute": {
          "value": "Independent fixed and floating execution; concurrent floating units",
          "source": "hist-36091-designers",
          "locator": "pp. 10–11"
        },
        "memory": {
          "value": "Interleaved core modules and instruction-loop history",
          "source": "hist-36091-designers",
          "locator": "pp. 10–11"
        },
        "control": {
          "value": "Instruction unit, dependency interlocks and buffered issue",
          "source": "hist-36091-designers",
          "locator": "pp. 11–13"
        },
        "io": {
          "value": "I/O handling coordinated with instruction/control facilities",
          "source": "hist-36091-designers",
          "locator": "Instruction handling, I/O section"
        },
        "software": {
          "value": "System/360 instruction stream",
          "source": "hist-36091-designers",
          "locator": "Introduction"
        },
        "workload": {
          "value": "High-throughput scientific arithmetic",
          "source": "hist-36091-designers",
          "locator": "Introduction; CPU organization"
        }
      },
      "diagram": {
        "title": "Queues isolate instruction supply from execution and stores",
        "scope": "Figure 5’s boundaries and buffer roles; branch-address buffers are grouped with instruction supply.",
        "nodes": [
          {
            "id": "storage",
            "label": "Interleaved storage",
            "subtitle": "INDEPENDENT MODULES",
            "text": "Overlaps memory cycles.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-36091-designers",
            "locator": "p. 10",
            "control": false
          },
          {
            "id": "fetch",
            "label": "Instruction / branch buffers",
            "subtitle": "EIGHT DOUBLEWORDS",
            "text": "Retain fetched words and loops.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-36091-designers",
            "locator": "p. 11 Figure 5",
            "control": false
          },
          {
            "id": "issue",
            "label": "Instruction unit",
            "subtitle": "DECODE / ISSUE",
            "text": "Forms operand addresses and operations.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-36091-designers",
            "locator": "pp. 10–11",
            "control": true
          },
          {
            "id": "fixbuf",
            "label": "Fixed operand / op buffers",
            "subtitle": "SEPARATE QUEUES",
            "text": "Wait for data and execution.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "control": false
          },
          {
            "id": "fixed",
            "label": "Fixed-point execution",
            "subtitle": "SERIAL WITHIN UNIT",
            "text": "Executes fixed and string operations.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-36091-designers",
            "locator": "pp. 10–11",
            "control": false
          },
          {
            "id": "floatbuf",
            "label": "Floating operand / op buffers",
            "subtitle": "SEPARATE QUEUES",
            "text": "Decouple fetch from floating work.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "control": false
          },
          {
            "id": "floating",
            "label": "Floating execution",
            "subtitle": "CONCURRENT UNITS",
            "text": "Executes independent operations out of order.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-36091-designers",
            "locator": "p. 11",
            "control": false
          },
          {
            "id": "stores",
            "label": "Store data / address buffers",
            "subtitle": "THREE EACH",
            "text": "Queue writeback information.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-36091-designers",
            "locator": "Figure 5; p. 11 footnote",
            "control": false
          },
          {
            "id": "conflict",
            "label": "Conflict addresses",
            "subtitle": "FOUR ENTRIES",
            "text": "Track conflicting storage references.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-36091-designers",
            "locator": "Figure 5; storage interlocks",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "storage",
            "to": "fetch",
            "type": "data",
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "fetch",
            "to": "issue",
            "type": "data",
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "issue",
            "to": "fixbuf",
            "type": "control",
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "issue",
            "to": "floatbuf",
            "type": "control",
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "storage",
            "to": "fixbuf",
            "type": "data",
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "storage",
            "to": "floatbuf",
            "type": "data",
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "fixbuf",
            "to": "fixed",
            "type": "data",
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "floatbuf",
            "to": "floating",
            "type": "data",
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "fixed",
            "to": "stores",
            "type": "data",
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "floating",
            "to": "stores",
            "type": "data",
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "stores",
            "to": "storage",
            "type": "data",
            "source": "hist-36091-designers",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "issue",
            "to": "conflict",
            "type": "control",
            "source": "hist-36091-designers",
            "locator": "Figure 5; storage interlocks",
            "label": ""
          },
          {
            "from": "conflict",
            "to": "storage",
            "type": "control",
            "source": "hist-36091-designers",
            "locator": "storage interlocks",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IBM System/360 Model 91"
    },
    {
      "id": "queue-029",
      "name": "IBM System/370 Model 168-1 — 3168 J",
      "organization": "IBM",
      "year": 1976,
      "yearLabel": "1976 manual configuration",
      "kind": "Virtual-memory mainframe",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "register-memory"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-370168-functional"
      ],
      "summary": "A TLB and high-speed buffer reduce CPU access costs while channel stores invalidate cached data when needed.",
      "config": "3168 Model 1 J: 1,024K processor-storage bytes and standard 8K buffer; no attached processor.",
      "gaps": [
        "Model 3’s 32K cache and optional APU are excluded.",
        "Buffer expansion and installed channel counts remain optional."
      ],
      "originalName": "IBM System/370",
      "insight": "Why does a channel write need to invalidate a CPU buffer block?",
      "fields": {
        "state": {
          "value": "Byte-addressed instructions/data; 16 general and four floating registers",
          "source": "hist-370168-functional",
          "locator": "pp. 10–11"
        },
        "compute": {
          "value": "Instruction and execution units with local registers",
          "source": "hist-370168-functional",
          "locator": "Figure 5"
        },
        "memory": {
          "value": "1 MiB four-way interleaved store; 8 KiB buffer",
          "source": "hist-370168-functional",
          "locator": "pp. 11–13"
        },
        "control": {
          "value": "DAT translator and 128-entry TLB",
          "source": "hist-370168-functional",
          "locator": "p. 14"
        },
        "io": {
          "value": "Channel requests through storage control",
          "source": "hist-370168-functional",
          "locator": "Figure 5; p. 13"
        },
        "software": {
          "value": "System/370 operating/control modes",
          "source": "hist-370168-functional",
          "locator": "Basic System Description"
        },
        "workload": {
          "value": "General multiprogrammed processing",
          "source": "hist-370168-functional",
          "locator": "Introduction"
        }
      },
      "diagram": {
        "title": "Translation and cache lookup with I/O invalidation",
        "scope": "CPU and channel access obey different cache paths in the selected 3168-1 configuration.",
        "nodes": [
          {
            "id": "instruction",
            "label": "Instruction unit",
            "subtitle": "DECODE / ADDRESS",
            "text": "Produces logical references.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-370168-functional",
            "locator": "Figure 5; p. 16",
            "control": false
          },
          {
            "id": "tlb",
            "label": "Translation lookaside",
            "subtitle": "128 MAPPINGS",
            "text": "Retains logical-to-real pairs.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-370168-functional",
            "locator": "p. 14",
            "control": false
          },
          {
            "id": "translator",
            "label": "DAT translator",
            "subtitle": "TABLE WALK",
            "text": "Builds missing page translations.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-370168-functional",
            "locator": "p. 14",
            "control": true
          },
          {
            "id": "buffer",
            "label": "High-speed buffer",
            "subtitle": "8 KiB / 32-BYTE BLOCKS",
            "text": "Retains recently used instructions/data.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-370168-functional",
            "locator": "pp. 13–14",
            "control": false
          },
          {
            "id": "control",
            "label": "Processor storage control",
            "subtitle": "ARBITRATION",
            "text": "Coordinates core and channel access.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-370168-functional",
            "locator": "Figure 5",
            "control": true
          },
          {
            "id": "store",
            "label": "Processor storage",
            "subtitle": "1 MiB / 4-WAY",
            "text": "Services independent eight-byte accesses.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-370168-functional",
            "locator": "pp. 11–12",
            "control": false
          },
          {
            "id": "exec",
            "label": "Execution unit",
            "subtitle": "LOCAL REGISTERS",
            "text": "Operates on fetched data.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-370168-functional",
            "locator": "Figure 5",
            "control": false
          },
          {
            "id": "channels",
            "label": "I/O channels",
            "subtitle": "DIRECT STORE REQUESTS",
            "text": "Fetch from processor storage.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-370168-functional",
            "locator": "p. 13",
            "control": false
          },
          {
            "id": "invalidate",
            "label": "Buffer invalidation",
            "subtitle": "CHANNEL STORE CHECK",
            "text": "Invalidates a cached matching block.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-370168-functional",
            "locator": "p. 13",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "instruction",
            "to": "tlb",
            "type": "data",
            "source": "hist-370168-functional",
            "locator": "p. 14",
            "label": ""
          },
          {
            "from": "instruction",
            "to": "buffer",
            "type": "control",
            "source": "hist-370168-functional",
            "locator": "p. 14",
            "label": ""
          },
          {
            "from": "tlb",
            "to": "buffer",
            "type": "data",
            "source": "hist-370168-functional",
            "locator": "p. 14 real address comparison",
            "label": ""
          },
          {
            "from": "translator",
            "to": "tlb",
            "type": "data",
            "source": "hist-370168-functional",
            "locator": "p. 14",
            "label": ""
          },
          {
            "from": "translator",
            "to": "control",
            "type": "control",
            "source": "hist-370168-functional",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "control",
            "to": "store",
            "type": "data",
            "source": "hist-370168-functional",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "store",
            "to": "control",
            "type": "data",
            "source": "hist-370168-functional",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "control",
            "to": "buffer",
            "type": "data",
            "source": "hist-370168-functional",
            "locator": "p. 13 block load",
            "label": ""
          },
          {
            "from": "buffer",
            "to": "exec",
            "type": "data",
            "source": "hist-370168-functional",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "channels",
            "to": "control",
            "type": "data",
            "source": "hist-370168-functional",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "control",
            "to": "channels",
            "type": "data",
            "source": "hist-370168-functional",
            "locator": "Figure 5",
            "label": ""
          },
          {
            "from": "channels",
            "to": "invalidate",
            "type": "control",
            "source": "hist-370168-functional",
            "locator": "p. 13",
            "label": ""
          },
          {
            "from": "invalidate",
            "to": "buffer",
            "type": "control",
            "source": "hist-370168-functional",
            "locator": "p. 13",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IBM System/370"
    },
    {
      "id": "queue-030",
      "name": "IBM z16 A01 — CPC drawer organization",
      "organization": "IBM",
      "year": 2023,
      "yearLabel": "April 2023 Redbook specification",
      "kind": "Enterprise mainframe",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "superscalar",
        "smp",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-z16-redbook"
      ],
      "summary": "Telum chips form a coherent drawer in which physical L2 arrays also serve logical victim-cache roles across cores and chips.",
      "config": "A01 drawer-level organization with four DCMs/eight Telum chips; physical cores are not all customer-characterizable CPs.",
      "gaps": [
        "This is an A01 drawer configuration, not the different A02/AGZ topology.",
        "Licensed processor count and memory population vary by order."
      ],
      "originalName": "IBM z16",
      "insight": "Why must the virtual L3/L4 capacities not be added as separate SRAM arrays?",
      "fields": {
        "state": {
          "value": "z/Architecture cores; 64 physical cores per drawer",
          "source": "hist-z16-redbook",
          "locator": "§2.3"
        },
        "compute": {
          "value": "Out-of-order superscalar PU cores",
          "source": "hist-z16-redbook",
          "locator": "§2.3.2"
        },
        "memory": {
          "value": "Physical L1/L2; logical victim L3/L4; drawer DIMMs",
          "source": "hist-z16-redbook",
          "locator": "§§2.3–2.3.2"
        },
        "control": {
          "value": "PR/SM memory-coherent SMP; retry and PU sparing",
          "source": "hist-z16-redbook",
          "locator": "§2.3.2"
        },
        "io": {
          "value": "PCIe fanouts connect separate I/O drawers",
          "source": "hist-z16-redbook",
          "locator": "§2.3"
        },
        "software": {
          "value": "PR/SM-managed partitioned system organization",
          "source": "hist-z16-redbook",
          "locator": "§2.3 Figure 2-4 discussion"
        },
        "workload": {
          "value": "Enterprise numerical, transactional and data processing",
          "source": "hist-z16-redbook",
          "locator": "Chapter 1"
        }
      },
      "diagram": {
        "title": "Physical cache arrays and logical shared-victim roles",
        "scope": "L3/L4 are logical uses of distributed physical L2 capacity. Association edges identify those roles rather than additional SRAM chips.",
        "nodes": [
          {
            "id": "cores",
            "label": "Telum PU cores",
            "subtitle": "8 PER CHIP",
            "text": "Decode and execute out of order.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-z16-redbook",
            "locator": "§2.3.2",
            "control": false
          },
          {
            "id": "l1",
            "label": "Private L1 I / D",
            "subtitle": "128 KiB EACH",
            "text": "Separate instruction and data caches.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-z16-redbook",
            "locator": "§2.3.2",
            "control": false
          },
          {
            "id": "l2",
            "label": "Physical L2 arrays",
            "subtitle": "32 MiB PER CORE",
            "text": "Provide nearby semi-private storage.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-z16-redbook",
            "locator": "§2.3.2",
            "control": false
          },
          {
            "id": "l3",
            "label": "Virtual L3 role",
            "subtitle": "256 MiB PER CHIP",
            "text": "Shares victim capacity across L2s.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-z16-redbook",
            "locator": "§2.3.2 Figure 2-5",
            "control": false
          },
          {
            "id": "links",
            "label": "M-Bus / X-Bus",
            "subtitle": "CHIP / DRAWER LINKS",
            "text": "Connect paired chips and drawer DCMs.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-z16-redbook",
            "locator": "§2.3",
            "control": false
          },
          {
            "id": "l4",
            "label": "Virtual L4 role",
            "subtitle": "2 GiB PER DRAWER",
            "text": "Uses remote chip victim capacity.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-z16-redbook",
            "locator": "§2.3.2 Figure 2-5",
            "control": false
          },
          {
            "id": "dram",
            "label": "Drawer DIMMs",
            "subtitle": "MAIN STORAGE",
            "text": "Provide system memory capacity.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-z16-redbook",
            "locator": "§2.3",
            "control": false
          },
          {
            "id": "io",
            "label": "PCIe fanout / I/O drawers",
            "subtitle": "CHANNEL ATTACHMENT",
            "text": "Connect peripheral adapters.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-z16-redbook",
            "locator": "§2.3",
            "control": false
          },
          {
            "id": "prsm",
            "label": "PR/SM / recovery",
            "subtitle": "SYSTEM CONTROL",
            "text": "Manages coherent SMP and sparing.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-z16-redbook",
            "locator": "§2.3.2",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "cores",
            "to": "l1",
            "type": "data",
            "source": "hist-z16-redbook",
            "locator": "§2.3.2",
            "label": ""
          },
          {
            "from": "l1",
            "to": "l2",
            "type": "data",
            "source": "hist-z16-redbook",
            "locator": "§2.3.2 Figure 2-5",
            "label": ""
          },
          {
            "from": "l2",
            "to": "l3",
            "type": "association",
            "source": "hist-z16-redbook",
            "locator": "§2.3.2 logical construction",
            "label": ""
          },
          {
            "from": "l3",
            "to": "l4",
            "type": "association",
            "source": "hist-z16-redbook",
            "locator": "§2.3.2 remote virtual L3s",
            "label": ""
          },
          {
            "from": "l2",
            "to": "links",
            "type": "data",
            "source": "hist-z16-redbook",
            "locator": "Figure 2-5",
            "label": ""
          },
          {
            "from": "links",
            "to": "l2",
            "type": "data",
            "source": "hist-z16-redbook",
            "locator": "Figure 2-5",
            "label": ""
          },
          {
            "from": "links",
            "to": "l4",
            "type": "association",
            "source": "hist-z16-redbook",
            "locator": "Figure 2-5",
            "label": ""
          },
          {
            "from": "cores",
            "to": "dram",
            "type": "association",
            "source": "hist-z16-redbook",
            "locator": "§2.3 drawer components",
            "label": ""
          },
          {
            "from": "cores",
            "to": "io",
            "type": "association",
            "source": "hist-z16-redbook",
            "locator": "§2.3 drawer fanouts",
            "label": ""
          },
          {
            "from": "prsm",
            "to": "cores",
            "type": "control",
            "source": "hist-z16-redbook",
            "locator": "§2.3.2 PR/SM and sparing",
            "label": ""
          },
          {
            "from": "prsm",
            "to": "links",
            "type": "association",
            "source": "hist-z16-redbook",
            "locator": "§2.3 Figure 2-4 coherent SMP",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IBM z16"
    },
    {
      "id": "queue-031",
      "name": "ICL 1904A — 2044/1",
      "organization": "ICL",
      "year": 1972,
      "yearLabel": "September 1972 training issue",
      "kind": "Commercial mainframe",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "register-memory"
      ],
      "substrates": [
        "integrated",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-icl1904a-training"
      ],
      "summary": "Eight hardware accumulators overlay low program addresses; datum/limit checks protect relocated programs while autonomous peripheral control accesses store.",
      "config": "2044/1 with 32K words, as sheet 1.4; larger SEU configurations are excluded.",
      "gaps": [
        "Training drawing shows an FPU, but no FPU performance or optional installation claim is added.",
        "1900-family coverage is limited to the named 1904A configuration."
      ],
      "originalName": "ICL 1900 series",
      "insight": "How does Executive make relative program addresses coexist in one physical store?",
      "fields": {
        "state": {
          "value": "24-bit words and eight hardware accumulators",
          "source": "hist-icl1904a-training",
          "locator": "sheet 1.7"
        },
        "compute": {
          "value": "24-bit parallel mill; double-length work registers",
          "source": "hist-icl1904a-training",
          "locator": "sheet 1.7"
        },
        "memory": {
          "value": "32K-word core configuration",
          "source": "hist-icl1904a-training",
          "locator": "sheet 1.4"
        },
        "control": {
          "value": "C/N/F registers with datum and limit boundaries",
          "source": "hist-icl1904a-training",
          "locator": "sheets 1.2, 1.7"
        },
        "io": {
          "value": "Autonomous fast channels; CPU slow interface and console",
          "source": "hist-icl1904a-training",
          "locator": "sheet 1.1"
        },
        "software": {
          "value": "Executive schedules relocated programs and saves accumulator state",
          "source": "hist-icl1904a-training",
          "locator": "sheets 1.2, 1.7"
        },
        "workload": {
          "value": "Concurrent resident application programs",
          "source": "hist-icl1904a-training",
          "locator": "sheet 1.2"
        }
      },
      "diagram": {
        "title": "Accumulator overlay, boundary checks and autonomous I/O",
        "scope": "Selected data-flow paths from sheets 1.1, 1.6 and 1.7; schematic is redrawn without original artwork.",
        "nodes": [
          {
            "id": "store",
            "label": "Core store",
            "subtitle": "32K WORDS",
            "text": "Retains programs and Executive.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-icl1904a-training",
            "locator": "sheets 1.2, 1.4",
            "control": false
          },
          {
            "id": "b",
            "label": "B store buffer",
            "subtitle": "24 BITS",
            "text": "Stages all CPU store data.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.7",
            "control": false
          },
          {
            "id": "acc",
            "label": "Hardware accumulators",
            "subtitle": "8 × 24 BITS",
            "text": "Overlay relative locations 0–7.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.7",
            "control": false
          },
          {
            "id": "mill",
            "label": "Parallel mill",
            "subtitle": "24-BIT ADDER",
            "text": "Combines working-register data.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-icl1904a-training",
            "locator": "sheets 1.6–1.7",
            "control": false
          },
          {
            "id": "control",
            "label": "C / N / F state",
            "subtitle": "ADDRESS / FUNCTION",
            "text": "Retains instruction and operand controls.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.7",
            "control": true
          },
          {
            "id": "bounds",
            "label": "Datum / limit",
            "subtitle": "D AND L REGISTERS",
            "text": "Constrain the current program area.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-icl1904a-training",
            "locator": "sheets 1.2, 1.7",
            "control": true
          },
          {
            "id": "pac",
            "label": "Peripheral autonomous control",
            "subtitle": "FAST DATA CHANNELS",
            "text": "Moves data independently of mill.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.1",
            "control": false
          },
          {
            "id": "peripherals",
            "label": "Fast / slow peripherals",
            "subtitle": "EXTERNAL DATA",
            "text": "Use PAC or CPU slow interface.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.1",
            "control": false
          },
          {
            "id": "executive",
            "label": "Executive",
            "subtitle": "RESIDENT CONTROL PROGRAM",
            "text": "Switches program and accumulator context.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-icl1904a-training",
            "locator": "sheets 1.2, 1.7",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "store",
            "to": "b",
            "type": "data",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.7",
            "label": ""
          },
          {
            "from": "b",
            "to": "store",
            "type": "data",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.7",
            "label": ""
          },
          {
            "from": "b",
            "to": "mill",
            "type": "data",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.6",
            "label": ""
          },
          {
            "from": "acc",
            "to": "mill",
            "type": "data",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.6",
            "label": ""
          },
          {
            "from": "mill",
            "to": "b",
            "type": "data",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.6",
            "label": ""
          },
          {
            "from": "mill",
            "to": "acc",
            "type": "data",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.6",
            "label": ""
          },
          {
            "from": "control",
            "to": "store",
            "type": "control",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.7",
            "label": ""
          },
          {
            "from": "bounds",
            "to": "store",
            "type": "control",
            "source": "hist-icl1904a-training",
            "locator": "sheets 1.2, 1.7",
            "label": ""
          },
          {
            "from": "executive",
            "to": "bounds",
            "type": "association",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.2 program layout",
            "label": ""
          },
          {
            "from": "executive",
            "to": "acc",
            "type": "association",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.7 context save/restore",
            "label": ""
          },
          {
            "from": "pac",
            "to": "store",
            "type": "data",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.1",
            "label": ""
          },
          {
            "from": "store",
            "to": "pac",
            "type": "data",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.1",
            "label": ""
          },
          {
            "from": "peripherals",
            "to": "pac",
            "type": "data",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.1",
            "label": ""
          },
          {
            "from": "pac",
            "to": "peripherals",
            "type": "data",
            "source": "hist-icl1904a-training",
            "locator": "sheet 1.1",
            "label": ""
          }
        ]
      },
      "originalCandidate": "ICL 1900"
    },
    {
      "id": "queue-032",
      "name": "Burroughs B5000 — Processor A system",
      "organization": "Burroughs",
      "year": 1963,
      "yearLabel": "1963 Revision A operational manual",
      "kind": "Language-oriented mainframe",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "stack"
      ],
      "substrates": [
        "transistor",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-b5000-operational"
      ],
      "summary": "Syllables select operations while PRT descriptors supply addresses, bounds and presence; register-stack tops extend a memory stack.",
      "config": "B5280 Processor A organization with modular core and I/O exchanges; optional Processor B is excluded.",
      "gaps": [
        "Core-module and peripheral counts are installation-dependent.",
        "B5500 and B6500 mechanisms are not assigned retrospectively."
      ],
      "originalName": "Burroughs B5000",
      "insight": "Why can instruction syllables remain separate from address/control descriptors?",
      "fields": {
        "state": {
          "value": "48-bit information words; four 12-bit syllables",
          "source": "hist-b5000-operational",
          "locator": "§2 pp. 2-3–2-5"
        },
        "compute": {
          "value": "Word-mode stack arithmetic; character-mode string operations",
          "source": "hist-b5000-operational",
          "locator": "§2"
        },
        "memory": {
          "value": "4,096-word core modules with exchange access",
          "source": "hist-b5000-operational",
          "locator": "§1 p. 1-2"
        },
        "control": {
          "value": "P/C/L/T program registers; descriptor checks and interrupts",
          "source": "hist-b5000-operational",
          "locator": "§2 pp. 2-4, 2-6–2-10"
        },
        "io": {
          "value": "Up to four I/O channels and separate I/O exchange",
          "source": "hist-b5000-operational",
          "locator": "§1"
        },
        "software": {
          "value": "MCP with ALGOL/COBOL-oriented compilation",
          "source": "hist-b5000-operational",
          "locator": "§1 Introduction"
        },
        "workload": {
          "value": "Numeric and character-data processing",
          "source": "hist-b5000-operational",
          "locator": "§2 modes"
        }
      },
      "diagram": {
        "title": "Syllables, descriptors and two register stack positions",
        "scope": "PRT, program and stack nodes are logical regions of shared core; exchange nodes denote actual system boundaries.",
        "nodes": [
          {
            "id": "memory",
            "label": "Core modules",
            "subtitle": "49 BITS WITH PARITY",
            "text": "Provide modular common storage.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-b5000-operational",
            "locator": "§1 p. 1-2",
            "control": false
          },
          {
            "id": "program",
            "label": "P / C / L / T",
            "subtitle": "SYLLABLE SEQUENCING",
            "text": "Fetch and select program syllables.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-b5000-operational",
            "locator": "§2 p. 2-6",
            "control": false
          },
          {
            "id": "prt",
            "label": "Program Reference Table",
            "subtitle": "DESCRIPTORS",
            "text": "Supplies address, bounds and presence.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-b5000-operational",
            "locator": "§2 pp. 2-3–2-4",
            "control": false
          },
          {
            "id": "a",
            "label": "A register",
            "subtitle": "STACK TOP / SOURCE",
            "text": "Retains an operand or source word.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-b5000-operational",
            "locator": "§2 p. 2-6",
            "control": false
          },
          {
            "id": "b",
            "label": "B register",
            "subtitle": "NEXT / DESTINATION",
            "text": "Retains operand, result or destination.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-b5000-operational",
            "locator": "§2 p. 2-7",
            "control": false
          },
          {
            "id": "stack",
            "label": "Memory stack",
            "subtitle": "TEMPORARY / CONTROL",
            "text": "Extends register-held state.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-b5000-operational",
            "locator": "§3 stack push-down",
            "control": false
          },
          {
            "id": "arithmetic",
            "label": "Parallel / serial adders",
            "subtitle": "NUMERIC / CHARACTER",
            "text": "Process word or character operands.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-b5000-operational",
            "locator": "§2 pp. 2-11–2-12",
            "control": false
          },
          {
            "id": "exchange",
            "label": "Memory exchange",
            "subtitle": "PARALLEL MODULE ACCESS",
            "text": "Connects processor and I/O accesses.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-b5000-operational",
            "locator": "§1 p. 1-1",
            "control": false
          },
          {
            "id": "io",
            "label": "I/O channels / exchange",
            "subtitle": "PERIPHERAL ASSIGNMENT",
            "text": "Connect devices without fixed pairing.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-b5000-operational",
            "locator": "§1 pp. 1-1–1-2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "memory",
            "to": "program",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§2 p. 2-6",
            "label": ""
          },
          {
            "from": "program",
            "to": "prt",
            "type": "control",
            "source": "hist-b5000-operational",
            "locator": "§2 syllable-descriptor operation",
            "label": ""
          },
          {
            "from": "prt",
            "to": "memory",
            "type": "control",
            "source": "hist-b5000-operational",
            "locator": "§2 p. 2-4",
            "label": ""
          },
          {
            "from": "memory",
            "to": "a",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§2 p. 2-6",
            "label": ""
          },
          {
            "from": "a",
            "to": "memory",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§2 p. 2-6",
            "label": ""
          },
          {
            "from": "memory",
            "to": "b",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§2 p. 2-7",
            "label": ""
          },
          {
            "from": "b",
            "to": "memory",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§2 p. 2-7",
            "label": ""
          },
          {
            "from": "a",
            "to": "arithmetic",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§2 parallel arithmetic",
            "label": ""
          },
          {
            "from": "b",
            "to": "arithmetic",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§2 parallel arithmetic",
            "label": ""
          },
          {
            "from": "arithmetic",
            "to": "b",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§2 p. 2-7",
            "label": ""
          },
          {
            "from": "b",
            "to": "stack",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§3 stack push-down",
            "label": ""
          },
          {
            "from": "stack",
            "to": "b",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§3 stack push-up",
            "label": ""
          },
          {
            "from": "exchange",
            "to": "memory",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§1 p. 1-1",
            "label": ""
          },
          {
            "from": "io",
            "to": "exchange",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§1 pp. 1-1–1-2",
            "label": ""
          },
          {
            "from": "exchange",
            "to": "io",
            "type": "data",
            "source": "hist-b5000-operational",
            "locator": "§1 pp. 1-1–1-2",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Burroughs B5000"
    },
    {
      "id": "queue-033",
      "name": "Burroughs B6500 — B6503 stack organization",
      "organization": "Burroughs",
      "year": 1969,
      "yearLabel": "September 1969 reference manual",
      "kind": "Language-oriented mainframe",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "stack"
      ],
      "substrates": [
        "integrated",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-b6500-reference"
      ],
      "summary": "Operand-oriented top registers extend each job’s protected memory stack; presence faults invoke MCP to bring disk-resident arrays into core.",
      "config": "B6503 processor variant; other processor clocks and maximum dual-system equipment are not combined into a fictional installation.",
      "gaps": [
        "Physical module counts remain installation-dependent.",
        "B6504/B6506 clock and memory timings are separate variants."
      ],
      "originalName": "Burroughs B6500",
      "insight": "Why do four stack registers hold two operands rather than always four?",
      "fields": {
        "state": {
          "value": "48 information bits, three control bits and parity",
          "source": "hist-b6500-reference",
          "locator": "§1 p. 1-17"
        },
        "compute": {
          "value": "Parallel stack processor; 2.5 MHz B6503",
          "source": "hist-b6500-reference",
          "locator": "§1 p. 1-12"
        },
        "memory": {
          "value": "Shared modular core plus disk backing",
          "source": "hist-b6500-reference",
          "locator": "§1 pp. 1-10, 1-17"
        },
        "control": {
          "value": "A/X/B/Y stack extension; S and stack bounds",
          "source": "hist-b6500-reference",
          "locator": "§3 pp. 3-1–3-2"
        },
        "io": {
          "value": "Independent I/O multiplexor and peripheral controls",
          "source": "hist-b6500-reference",
          "locator": "§1 pp. 1-9, 1-17"
        },
        "software": {
          "value": "MCP; protected descriptors and procedure state",
          "source": "hist-b6500-reference",
          "locator": "§1; §3 pp. 3-3–3-4"
        },
        "workload": {
          "value": "Multiprogrammed numeric/string processing",
          "source": "hist-b6500-reference",
          "locator": "§1"
        }
      },
      "diagram": {
        "title": "Operand stacks, descriptor faults and independent I/O",
        "scope": "Logical job stack and arrays share core; MCP handles absent descriptors through disk transfers.",
        "nodes": [
          {
            "id": "top",
            "label": "A/X and B/Y",
            "subtitle": "TWO OPERAND POSITIONS",
            "text": "Extend stack for single/double precision.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-b6500-reference",
            "locator": "§3 pp. 3-1–3-3",
            "control": false
          },
          {
            "id": "stack",
            "label": "Job stack in core",
            "subtitle": "TEMPORARY / HISTORY",
            "text": "Spills and refills top operands.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-b6500-reference",
            "locator": "§3 pp. 3-1–3-2",
            "control": false
          },
          {
            "id": "bounds",
            "label": "S / BOSR / LOSR",
            "subtitle": "STACK ADDRESS / BOUNDS",
            "text": "Check stack movement limits.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-b6500-reference",
            "locator": "§3 p. 3-2",
            "control": true
          },
          {
            "id": "descriptor",
            "label": "Data / segment descriptors",
            "subtitle": "PRESENCE / LENGTH",
            "text": "Locate and bound external arrays.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-b6500-reference",
            "locator": "§3 pp. 3-3–3-4",
            "control": false
          },
          {
            "id": "arrays",
            "label": "Core arrays / code",
            "subtitle": "RESIDENT OBJECTS",
            "text": "Supply referenced data and programs.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-b6500-reference",
            "locator": "§3 p. 3-3",
            "control": false
          },
          {
            "id": "mcp",
            "label": "Master Control Program",
            "subtitle": "PRESENCE FAULT HANDLER",
            "text": "Loads missing objects and resumes jobs.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-b6500-reference",
            "locator": "§3 p. 3-4",
            "control": true
          },
          {
            "id": "disk",
            "label": "Backing disk file",
            "subtitle": "NONRESIDENT OBJECTS",
            "text": "Retains absent arrays and segments.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-b6500-reference",
            "locator": "§1 p. 1-17; §3 p. 3-4",
            "control": false
          },
          {
            "id": "multiplexor",
            "label": "I/O multiplexor",
            "subtitle": "AUTONOMOUS TRANSFERS",
            "text": "Executes processor-initiated I/O.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-b6500-reference",
            "locator": "§1 p. 1-17",
            "control": false
          },
          {
            "id": "devices",
            "label": "Peripheral controls / units",
            "subtitle": "INDEPENDENT ACCESS",
            "text": "Connect disk, tape and other devices.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-b6500-reference",
            "locator": "§1 Figure 1-4",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "top",
            "to": "stack",
            "type": "data",
            "source": "hist-b6500-reference",
            "locator": "§3 p. 3-2",
            "label": ""
          },
          {
            "from": "stack",
            "to": "top",
            "type": "data",
            "source": "hist-b6500-reference",
            "locator": "§3 p. 3-2",
            "label": ""
          },
          {
            "from": "bounds",
            "to": "stack",
            "type": "control",
            "source": "hist-b6500-reference",
            "locator": "§3 p. 3-2",
            "label": ""
          },
          {
            "from": "descriptor",
            "to": "arrays",
            "type": "control",
            "source": "hist-b6500-reference",
            "locator": "§3 p. 3-3",
            "label": ""
          },
          {
            "from": "arrays",
            "to": "top",
            "type": "data",
            "source": "hist-b6500-reference",
            "locator": "§3 p. 3-3",
            "label": ""
          },
          {
            "from": "top",
            "to": "arrays",
            "type": "data",
            "source": "hist-b6500-reference",
            "locator": "§3 p. 3-3",
            "label": ""
          },
          {
            "from": "descriptor",
            "to": "mcp",
            "type": "control",
            "source": "hist-b6500-reference",
            "locator": "§3 p. 3-4 presence interrupt",
            "label": ""
          },
          {
            "from": "disk",
            "to": "arrays",
            "type": "data",
            "source": "hist-b6500-reference",
            "locator": "§3 p. 3-4",
            "label": ""
          },
          {
            "from": "mcp",
            "to": "descriptor",
            "type": "control",
            "source": "hist-b6500-reference",
            "locator": "§3 p. 3-4 P-bit update",
            "label": ""
          },
          {
            "from": "mcp",
            "to": "multiplexor",
            "type": "control",
            "source": "hist-b6500-reference",
            "locator": "§1 p. 1-9",
            "label": ""
          },
          {
            "from": "multiplexor",
            "to": "arrays",
            "type": "data",
            "source": "hist-b6500-reference",
            "locator": "§1 p. 1-17",
            "label": ""
          },
          {
            "from": "arrays",
            "to": "multiplexor",
            "type": "data",
            "source": "hist-b6500-reference",
            "locator": "§1 p. 1-17",
            "label": ""
          },
          {
            "from": "devices",
            "to": "multiplexor",
            "type": "data",
            "source": "hist-b6500-reference",
            "locator": "§1 Figure 1-4",
            "label": ""
          },
          {
            "from": "multiplexor",
            "to": "devices",
            "type": "data",
            "source": "hist-b6500-reference",
            "locator": "§1 Figure 1-4",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Burroughs B6500"
    },
    {
      "id": "queue-034",
      "name": "English Electric KDF9 — programming-manual organization",
      "organization": "English Electric",
      "year": 1964,
      "yearLabel": "KDF9 service era; inspected manual undated",
      "kind": "Stack-oriented mainframe",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "stack"
      ],
      "substrates": [
        "transistor",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-kdf9-programming"
      ],
      "summary": "Separate operand and return-address nests support compact arithmetic and subroutines; Q-stores combine counters, increments and modifiers.",
      "config": "Manual’s logical KDF9 with modular core; no specific installed memory size or optional time-sharing equipment assumed.",
      "gaps": [
        "The inspected transcription does not establish a print date; 1964 labels the model’s service era.",
        "Q0 is conventional zero and is not a sixteenth physical Q-register."
      ],
      "originalName": "English Electric KDF9",
      "insight": "Why keep arithmetic operands and subroutine return addresses in separate nests?",
      "fields": {
        "state": {
          "value": "48-bit words; fixed/floating single/double precision",
          "source": "hist-kdf9-programming",
          "locator": "§§3.1, 3.4"
        },
        "compute": {
          "value": "Top-of-nest operand arithmetic",
          "source": "hist-kdf9-programming",
          "locator": "§§3.3–3.4"
        },
        "memory": {
          "value": "4,096-word core modules and 16-word operand nest",
          "source": "hist-kdf9-programming",
          "locator": "§§3.1, 3.3"
        },
        "control": {
          "value": "Q1–Q15; 16-cell subroutine jump nest",
          "source": "hist-kdf9-programming",
          "locator": "§§3.5–3.7"
        },
        "io": {
          "value": "Autonomous device buffers and protective interlocks",
          "source": "hist-kdf9-programming",
          "locator": "§3.2"
        },
        "software": {
          "value": "Director supervises holds and control services",
          "source": "hist-kdf9-programming",
          "locator": "§3.8"
        },
        "workload": {
          "value": "Scientific calculations and general numerical programs",
          "source": "hist-kdf9-programming",
          "locator": "§3.4"
        }
      },
      "diagram": {
        "title": "Two nests, Q-register fields and autonomous device buffers",
        "scope": "Operand values and return addresses have different automatic lifetime rules.",
        "nodes": [
          {
            "id": "core",
            "label": "Main core store",
            "subtitle": "4K-WORD MODULES",
            "text": "Retains instructions and program data.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-kdf9-programming",
            "locator": "§3.1",
            "control": false
          },
          {
            "id": "control",
            "label": "Instruction control",
            "subtitle": "SYLLABLE SEQUENCE",
            "text": "Fetches words and initiates actions.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-kdf9-programming",
            "locator": "§3.6",
            "control": true
          },
          {
            "id": "q",
            "label": "Q1–Q15",
            "subtitle": "COUNTER / INCREMENT / MODIFIER",
            "text": "Provide loop and address state.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-kdf9-programming",
            "locator": "§3.5",
            "control": false
          },
          {
            "id": "nest",
            "label": "Operand nesting store",
            "subtitle": "16 × 48 BITS",
            "text": "Keeps last-in-first-out operands.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-kdf9-programming",
            "locator": "§3.3",
            "control": false
          },
          {
            "id": "arith",
            "label": "Arithmetic functions",
            "subtitle": "TOP OPERANDS",
            "text": "Consume operands and leave results.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-kdf9-programming",
            "locator": "§3.4",
            "control": false
          },
          {
            "id": "returns",
            "label": "Subroutine jump nest",
            "subtitle": "16 RETURN ADDRESSES",
            "text": "Records nested subroutine entries.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-kdf9-programming",
            "locator": "§3.7",
            "control": false
          },
          {
            "id": "buffers",
            "label": "Device buffer units",
            "subtitle": "AUTONOMOUS I/O",
            "text": "Complete transfers after initiation.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-kdf9-programming",
            "locator": "§3.2",
            "control": false
          },
          {
            "id": "devices",
            "label": "Tape / cards / typewriter",
            "subtitle": "EXTERNAL I/O",
            "text": "Operate via individual buffers.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-kdf9-programming",
            "locator": "§3.2",
            "control": false
          },
          {
            "id": "director",
            "label": "Director / test state",
            "subtitle": "CONTROL SERVICES",
            "text": "Handles holds and interrogates devices.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-kdf9-programming",
            "locator": "§§3.2, 3.8",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "core",
            "to": "control",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§3.6",
            "label": ""
          },
          {
            "from": "control",
            "to": "core",
            "type": "control",
            "source": "hist-kdf9-programming",
            "locator": "§3.6",
            "label": ""
          },
          {
            "from": "core",
            "to": "nest",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§3.3",
            "label": ""
          },
          {
            "from": "nest",
            "to": "core",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§3.3; store operations",
            "label": ""
          },
          {
            "from": "nest",
            "to": "arith",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§3.4",
            "label": ""
          },
          {
            "from": "arith",
            "to": "nest",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§3.4",
            "label": ""
          },
          {
            "from": "q",
            "to": "nest",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§3.5",
            "label": ""
          },
          {
            "from": "nest",
            "to": "q",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§3.5",
            "label": ""
          },
          {
            "from": "control",
            "to": "returns",
            "type": "control",
            "source": "hist-kdf9-programming",
            "locator": "§3.7",
            "label": ""
          },
          {
            "from": "returns",
            "to": "control",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§11 EXIT",
            "label": ""
          },
          {
            "from": "returns",
            "to": "nest",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§3.7",
            "label": ""
          },
          {
            "from": "buffers",
            "to": "core",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§3.2",
            "label": ""
          },
          {
            "from": "core",
            "to": "buffers",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§3.2",
            "label": ""
          },
          {
            "from": "devices",
            "to": "buffers",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§3.2",
            "label": ""
          },
          {
            "from": "buffers",
            "to": "devices",
            "type": "data",
            "source": "hist-kdf9-programming",
            "locator": "§3.2",
            "label": ""
          },
          {
            "from": "buffers",
            "to": "director",
            "type": "control",
            "source": "hist-kdf9-programming",
            "locator": "§3.2 test register",
            "label": ""
          }
        ]
      },
      "originalCandidate": "English Electric KDF9"
    },
    {
      "id": "queue-035",
      "name": "GE-645 — initial MIT Multics system",
      "organization": "General Electric / MIT Project MAC / Bell Laboratories",
      "year": 1970,
      "yearLabel": "Spring 1970 operating service",
      "kind": "Time-sharing system",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "smp"
      ],
      "substrates": [
        "transistor",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-ge645-manual",
        "hist-multics-saltzer"
      ],
      "summary": "Segment descriptors and page mappings connect each process’s address environment to shared physical storage; associative entries avoid repeated walks.",
      "config": "Initial MIT two-processor GE-645 installation before the 1972 CPU upgrade. Multics service status comes from Saltzer, not the January 1968 plans.",
      "gaps": [
        "Honeywell 6180 hardware rings and later Multics features are not assigned to the GE-645.",
        "Approximate memory bytes follow Saltzer’s wording."
      ],
      "originalName": "GE-645 / Multics",
      "insight": "How can two descriptor environments refer to the same physical segment?",
      "fields": {
        "state": {
          "value": "36-bit words; A/Q combine for 72-bit operands",
          "source": "hist-ge645-manual",
          "locator": "Chapter 6 register descriptions"
        },
        "compute": {
          "value": "GE-645 arithmetic plus segment/page address preparation",
          "source": "hist-ge645-manual",
          "locator": "Chapter 6"
        },
        "memory": {
          "value": "Three core-memory boxes, each about 1 MB, plus drum/disk",
          "source": "hist-multics-saltzer",
          "locator": "Initial configuration list"
        },
        "control": {
          "value": "DBR, segment descriptors, page tables and access permissions",
          "source": "hist-ge645-manual",
          "locator": "Chapter 6"
        },
        "io": {
          "value": "General I/O controllers and external devices",
          "source": "hist-ge645-manual",
          "locator": "Chapter 4"
        },
        "software": {
          "value": "Multics segmented/paged execution environment",
          "source": "hist-ge645-manual",
          "locator": "Chapter 6"
        },
        "workload": {
          "value": "35 simultaneous time-sharing users in Spring 1970",
          "source": "hist-multics-saltzer",
          "locator": "Performance paragraph"
        }
      },
      "diagram": {
        "title": "Per-process descriptors, page origins and controller-based storage",
        "scope": "Logical address-generation path. Descriptor/page tables reside in core; associative hits avoid those extra references.",
        "nodes": [
          {
            "id": "processor",
            "label": "GE-645 processor",
            "subtitle": "A / Q / INDEX STATE",
            "text": "Executes user or privileged operations.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ge645-manual",
            "locator": "Chapter 6",
            "control": false
          },
          {
            "id": "dbr",
            "label": "Descriptor Base Register",
            "subtitle": "PROCESS ENVIRONMENT",
            "text": "Locates the process descriptor segment.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ge645-manual",
            "locator": "Chapter 6 descriptor segment",
            "control": false
          },
          {
            "id": "sdw",
            "label": "Segment descriptors",
            "subtitle": "ORIGIN / PERMISSIONS",
            "text": "Locate and protect referenced segments.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ge645-manual",
            "locator": "Chapter 6",
            "control": false
          },
          {
            "id": "page",
            "label": "Page table words",
            "subtitle": "PAGE ORIGINS",
            "text": "Resolve pages within segments.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ge645-manual",
            "locator": "Chapter 6 paging",
            "control": false
          },
          {
            "id": "assoc",
            "label": "Associative memory",
            "subtitle": "16 PAGE MAPPINGS",
            "text": "Reuses recent physical page origins.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ge645-manual",
            "locator": "Chapter 6 Associative Memory",
            "control": false
          },
          {
            "id": "controller",
            "label": "System controllers",
            "subtitle": "MEMORY / INTERRUPTS",
            "text": "Arbitrate connected module accesses.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ge645-manual",
            "locator": "Chapter 5",
            "control": true
          },
          {
            "id": "core",
            "label": "Core-memory modules",
            "subtitle": "RESIDENT SEGMENTS",
            "text": "Retain code, data and tables.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ge645-manual",
            "locator": "Chapters 4–5",
            "control": false
          },
          {
            "id": "gioc",
            "label": "General I/O controller",
            "subtitle": "AUTONOMOUS I/O",
            "text": "Connects storage and devices.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ge645-manual",
            "locator": "Chapter 4",
            "control": false
          },
          {
            "id": "devices",
            "label": "Drum / disk / terminals",
            "subtitle": "EXTERNAL STATE",
            "text": "Support swapping and interactive use.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-multics-saltzer",
            "locator": "Initial configuration list",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "processor",
            "to": "dbr",
            "type": "association",
            "source": "hist-ge645-manual",
            "locator": "Chapter 6 process environment",
            "label": ""
          },
          {
            "from": "dbr",
            "to": "sdw",
            "type": "control",
            "source": "hist-ge645-manual",
            "locator": "Chapter 6 descriptor segment",
            "label": ""
          },
          {
            "from": "sdw",
            "to": "page",
            "type": "data",
            "source": "hist-ge645-manual",
            "locator": "Chapter 6 paged segment",
            "label": ""
          },
          {
            "from": "page",
            "to": "assoc",
            "type": "data",
            "source": "hist-ge645-manual",
            "locator": "Chapter 6 Associative Memory",
            "label": ""
          },
          {
            "from": "assoc",
            "to": "controller",
            "type": "data",
            "source": "hist-ge645-manual",
            "locator": "Chapter 6 final absolute address",
            "label": ""
          },
          {
            "from": "page",
            "to": "controller",
            "type": "data",
            "source": "hist-ge645-manual",
            "locator": "Chapter 6 final absolute address",
            "label": ""
          },
          {
            "from": "controller",
            "to": "core",
            "type": "data",
            "source": "hist-ge645-manual",
            "locator": "Chapter 5",
            "label": ""
          },
          {
            "from": "core",
            "to": "controller",
            "type": "data",
            "source": "hist-ge645-manual",
            "locator": "Chapter 5",
            "label": ""
          },
          {
            "from": "core",
            "to": "sdw",
            "type": "data",
            "source": "hist-ge645-manual",
            "locator": "Chapter 6 table lookup",
            "label": ""
          },
          {
            "from": "core",
            "to": "page",
            "type": "data",
            "source": "hist-ge645-manual",
            "locator": "Chapter 6 table lookup",
            "label": ""
          },
          {
            "from": "gioc",
            "to": "controller",
            "type": "data",
            "source": "hist-ge645-manual",
            "locator": "Chapter 4 system organization",
            "label": ""
          },
          {
            "from": "controller",
            "to": "gioc",
            "type": "data",
            "source": "hist-ge645-manual",
            "locator": "Chapter 4 system organization",
            "label": ""
          },
          {
            "from": "gioc",
            "to": "devices",
            "type": "association",
            "source": "hist-multics-saltzer",
            "locator": "Initial configuration list",
            "label": ""
          }
        ]
      },
      "originalCandidate": "GE 645 / Multics"
    },
    {
      "id": "queue-036",
      "name": "Tandem 16 NonStop — two-processor slice",
      "organization": "Tandem Computers",
      "year": 1978,
      "yearLabel": "1978 designer hardware paper",
      "kind": "Fault-tolerant transaction system",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "distributed",
        "mimd",
        "fault-tolerant",
        "microcoded"
      ],
      "substrates": [
        "integrated",
        "magnetic"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "hist-tandem16-katzman",
        "hist-tandem16-processor",
        "hist-tandem-kernel"
      ],
      "summary": "Independent processors and memories use duplicated communication paths; each I/O controller is reachable from two separately powered processors.",
      "config": "Two-processor slice of the expandable Tandem 16 organization, not a maximum 16-processor installation.",
      "gaps": [
        "The diagram covers hardware reachability, not application transaction semantics.",
        "Processor memory population is variable."
      ],
      "originalName": "Tandem NonStop",
      "insight": "Why do two I/O ports need independent processor and power paths?",
      "fields": {
        "state": {
          "value": "16-bit stack/register processor view",
          "source": "hist-tandem16-processor",
          "locator": "Processor Module Organization"
        },
        "compute": {
          "value": "Microprogrammed CPU with eight register-stack entries",
          "source": "hist-tandem16-processor",
          "locator": "The CPU"
        },
        "memory": {
          "value": "Independent local core or semiconductor memory",
          "source": "hist-tandem16-processor",
          "locator": "Processor Module Organization"
        },
        "control": {
          "value": "Private execution plus Dynabus communication",
          "source": "hist-tandem16-processor",
          "locator": "Interconnections"
        },
        "io": {
          "value": "Dual-ported, dual-powered peripheral controllers",
          "source": "hist-tandem16-processor",
          "locator": "Power distribution"
        },
        "software": {
          "value": "Kernel processes/messages and process-pairs",
          "source": "hist-tandem-kernel",
          "locator": "Abstract; 1981 software account"
        },
        "workload": {
          "value": "Continuous online transaction service",
          "source": "hist-tandem16-processor",
          "locator": "System organization"
        }
      },
      "diagram": {
        "title": "Independent processor islands with duplicated reachability",
        "scope": "Two processors represent a slice of the modular system. Power edges are associations, not information buses.",
        "nodes": [
          {
            "id": "cpuA",
            "label": "Processor A",
            "subtitle": "16-BIT CPU / CHANNEL",
            "text": "Runs independent instructions.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-tandem16-katzman",
            "locator": "§1 processor module",
            "control": false
          },
          {
            "id": "bus0",
            "label": "Dynabus 0",
            "subtitle": "INTERPROCESSOR LINK",
            "text": "Provides one communication path.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-tandem16-katzman",
            "locator": "§1",
            "control": false
          },
          {
            "id": "cpuB",
            "label": "Processor B",
            "subtitle": "16-BIT CPU / CHANNEL",
            "text": "Runs independent instructions.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-tandem16-katzman",
            "locator": "§1 processor module",
            "control": false
          },
          {
            "id": "memA",
            "label": "Memory A",
            "subtitle": "PRIVATE STATE",
            "text": "Belongs to processor A.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-tandem16-katzman",
            "locator": "§1 packaging",
            "control": false
          },
          {
            "id": "bus1",
            "label": "Dynabus 1",
            "subtitle": "REDUNDANT LINK",
            "text": "Provides the alternate path.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-tandem16-katzman",
            "locator": "§1",
            "control": false
          },
          {
            "id": "memB",
            "label": "Memory B",
            "subtitle": "PRIVATE STATE",
            "text": "Belongs to processor B.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-tandem16-katzman",
            "locator": "§1 packaging",
            "control": false
          },
          {
            "id": "controller",
            "label": "Dual-ported controller",
            "subtitle": "TWO I/O CHANNELS",
            "text": "Can be reached through either processor.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-tandem16-katzman",
            "locator": "§1",
            "control": false
          },
          {
            "id": "device",
            "label": "Peripheral device",
            "subtitle": "TRANSACTION I/O",
            "text": "Connects through its controller.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-tandem16-katzman",
            "locator": "§1",
            "control": false
          },
          {
            "id": "power",
            "label": "Independent supplies",
            "subtitle": "DUAL-SOURCED I/O",
            "text": "Isolate processor and controller power.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-tandem16-processor",
            "locator": "p. 472 dual-power paragraph",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpuA",
            "to": "memA",
            "type": "data",
            "source": "hist-tandem16-katzman",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "memA",
            "to": "cpuA",
            "type": "data",
            "source": "hist-tandem16-katzman",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "cpuB",
            "to": "memB",
            "type": "data",
            "source": "hist-tandem16-katzman",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "memB",
            "to": "cpuB",
            "type": "data",
            "source": "hist-tandem16-katzman",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "cpuA",
            "to": "bus0",
            "type": "data",
            "source": "hist-tandem16-katzman",
            "locator": "§1 dual Dynabus",
            "label": ""
          },
          {
            "from": "bus0",
            "to": "cpuB",
            "type": "data",
            "source": "hist-tandem16-katzman",
            "locator": "§1 dual Dynabus",
            "label": ""
          },
          {
            "from": "cpuB",
            "to": "bus1",
            "type": "data",
            "source": "hist-tandem16-katzman",
            "locator": "§1 dual Dynabus",
            "label": ""
          },
          {
            "from": "bus1",
            "to": "cpuA",
            "type": "data",
            "source": "hist-tandem16-katzman",
            "locator": "§1 dual Dynabus",
            "label": ""
          },
          {
            "from": "cpuA",
            "to": "controller",
            "type": "data",
            "source": "hist-tandem16-katzman",
            "locator": "§1 dual I/O channels",
            "label": ""
          },
          {
            "from": "cpuB",
            "to": "controller",
            "type": "data",
            "source": "hist-tandem16-katzman",
            "locator": "§1 dual I/O channels",
            "label": ""
          },
          {
            "from": "controller",
            "to": "device",
            "type": "data",
            "source": "hist-tandem16-katzman",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "device",
            "to": "controller",
            "type": "data",
            "source": "hist-tandem16-katzman",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "power",
            "to": "cpuA",
            "type": "association",
            "source": "hist-tandem16-processor",
            "locator": "p. 472 power distribution",
            "label": ""
          },
          {
            "from": "power",
            "to": "cpuB",
            "type": "association",
            "source": "hist-tandem16-processor",
            "locator": "p. 472 power distribution",
            "label": ""
          },
          {
            "from": "power",
            "to": "controller",
            "type": "association",
            "source": "hist-tandem16-processor",
            "locator": "p. 472 current sharing",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Tandem NonStop"
    },
    {
      "id": "queue-037",
      "name": "Stratus ftServer V2404 — OpenVOS 19.1 configuration",
      "organization": "Stratus Technologies",
      "year": 2019,
      "yearLabel": "December 2019 manufacturer guide",
      "kind": "Fault-tolerant server",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "fault-tolerant"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-stratus-v2404"
      ],
      "summary": "Two CPU/I/O enclosures run the same CPU state in lockstep; duplicated I/O paths and replaceable enclosures preserve service after a component failure.",
      "config": "V2404 with one quad-core 2.0 GHz Xeon per enclosure and direct U580V Fibre Channel; V4408/6408 fabric-switch topology excluded.",
      "gaps": [
        "No installed RAM capacity is inferred from the slot count.",
        "This representative is much later than Stratus FT200; it does not cover the entire Stratus lineage."
      ],
      "originalName": "Stratus fault-tolerant systems",
      "insight": "Why is duplicated CPU execution different from alternate-path I/O recovery?",
      "fields": {
        "state": {
          "value": "Identical lockstep execution state in two CPU elements",
          "source": "hist-stratus-v2404",
          "locator": "p. 1-2"
        },
        "compute": {
          "value": "One quad-core 2.0 GHz Xeon per enclosure",
          "source": "hist-stratus-v2404",
          "locator": "p. A-6"
        },
        "memory": {
          "value": "Six fully buffered DIMM slots per enclosure",
          "source": "hist-stratus-v2404",
          "locator": "p. A-6"
        },
        "control": {
          "value": "CPU fault isolation; I/O element takeover",
          "source": "hist-stratus-v2404",
          "locator": "pp. 1-2–1-3"
        },
        "io": {
          "value": "Duplicated PCIe/FC paths; Ethernet ports",
          "source": "hist-stratus-v2404",
          "locator": "pp. 3-2, A-6"
        },
        "software": {
          "value": "OpenVOS 19.1.0 configuration",
          "source": "hist-stratus-v2404",
          "locator": "Publication notice"
        },
        "workload": {
          "value": "Continuous general-purpose service",
          "source": "hist-stratus-v2404",
          "locator": "pp. 1-2–1-3"
        }
      },
      "diagram": {
        "title": "Lockstep CPU elements and paired external-storage paths",
        "scope": "The two enclosures are one logical system. Synchronization is a relationship; internal comparison circuitry is not invented.",
        "nodes": [
          {
            "id": "cpu0",
            "label": "CPU element 0",
            "subtitle": "QUAD-CORE XEON",
            "text": "Runs the same instruction stream.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-stratus-v2404",
            "locator": "pp. 1-2, A-6",
            "control": false
          },
          {
            "id": "sync",
            "label": "Lockstep relationship",
            "subtitle": "DUPLICATED STATE",
            "text": "Keeps CPU execution synchronized.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-stratus-v2404",
            "locator": "p. 1-2",
            "control": true
          },
          {
            "id": "cpu1",
            "label": "CPU element 1",
            "subtitle": "QUAD-CORE XEON",
            "text": "Continues after its partner fails.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-stratus-v2404",
            "locator": "pp. 1-2, A-6",
            "control": false
          },
          {
            "id": "io0",
            "label": "I/O element 0",
            "subtitle": "PCIe / FC ADAPTERS",
            "text": "Provides one peripheral path.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-stratus-v2404",
            "locator": "pp. 1-2, 3-2",
            "control": false
          },
          {
            "id": "storage",
            "label": "ftScalable storage",
            "subtitle": "EXTERNAL RAID",
            "text": "Accepts paired FC connections.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-stratus-v2404",
            "locator": "p. 3-2",
            "control": false
          },
          {
            "id": "io1",
            "label": "I/O element 1",
            "subtitle": "PCIe / FC ADAPTERS",
            "text": "Provides an alternate peripheral path.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-stratus-v2404",
            "locator": "pp. 1-2, 3-2",
            "control": false
          },
          {
            "id": "ram0",
            "label": "Enclosure 0 DIMMs",
            "subtitle": "SIX SLOTS",
            "text": "Retains replicated working state.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-stratus-v2404",
            "locator": "pp. 1-2, A-6",
            "control": false
          },
          {
            "id": "network",
            "label": "Ethernet connections",
            "subtitle": "DUPLICATED PORTS",
            "text": "Connect client and service networks.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-stratus-v2404",
            "locator": "p. A-6",
            "control": false
          },
          {
            "id": "ram1",
            "label": "Enclosure 1 DIMMs",
            "subtitle": "SIX SLOTS",
            "text": "Retains the corresponding working state.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-stratus-v2404",
            "locator": "pp. 1-2, A-6",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "sync",
            "to": "cpu0",
            "type": "control",
            "source": "hist-stratus-v2404",
            "locator": "p. 1-2",
            "label": ""
          },
          {
            "from": "sync",
            "to": "cpu1",
            "type": "control",
            "source": "hist-stratus-v2404",
            "locator": "p. 1-2",
            "label": ""
          },
          {
            "from": "cpu0",
            "to": "ram0",
            "type": "data",
            "source": "hist-stratus-v2404",
            "locator": "pp. 1-2, A-6",
            "label": ""
          },
          {
            "from": "ram0",
            "to": "cpu0",
            "type": "data",
            "source": "hist-stratus-v2404",
            "locator": "pp. 1-2, A-6",
            "label": ""
          },
          {
            "from": "cpu1",
            "to": "ram1",
            "type": "data",
            "source": "hist-stratus-v2404",
            "locator": "pp. 1-2, A-6",
            "label": ""
          },
          {
            "from": "ram1",
            "to": "cpu1",
            "type": "data",
            "source": "hist-stratus-v2404",
            "locator": "pp. 1-2, A-6",
            "label": ""
          },
          {
            "from": "cpu0",
            "to": "io0",
            "type": "association",
            "source": "hist-stratus-v2404",
            "locator": "p. 1-2 enclosure elements",
            "label": ""
          },
          {
            "from": "cpu1",
            "to": "io1",
            "type": "association",
            "source": "hist-stratus-v2404",
            "locator": "p. 1-2 enclosure elements",
            "label": ""
          },
          {
            "from": "io0",
            "to": "storage",
            "type": "data",
            "source": "hist-stratus-v2404",
            "locator": "p. 3-2 paired U580V ports",
            "label": ""
          },
          {
            "from": "io1",
            "to": "storage",
            "type": "data",
            "source": "hist-stratus-v2404",
            "locator": "p. 3-2 paired U580V ports",
            "label": ""
          },
          {
            "from": "storage",
            "to": "io0",
            "type": "data",
            "source": "hist-stratus-v2404",
            "locator": "p. 3-2",
            "label": ""
          },
          {
            "from": "storage",
            "to": "io1",
            "type": "data",
            "source": "hist-stratus-v2404",
            "locator": "p. 3-2",
            "label": ""
          },
          {
            "from": "io0",
            "to": "network",
            "type": "data",
            "source": "hist-stratus-v2404",
            "locator": "p. A-6",
            "label": ""
          },
          {
            "from": "io1",
            "to": "network",
            "type": "data",
            "source": "hist-stratus-v2404",
            "locator": "p. A-6",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Stratus fault-tolerant systems"
    },
    {
      "id": "queue-038",
      "name": "Elbrus-1 — first-generation architecture",
      "organization": "ITM and VT, Moscow",
      "year": 1978,
      "yearLabel": "First delivery recalled by Babayan; formal acceptance was later",
      "kind": "Tagged multiprocessor system",
      "status": "dossier",
      "track": "mainframe",
      "trackName": "Mainframes & fault tolerance",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "stack",
        "smp",
        "mimd",
        "superscalar"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-elbrus-institution",
        "hist-elbrus-babayan"
      ],
      "summary": "A tagged stack programming model sits above dynamically scheduled execution and a modular shared-memory system with distinct I/O processors.",
      "config": "First-generation Elbrus-1 architecture; modular counts are capabilities rather than a claim about one installed machine.",
      "gaps": [
        "No complete original Elbrus-1 hardware manual was retrieved.",
        "Common system roles follow an institutional history; processor-detail evidence is explicitly retrospective.",
        "Elbrus-2 maxima and later E2K VLIW features are excluded."
      ],
      "originalName": "Elbrus-1",
      "insight": "How can a stack-visible instruction set coexist with internal out-of-order execution?",
      "fields": {
        "state": {
          "value": "Tagged typed data, references and descriptors",
          "source": "hist-elbrus-babayan",
          "locator": "pp. 10–11"
        },
        "compute": {
          "value": "Two-issue out-of-order execution, as recalled by architect",
          "source": "hist-elbrus-babayan",
          "locator": "p. 13"
        },
        "memory": {
          "value": "Shared modules reached through a protective switch",
          "source": "hist-elbrus-institution",
          "locator": "p. 18"
        },
        "control": {
          "value": "Modular multiprocessor organization and monitoring",
          "source": "hist-elbrus-institution",
          "locator": "p. 18"
        },
        "io": {
          "value": "Separate I/O and communications processors",
          "source": "hist-elbrus-institution",
          "locator": "p. 18"
        },
        "software": {
          "value": "El-76 system software and multiprogrammed OS",
          "source": "hist-elbrus-institution",
          "locator": "p. 19"
        },
        "workload": {
          "value": "Scientific, space and defense computation",
          "source": "hist-elbrus-institution",
          "locator": "p. 18"
        }
      },
      "diagram": {
        "title": "Stack-visible typed execution within a modular shared-memory system",
        "scope": "Shared-memory and processor-class roles are common to the first two generations in the institutional source; no Elbrus-2 performance is assigned.",
        "nodes": [
          {
            "id": "cpu",
            "label": "Central processors",
            "subtitle": "ELBRUS-1 EXECUTION",
            "text": "Run independent instruction streams.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-elbrus-institution",
            "locator": "p. 18",
            "control": false
          },
          {
            "id": "stack",
            "label": "Operand stacks",
            "subtitle": "REVERSE POLISH MODEL",
            "text": "Provide operands to stack operations.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-elbrus-institution",
            "locator": "p. 19",
            "control": false
          },
          {
            "id": "types",
            "label": "Tags / descriptors",
            "subtitle": "TYPE SAFETY",
            "text": "Support typed references and objects.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-elbrus-babayan",
            "locator": "pp. 10–11",
            "control": false
          },
          {
            "id": "switch",
            "label": "Memory switch",
            "subtitle": "SHARED ACCESS / ISOLATION",
            "text": "Connects processors and memory modules.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-elbrus-institution",
            "locator": "p. 18",
            "control": true
          },
          {
            "id": "memory",
            "label": "Memory modules",
            "subtitle": "SHARED RESIDENT STATE",
            "text": "Serve processor requests.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-elbrus-institution",
            "locator": "p. 18",
            "control": false
          },
          {
            "id": "io",
            "label": "I/O processors",
            "subtitle": "EXTERNAL TRANSFERS",
            "text": "Handle input/output work.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-elbrus-institution",
            "locator": "p. 18",
            "control": false
          },
          {
            "id": "comm",
            "label": "Communications processors",
            "subtitle": "COMMUNICATION SERVICES",
            "text": "Provide a separate processing class.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-elbrus-institution",
            "locator": "p. 18",
            "control": false
          },
          {
            "id": "storage",
            "label": "Drum / disk controls",
            "subtitle": "STORAGE MANAGEMENT",
            "text": "Manage external storage modules.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-elbrus-institution",
            "locator": "p. 18",
            "control": false
          },
          {
            "id": "software",
            "label": "El-76 / operating system",
            "subtitle": "SYSTEM LAYER",
            "text": "Coordinates multiprogrammed computation.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-elbrus-institution",
            "locator": "p. 19",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "stack",
            "to": "cpu",
            "type": "data",
            "source": "hist-elbrus-institution",
            "locator": "p. 19 operand stack",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "stack",
            "type": "data",
            "source": "hist-elbrus-institution",
            "locator": "p. 19 stack operations",
            "label": ""
          },
          {
            "from": "types",
            "to": "cpu",
            "type": "association",
            "source": "hist-elbrus-babayan",
            "locator": "pp. 10–11 tagged execution",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "switch",
            "type": "data",
            "source": "hist-elbrus-institution",
            "locator": "p. 18 any-memory access",
            "label": ""
          },
          {
            "from": "switch",
            "to": "cpu",
            "type": "data",
            "source": "hist-elbrus-institution",
            "locator": "p. 18 any-memory access",
            "label": ""
          },
          {
            "from": "switch",
            "to": "memory",
            "type": "data",
            "source": "hist-elbrus-institution",
            "locator": "p. 18",
            "label": ""
          },
          {
            "from": "memory",
            "to": "switch",
            "type": "data",
            "source": "hist-elbrus-institution",
            "locator": "p. 18",
            "label": ""
          },
          {
            "from": "io",
            "to": "switch",
            "type": "association",
            "source": "hist-elbrus-institution",
            "locator": "p. 18 system components",
            "label": ""
          },
          {
            "from": "comm",
            "to": "io",
            "type": "association",
            "source": "hist-elbrus-institution",
            "locator": "p. 18 processor classes",
            "label": ""
          },
          {
            "from": "storage",
            "to": "io",
            "type": "association",
            "source": "hist-elbrus-institution",
            "locator": "p. 18 storage-management components",
            "label": ""
          },
          {
            "from": "software",
            "to": "cpu",
            "type": "association",
            "source": "hist-elbrus-institution",
            "locator": "p. 19 El-76 system software",
            "label": ""
          },
          {
            "from": "software",
            "to": "types",
            "type": "association",
            "source": "hist-elbrus-babayan",
            "locator": "pp. 10–11 language/type support",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Elbrus-1"
    },
    {
      "id": "queue-039",
      "name": "DEC PDP-1 — October 1963 handbook configuration",
      "organization": "Digital Equipment Corporation",
      "year": 1963,
      "yearLabel": "October 1963 handbook",
      "kind": "Interactive minicomputer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator"
      ],
      "substrates": [
        "transistor",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-pdp1-1963"
      ],
      "summary": "An 18-bit accumulator computer couples core storage to interactive peripherals through an I/O register and interrupt-like sequence break.",
      "config": "Standard 4096-word configuration in the October 1963 handbook; expanded memory, multichannel sequence break and high-speed channel remain optional.",
      "gaps": [
        "This later handbook configuration is not asserted to describe every 1960 installation.",
        "Optional displays, memory extensions and high-speed data controls are shown as options, not installed equipment."
      ],
      "originalName": "DEC PDP-1",
      "insight": "Why does the I/O register participate in both arithmetic and peripheral transfers?",
      "fields": {
        "state": {
          "value": "18-bit accumulator, I/O register and core words",
          "source": "hist-pdp1-1963",
          "locator": "pp. 3, 7–8"
        },
        "compute": {
          "value": "Accumulator arithmetic; handbook-standard automatic multiply/divide",
          "source": "hist-pdp1-1963",
          "locator": "pp. 3–5"
        },
        "memory": {
          "value": "4096 18-bit core words; 5 μs cycle",
          "source": "hist-pdp1-1963",
          "locator": "pp. 3–5"
        },
        "control": {
          "value": "PC/MA addressing and single-channel sequence break",
          "source": "hist-pdp1-1963",
          "locator": "pp. 5, 7–8"
        },
        "io": {
          "value": "Reader, punch and bidirectional typewriter through I/O control",
          "source": "hist-pdp1-1963",
          "locator": "pp. 5–7"
        },
        "software": {
          "value": "Stored instructions; programmed I/O and sequence-break service",
          "source": "hist-pdp1-1963",
          "locator": "pp. 7–8"
        },
        "workload": {
          "value": "Scientific, real-time and interactive computation",
          "source": "hist-pdp1-1963",
          "locator": "pp. 3, 6–8"
        }
      },
      "diagram": {
        "title": "A shared arithmetic and peripheral I/O register",
        "scope": "Register roles follow pp. 7–8; equipment boundary follows the visually inspected pp. 4–5 diagram.",
        "nodes": [
          {
            "id": "core",
            "label": "Core memory",
            "subtitle": "4096 × 18 BITS",
            "text": "Stores instructions and working values.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1-1963",
            "locator": "pp. 3–5",
            "control": false
          },
          {
            "id": "mb",
            "label": "Memory buffer",
            "subtitle": "18-BIT WORD TRANSFER",
            "text": "Holds words crossing the core interface.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1-1963",
            "locator": "pp. 7–8",
            "control": false
          },
          {
            "id": "ac",
            "label": "Accumulator",
            "subtitle": "ARITHMETIC STATE",
            "text": "Retains arithmetic operands and results.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1-1963",
            "locator": "pp. 7–8",
            "control": false
          },
          {
            "id": "address",
            "label": "PC and MA",
            "subtitle": "INSTRUCTION / DATA ADDRESS",
            "text": "Select successive or addressed core locations.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1-1963",
            "locator": "pp. 7–8",
            "control": false
          },
          {
            "id": "control",
            "label": "Central control",
            "subtitle": "DECODE / SEQUENCE BREAK",
            "text": "Sequences instructions and interrupted service.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1-1963",
            "locator": "pp. 5, 7–8",
            "control": true
          },
          {
            "id": "io",
            "label": "I/O register",
            "subtitle": "ARITHMETIC AND I/O",
            "text": "Extends arithmetic and carries device words.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1-1963",
            "locator": "pp. 7–8",
            "control": false
          },
          {
            "id": "devices",
            "label": "Reader / punch / typewriter",
            "subtitle": "STANDARD PERIPHERALS",
            "text": "Exchange paper-tape and typed information.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1-1963",
            "locator": "pp. 5–7",
            "control": false
          },
          {
            "id": "hs",
            "label": "High-speed channel",
            "subtitle": "OPTIONAL TYPE 19 / 131",
            "text": "Provides an optional fast transfer path.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1-1963",
            "locator": "pp. 4–5, 7",
            "control": false
          },
          {
            "id": "expand",
            "label": "Memory extension",
            "subtitle": "OPTIONAL TYPE 15 / 12",
            "text": "Connects additional core modules.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1-1963",
            "locator": "pp. 4–5",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "core",
            "to": "mb",
            "type": "data",
            "source": "hist-pdp1-1963",
            "locator": "pp. 7–8",
            "label": ""
          },
          {
            "from": "mb",
            "to": "core",
            "type": "data",
            "source": "hist-pdp1-1963",
            "locator": "pp. 7–8",
            "label": ""
          },
          {
            "from": "mb",
            "to": "ac",
            "type": "data",
            "source": "hist-pdp1-1963",
            "locator": "pp. 7–8",
            "label": ""
          },
          {
            "from": "ac",
            "to": "mb",
            "type": "data",
            "source": "hist-pdp1-1963",
            "locator": "pp. 7–8",
            "label": ""
          },
          {
            "from": "address",
            "to": "core",
            "type": "control",
            "source": "hist-pdp1-1963",
            "locator": "pp. 7–8",
            "label": ""
          },
          {
            "from": "mb",
            "to": "control",
            "type": "control",
            "source": "hist-pdp1-1963",
            "locator": "pp. 7–8 instruction decoding",
            "label": ""
          },
          {
            "from": "control",
            "to": "address",
            "type": "control",
            "source": "hist-pdp1-1963",
            "locator": "pp. 7–8",
            "label": ""
          },
          {
            "from": "io",
            "to": "ac",
            "type": "association",
            "source": "hist-pdp1-1963",
            "locator": "pp. 7–8 arithmetic section",
            "label": ""
          },
          {
            "from": "devices",
            "to": "io",
            "type": "data",
            "source": "hist-pdp1-1963",
            "locator": "pp. 5–7 I/O transfer control",
            "label": ""
          },
          {
            "from": "io",
            "to": "devices",
            "type": "data",
            "source": "hist-pdp1-1963",
            "locator": "pp. 5–7",
            "label": ""
          },
          {
            "from": "hs",
            "to": "control",
            "type": "association",
            "source": "hist-pdp1-1963",
            "locator": "pp. 4–5 optional channel connection",
            "label": ""
          },
          {
            "from": "expand",
            "to": "core",
            "type": "association",
            "source": "hist-pdp1-1963",
            "locator": "pp. 4–5 optional memory connection",
            "label": ""
          }
        ]
      },
      "originalCandidate": "PDP-1"
    },
    {
      "id": "queue-040",
      "name": "DEC PDP-8 — original 1966 handbook machine",
      "organization": "Digital Equipment Corporation",
      "year": 1966,
      "yearLabel": "1966 handbook for original PDP-8",
      "kind": "12-bit minicomputer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator",
        "hardwired"
      ],
      "substrates": [
        "transistor",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-pdp8-1966"
      ],
      "summary": "A 12-bit accumulator and link execute short instructions while programmed I/O uses the accumulator and data-break transfers use the memory buffer.",
      "config": "Original PDP-8 with 4096 core words; optional extended arithmetic and later PDP-8 family implementations excluded.",
      "gaps": [
        "The EAE multiply timing is an option and is not assigned to the base machine.",
        "This record does not cover PDP-8/S serial logic or later PDP-8/I/E integrated implementations."
      ],
      "originalName": "DEC PDP-8",
      "insight": "How does data break move data without using the accumulator?",
      "fields": {
        "state": {
          "value": "12-bit accumulator plus one-bit link",
          "source": "hist-pdp8-1966",
          "locator": "System Introduction; Fig. 2"
        },
        "compute": {
          "value": "Parallel two’s-complement accumulator arithmetic",
          "source": "hist-pdp8-1966",
          "locator": "p. xiii"
        },
        "memory": {
          "value": "4096 12-bit core words; 1.5 μs cycle",
          "source": "hist-pdp8-1966",
          "locator": "p. xiii"
        },
        "control": {
          "value": "Major states and timing pulses gate register operations",
          "source": "hist-pdp8-1966",
          "locator": "p. 7"
        },
        "io": {
          "value": "Programmed I/O through AC; data break through MB",
          "source": "hist-pdp8-1966",
          "locator": "pp. xiii–xiv; Fig. 2"
        },
        "software": {
          "value": "Single-address stored instructions; software multiply unless EAE installed",
          "source": "hist-pdp8-1966",
          "locator": "p. xiii"
        },
        "workload": {
          "value": "Small general-purpose, laboratory and control computing",
          "source": "hist-pdp8-1966",
          "locator": "System Introduction"
        }
      },
      "diagram": {
        "title": "Two peripheral paths: accumulator I/O and memory data break",
        "scope": "Figure 2 and p. 7 distinguish the actual transfer registers and major-state controls.",
        "nodes": [
          {
            "id": "core",
            "label": "Core memory",
            "subtitle": "4096 × 12 BITS",
            "text": "Stores data and instructions in one array.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-pdp8-1966",
            "locator": "p. xiii; Fig. 2",
            "control": false
          },
          {
            "id": "mb",
            "label": "Memory buffer",
            "subtitle": "12-BIT MB",
            "text": "Transfers core words and data-break data.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "ac",
            "label": "AC and link",
            "subtitle": "12 + 1 BITS",
            "text": "Carry arithmetic and programmed I/O values.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "ma",
            "label": "Memory address",
            "subtitle": "12-BIT MA",
            "text": "Selects the active core location.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "pc",
            "label": "Program counter",
            "subtitle": "12-BIT PC",
            "text": "Identifies the next instruction address.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "ir",
            "label": "Instruction register",
            "subtitle": "3-BIT OPERATION",
            "text": "Selects the major instruction operation.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "states",
            "label": "Timing / major states",
            "subtitle": "HARDWIRED GATING",
            "text": "Sequences fetch, defer, execute and break.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-pdp8-1966",
            "locator": "p. 7; Fig. 2",
            "control": true
          },
          {
            "id": "pio",
            "label": "Programmed peripherals",
            "subtitle": "IOT / AC TRANSFERS",
            "text": "Provide data and request skips or interrupts.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-pdp8-1966",
            "locator": "p. 7; Fig. 2",
            "control": false
          },
          {
            "id": "break",
            "label": "Data-break interface",
            "subtitle": "MEMORY-CYCLE TRANSFERS",
            "text": "Requests core cycles using MA and MB controls.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-pdp8-1966",
            "locator": "p. 7; Fig. 2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "core",
            "to": "mb",
            "type": "data",
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "mb",
            "to": "core",
            "type": "data",
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "mb",
            "to": "ac",
            "type": "data",
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "ac",
            "to": "mb",
            "type": "data",
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "ma",
            "to": "core",
            "type": "control",
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "pc",
            "to": "ma",
            "type": "data",
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "mb",
            "to": "ir",
            "type": "data",
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "ir",
            "to": "states",
            "type": "control",
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "states",
            "to": "pc",
            "type": "control",
            "source": "hist-pdp8-1966",
            "locator": "p. 7",
            "label": ""
          },
          {
            "from": "states",
            "to": "mb",
            "type": "control",
            "source": "hist-pdp8-1966",
            "locator": "p. 7",
            "label": ""
          },
          {
            "from": "pio",
            "to": "ac",
            "type": "data",
            "source": "hist-pdp8-1966",
            "locator": "p. 7; Fig. 2",
            "label": ""
          },
          {
            "from": "ac",
            "to": "pio",
            "type": "data",
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "break",
            "to": "mb",
            "type": "data",
            "source": "hist-pdp8-1966",
            "locator": "p. 7; Fig. 2",
            "label": ""
          },
          {
            "from": "mb",
            "to": "break",
            "type": "data",
            "source": "hist-pdp8-1966",
            "locator": "Fig. 2",
            "label": ""
          },
          {
            "from": "break",
            "to": "states",
            "type": "control",
            "source": "hist-pdp8-1966",
            "locator": "p. 7; Fig. 2",
            "label": ""
          }
        ]
      },
      "originalCandidate": "PDP-8"
    },
    {
      "id": "queue-041",
      "name": "DEC PDP-10 KA10 — 1968 processor",
      "organization": "Digital Equipment Corporation",
      "year": 1968,
      "yearLabel": "December 1968 maintenance manual",
      "kind": "36-bit general-purpose computer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "register-memory",
        "hardwired"
      ],
      "substrates": [
        "transistor",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-ka10-1968"
      ],
      "summary": "The KA10 routes arithmetic and most I/O through AR, while a parity buffer bridges its registers and the external memory bus.",
      "config": "KA10 register organization; optional fast memory and KT10A relocation/protection remain options, not assumed standard installations.",
      "gaps": [
        "No particular installed core capacity or option set is inferred.",
        "The drawing focuses on KA10 physical registers and does not apply later KI10/KL10 paging or cache features."
      ],
      "originalName": "DEC PDP-10 / KA10",
      "insight": "Why is the architectural accumulator model different from the physical AR/BR/MQ datapath?",
      "fields": {
        "state": {
          "value": "36-bit AR, BR and MQ; 18-bit PC and MA",
          "source": "hist-ka10-1968",
          "locator": "pp. 4-1–4-2"
        },
        "compute": {
          "value": "36-bit adder with AR/BR inputs; MQ extends multiply/divide",
          "source": "hist-ka10-1968",
          "locator": "p. 4-1"
        },
        "memory": {
          "value": "Core modules on memory bus; optional fast accumulator memory",
          "source": "hist-ka10-1968",
          "locator": "p. 2-1; p. 4-1"
        },
        "control": {
          "value": "Instruction, address, fetch, execute and store cycles",
          "source": "hist-ka10-1968",
          "locator": "p. 4-2"
        },
        "io": {
          "value": "Separate I/O bus; data channels can access memory bus",
          "source": "hist-ka10-1968",
          "locator": "p. 2-1"
        },
        "software": {
          "value": "36-bit stored instruction execution; optional relocation/protection",
          "source": "hist-ka10-1968",
          "locator": "pp. 2-1, 4-1–4-2"
        },
        "workload": {
          "value": "General-purpose scientific and time-sharing processor organization",
          "source": "hist-ka10-1968",
          "locator": "pp. 2-1–2-2"
        }
      },
      "diagram": {
        "title": "AR-centered register transfers and the parity-buffer boundary",
        "scope": "Directions follow pp. 4-1–4-2; bus placement follows p. 2-1.",
        "nodes": [
          {
            "id": "ar",
            "label": "AR register",
            "subtitle": "36-BIT CENTRAL REGISTER",
            "text": "Accepts arithmetic, shift, memory and I/O inputs.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ka10-1968",
            "locator": "p. 4-1",
            "control": false
          },
          {
            "id": "adder",
            "label": "AD network",
            "subtitle": "AR / BR BOOLEAN-ARITHMETIC",
            "text": "Combines selected true/complemented inputs.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ka10-1968",
            "locator": "p. 4-1",
            "control": false
          },
          {
            "id": "br",
            "label": "BR register",
            "subtitle": "SECOND OPERAND",
            "text": "Loads only from AR and supplies the adder.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ka10-1968",
            "locator": "p. 4-1",
            "control": false
          },
          {
            "id": "mq",
            "label": "MQ register",
            "subtitle": "MULTIPLIER / QUOTIENT",
            "text": "Extends AR for multiply, divide and shifts.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ka10-1968",
            "locator": "p. 4-1",
            "control": false
          },
          {
            "id": "control",
            "label": "PC / MA / IR",
            "subtitle": "ADDRESS AND DECODE",
            "text": "Form addresses and sequence instruction cycles.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ka10-1968",
            "locator": "pp. 4-1–4-2",
            "control": true
          },
          {
            "id": "pb",
            "label": "Parity buffer",
            "subtitle": "37-BIT MEMORY BRIDGE",
            "text": "Holds every word crossing the memory bus.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ka10-1968",
            "locator": "p. 4-1",
            "control": false
          },
          {
            "id": "memory",
            "label": "Core memory bus",
            "subtitle": "EXTERNAL MODULES",
            "text": "Connects storage and memory-side channels.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ka10-1968",
            "locator": "p. 2-1",
            "control": false
          },
          {
            "id": "fast",
            "label": "Fast accumulator memory",
            "subtitle": "OPTIONAL",
            "text": "Supplies low-latency register words to AR.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ka10-1968",
            "locator": "pp. 2-1, 4-1",
            "control": false
          },
          {
            "id": "io",
            "label": "I/O bus and priority",
            "subtitle": "PERIPHERAL SERVICE",
            "text": "Moves device words through AR and signals interrupts.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ka10-1968",
            "locator": "pp. 2-1, 4-1–4-2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "ar",
            "to": "br",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1 BR loads AR",
            "label": ""
          },
          {
            "from": "ar",
            "to": "adder",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1",
            "label": ""
          },
          {
            "from": "br",
            "to": "adder",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1",
            "label": ""
          },
          {
            "from": "adder",
            "to": "ar",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1 AR input adder",
            "label": ""
          },
          {
            "from": "mq",
            "to": "ar",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1 shifting",
            "label": ""
          },
          {
            "from": "ar",
            "to": "mq",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1 shifting",
            "label": ""
          },
          {
            "from": "memory",
            "to": "pb",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1",
            "label": ""
          },
          {
            "from": "pb",
            "to": "memory",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1",
            "label": ""
          },
          {
            "from": "ar",
            "to": "pb",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1 memory transfers",
            "label": ""
          },
          {
            "from": "pb",
            "to": "ar",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1 memory input",
            "label": ""
          },
          {
            "from": "control",
            "to": "memory",
            "type": "control",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1 MA address",
            "label": ""
          },
          {
            "from": "memory",
            "to": "control",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1 IR input",
            "label": ""
          },
          {
            "from": "fast",
            "to": "ar",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1",
            "label": ""
          },
          {
            "from": "io",
            "to": "ar",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1",
            "label": ""
          },
          {
            "from": "ar",
            "to": "io",
            "type": "data",
            "source": "hist-ka10-1968",
            "locator": "p. 4-1",
            "label": ""
          },
          {
            "from": "io",
            "to": "control",
            "type": "control",
            "source": "hist-ka10-1968",
            "locator": "p. 4-2 priority interrupt",
            "label": ""
          }
        ]
      },
      "originalCandidate": "PDP-10 / KA10"
    },
    {
      "id": "queue-042",
      "name": "DEC PDP-11/45 — 1973 memory-path configuration",
      "organization": "Digital Equipment Corporation",
      "year": 1973,
      "yearLabel": "1973 handbook",
      "kind": "16-bit minicomputer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "register-memory",
        "cisc"
      ],
      "substrates": [
        "integrated",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-pdp1145-1973"
      ],
      "summary": "The 11/45 combines banked general registers and three protection modes with independent CPU and UNIBUS paths into dual-port solid-state memory.",
      "config": "1973 CPU with memory management; diagram includes optional solid-state memory and optional floating-point processor. Core memory uses UNIBUS.",
      "gaps": [
        "The fast solid-state path is not a cache.",
        "Memory mix and FPU are explicit options; no specific installed total is inferred.",
        "CISC is an atlas classification of the documented operand-addressed instruction organization."
      ],
      "originalName": "DEC PDP-11/45",
      "insight": "How can a peripheral transfer and CPU memory operation proceed at the same time?",
      "fields": {
        "state": {
          "value": "16-bit words, byte addressing, two R0–R5 banks and mode stacks",
          "source": "hist-pdp1145-1973",
          "locator": "pp. 1–3, 11–13"
        },
        "compute": {
          "value": "Register/memory instruction operations; optional parallel FPU",
          "source": "hist-pdp1145-1973",
          "locator": "pp. 1–3, 14"
        },
        "memory": {
          "value": "Core via UNIBUS; optional MOS/bipolar through direct path",
          "source": "hist-pdp1145-1973",
          "locator": "pp. 15–16"
        },
        "control": {
          "value": "Kernel, supervisor and user modes; PSW and memory management",
          "source": "hist-pdp1145-1973",
          "locator": "pp. 2–3, 11–13"
        },
        "io": {
          "value": "Memory-mapped device registers and bus-master DMA",
          "source": "hist-pdp1145-1973",
          "locator": "pp. 3–5"
        },
        "software": {
          "value": "PDP-11 variable-length operand-addressed instructions and protected stacks",
          "source": "hist-pdp1145-1973",
          "locator": "pp. 1–5, 11–13"
        },
        "workload": {
          "value": "General-purpose protected multiprogramming and real-time I/O",
          "source": "hist-pdp1145-1973",
          "locator": "pp. 1–5"
        }
      },
      "diagram": {
        "title": "A direct CPU memory path alongside UNIBUS",
        "scope": "The second UNIBUS is normally joined to the first in a single-CPU system; independent use is a documented option.",
        "nodes": [
          {
            "id": "regs",
            "label": "General register banks",
            "subtitle": "16 PHYSICAL REGISTERS",
            "text": "Select working registers and mode-specific stacks.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1145-1973",
            "locator": "pp. 11–13",
            "control": false
          },
          {
            "id": "alu",
            "label": "CPU datapath",
            "subtitle": "16-BIT OPERATIONS",
            "text": "Executes arithmetic and address calculations.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1145-1973",
            "locator": "pp. 11–14",
            "control": false
          },
          {
            "id": "mmu",
            "label": "Memory management",
            "subtitle": "THREE PRIVILEGE MODES",
            "text": "Relocates and checks memory references.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1145-1973",
            "locator": "pp. 2–3, 11–13",
            "control": true
          },
          {
            "id": "ssm",
            "label": "Solid-state controller",
            "subtitle": "DUAL PORTS / OPTIONAL",
            "text": "Accepts direct CPU and second-UNIBUS requests.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1145-1973",
            "locator": "pp. 15–16",
            "control": false
          },
          {
            "id": "fast",
            "label": "MOS / bipolar memory",
            "subtitle": "OPTIONAL FAST STORE",
            "text": "Supplies words without first traversing UNIBUS.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1145-1973",
            "locator": "pp. 15–16",
            "control": false
          },
          {
            "id": "bus",
            "label": "UNIBUS / second bus",
            "subtitle": "ASYNCHRONOUS MASTERS",
            "text": "Carries device registers, DMA and core traffic.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1145-1973",
            "locator": "pp. 3–5, 15–16",
            "control": false
          },
          {
            "id": "core",
            "label": "Core memory",
            "subtitle": "UNIBUS MEMORY",
            "text": "Serves references through the shared bus.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1145-1973",
            "locator": "p. 16",
            "control": false
          },
          {
            "id": "devices",
            "label": "Peripheral controllers",
            "subtitle": "MAPPED REGISTERS / DMA",
            "text": "Arbitrate for transfers and signal interrupts.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1145-1973",
            "locator": "pp. 3–5",
            "control": false
          },
          {
            "id": "fpu",
            "label": "Floating-point processor",
            "subtitle": "OPTIONAL",
            "text": "Performs single/double arithmetic alongside CPU.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1145-1973",
            "locator": "p. 14",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "regs",
            "to": "alu",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "alu",
            "to": "regs",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "alu",
            "to": "mmu",
            "type": "control",
            "source": "hist-pdp1145-1973",
            "locator": "pp. 11–13",
            "label": ""
          },
          {
            "from": "mmu",
            "to": "ssm",
            "type": "control",
            "source": "hist-pdp1145-1973",
            "locator": "pp. 15–16 direct path",
            "label": ""
          },
          {
            "from": "alu",
            "to": "ssm",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "pp. 15–16 direct path",
            "label": ""
          },
          {
            "from": "ssm",
            "to": "alu",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "pp. 15–16",
            "label": ""
          },
          {
            "from": "ssm",
            "to": "fast",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "pp. 15–16",
            "label": ""
          },
          {
            "from": "fast",
            "to": "ssm",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "pp. 15–16",
            "label": ""
          },
          {
            "from": "bus",
            "to": "ssm",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "pp. 15–16 second port",
            "label": ""
          },
          {
            "from": "ssm",
            "to": "bus",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "pp. 15–16",
            "label": ""
          },
          {
            "from": "alu",
            "to": "bus",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "pp. 3–5",
            "label": ""
          },
          {
            "from": "bus",
            "to": "core",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "p. 16",
            "label": ""
          },
          {
            "from": "core",
            "to": "bus",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "p. 16",
            "label": ""
          },
          {
            "from": "devices",
            "to": "bus",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "pp. 3–5",
            "label": ""
          },
          {
            "from": "bus",
            "to": "devices",
            "type": "data",
            "source": "hist-pdp1145-1973",
            "locator": "pp. 3–5",
            "label": ""
          },
          {
            "from": "fpu",
            "to": "alu",
            "type": "association",
            "source": "hist-pdp1145-1973",
            "locator": "p. 14 parallel processor",
            "label": ""
          }
        ]
      },
      "originalCandidate": "PDP-11/45"
    },
    {
      "id": "queue-043",
      "name": "DEC PDP-11/70 — 1977–78 handbook system",
      "organization": "Digital Equipment Corporation",
      "year": 1977,
      "yearLabel": "1977–78 handbook edition",
      "kind": "Cached 16-bit minicomputer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "register-memory",
        "cisc"
      ],
      "substrates": [
        "integrated",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-pdp1170-1977"
      ],
      "summary": "A 2KiB write-through cache fronts the CPU, while high-speed controllers reach the separate memory bus without transferring their payload through cache storage.",
      "config": "CPU, standard mapping/cache and separate main-memory path; high-speed controllers and FPU are optional.",
      "gaps": [
        "22 address bits are not presented as an installed RAM capacity.",
        "High-speed I/O uses cache timing/control only, not the cache data array.",
        "CISC is an atlas classification of the documented PDP-11 instruction organization."
      ],
      "originalName": "DEC PDP-11/70",
      "insight": "Why can a DMA path pass through cache timing logic without being a cached data path?",
      "fields": {
        "state": {
          "value": "16-bit registers, mode stacks and byte-addressed ISA",
          "source": "hist-pdp1170-1977",
          "locator": "pp. 1-2–1-4"
        },
        "compute": {
          "value": "PDP-11 fixed arithmetic and optional floating point",
          "source": "hist-pdp1170-1977",
          "locator": "p. 1-2"
        },
        "memory": {
          "value": "2048-byte write-through cache; 22-bit physical addressing",
          "source": "hist-pdp1170-1977",
          "locator": "pp. 1-1, 1-5–1-7"
        },
        "control": {
          "value": "Three modes; memory mapping; CPU arbitrates UNIBUS",
          "source": "hist-pdp1170-1977",
          "locator": "pp. 1-2–1-4"
        },
        "io": {
          "value": "UNIBUS control plus dedicated 32-bit high-speed memory transfers",
          "source": "hist-pdp1170-1977",
          "locator": "pp. 1-1–1-2, Fig. 1-1"
        },
        "software": {
          "value": "Compatible PDP-11 instructions despite expanded memory paths",
          "source": "hist-pdp1170-1977",
          "locator": "p. 1-2"
        },
        "workload": {
          "value": "General-purpose multiuser and high-throughput peripheral service",
          "source": "hist-pdp1170-1977",
          "locator": "pp. 1-1–1-2"
        }
      },
      "diagram": {
        "title": "CPU cache and two differently routed peripheral paths",
        "scope": "Control registers remain on UNIBUS; a high-speed controller has a separate payload path to main memory.",
        "nodes": [
          {
            "id": "cpu",
            "label": "PDP-11 CPU",
            "subtitle": "16-BIT ISA",
            "text": "Executes compatible instructions and arbitrates UNIBUS.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1170-1977",
            "locator": "pp. 1-2–1-4",
            "control": false
          },
          {
            "id": "mmu",
            "label": "CPU memory mapping",
            "subtitle": "16 → 22 ADDRESS BITS",
            "text": "Maps processor virtual addresses.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1170-1977",
            "locator": "p. 1-1",
            "control": false
          },
          {
            "id": "cache",
            "label": "CPU cache",
            "subtitle": "2KiB / WRITE THROUGH",
            "text": "Serves CPU reads and updates main memory.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1170-1977",
            "locator": "pp. 1-5–1-7",
            "control": false
          },
          {
            "id": "timing",
            "label": "Memory timing / bus",
            "subtitle": "32-BIT DATA PATH",
            "text": "Arbitrates main-memory cycles, including DMA.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1170-1977",
            "locator": "pp. 1-1–1-2, Fig. 1-1",
            "control": false
          },
          {
            "id": "memory",
            "label": "Main memory",
            "subtitle": "SEPARATE MEMORY BUS",
            "text": "Retains authoritative stored words.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1170-1977",
            "locator": "pp. 1-1–1-2",
            "control": false
          },
          {
            "id": "map",
            "label": "UNIBUS map",
            "subtitle": "18 → 22 ADDRESS BITS",
            "text": "Translates ordinary UNIBUS memory requests.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1170-1977",
            "locator": "p. 1-1; Fig. 1-1",
            "control": false
          },
          {
            "id": "bus",
            "label": "UNIBUS",
            "subtitle": "CONTROL AND DEVICE I/O",
            "text": "Carries controller commands and normal bus transfers.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1170-1977",
            "locator": "p. 1-2",
            "control": false
          },
          {
            "id": "mass",
            "label": "High-speed controller",
            "subtitle": "OPTIONAL / UP TO FOUR",
            "text": "Sends payload via dedicated memory-side path.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1170-1977",
            "locator": "pp. 1-1–1-2",
            "control": false
          },
          {
            "id": "disk",
            "label": "Mass storage",
            "subtitle": "CONTROLLER-ATTACHED",
            "text": "Exchanges blocks with the optional controller.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-pdp1170-1977",
            "locator": "Fig. 1-1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu",
            "to": "mmu",
            "type": "control",
            "source": "hist-pdp1170-1977",
            "locator": "p. 1-1",
            "label": ""
          },
          {
            "from": "mmu",
            "to": "cache",
            "type": "control",
            "source": "hist-pdp1170-1977",
            "locator": "Fig. 1-1",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "cache",
            "type": "data",
            "source": "hist-pdp1170-1977",
            "locator": "p. 1-2",
            "label": ""
          },
          {
            "from": "cache",
            "to": "cpu",
            "type": "data",
            "source": "hist-pdp1170-1977",
            "locator": "p. 1-2",
            "label": ""
          },
          {
            "from": "cache",
            "to": "timing",
            "type": "data",
            "source": "hist-pdp1170-1977",
            "locator": "pp. 1-5–1-7",
            "label": ""
          },
          {
            "from": "timing",
            "to": "cache",
            "type": "data",
            "source": "hist-pdp1170-1977",
            "locator": "pp. 1-5–1-7",
            "label": ""
          },
          {
            "from": "timing",
            "to": "memory",
            "type": "data",
            "source": "hist-pdp1170-1977",
            "locator": "Fig. 1-1",
            "label": ""
          },
          {
            "from": "memory",
            "to": "timing",
            "type": "data",
            "source": "hist-pdp1170-1977",
            "locator": "Fig. 1-1",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "bus",
            "type": "control",
            "source": "hist-pdp1170-1977",
            "locator": "p. 1-2",
            "label": ""
          },
          {
            "from": "bus",
            "to": "map",
            "type": "control",
            "source": "hist-pdp1170-1977",
            "locator": "p. 1-1",
            "label": ""
          },
          {
            "from": "map",
            "to": "timing",
            "type": "data",
            "source": "hist-pdp1170-1977",
            "locator": "Fig. 1-1",
            "label": ""
          },
          {
            "from": "bus",
            "to": "mass",
            "type": "control",
            "source": "hist-pdp1170-1977",
            "locator": "p. 1-2 control/status",
            "label": ""
          },
          {
            "from": "mass",
            "to": "timing",
            "type": "data",
            "source": "hist-pdp1170-1977",
            "locator": "p. 1-2 cache used for timing only",
            "label": ""
          },
          {
            "from": "timing",
            "to": "mass",
            "type": "data",
            "source": "hist-pdp1170-1977",
            "locator": "p. 1-2",
            "label": ""
          },
          {
            "from": "mass",
            "to": "disk",
            "type": "data",
            "source": "hist-pdp1170-1977",
            "locator": "Fig. 1-1",
            "label": ""
          },
          {
            "from": "disk",
            "to": "mass",
            "type": "data",
            "source": "hist-pdp1170-1977",
            "locator": "Fig. 1-1",
            "label": ""
          }
        ]
      },
      "originalCandidate": "PDP-11/70"
    },
    {
      "id": "queue-044",
      "name": "DEC VAX-11/780 — KA780 organization",
      "organization": "Digital Equipment Corporation",
      "year": 1983,
      "yearLabel": "March 1983 maintenance edition",
      "kind": "Microprogrammed 32-bit computer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "register-memory",
        "cisc",
        "microcoded"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-vax780-1983"
      ],
      "summary": "Microcoded decimal, string and floating operations share a datapath, translation buffer and cache; SBI adapters isolate the processor from two peripheral bus families.",
      "config": "KA780 system documented in 1983; writable control store and floating-point accelerator are explicitly optional. Installed RAM total is unspecified.",
      "gaps": [
        "The CISC classification is supported by the documented combined decimal, string and floating instruction facilities, not a speed comparison.",
        "The 1983 handbook covers maintenance configurations; no original 1977 shipment memory count is inferred."
      ],
      "originalName": "DEC VAX-11/780",
      "insight": "How can one complex-instruction processor use a separate small computer as its console?",
      "fields": {
        "state": {
          "value": "32-bit processor datapath and memory data buses",
          "source": "hist-vax780-1983",
          "locator": "p. 9 KA780 block diagram"
        },
        "compute": {
          "value": "Floating-point, decimal and character-string instructions; optional FPA",
          "source": "hist-vax780-1983",
          "locator": "p. 7"
        },
        "memory": {
          "value": "Translation buffer, data cache and ECC MOS main memory",
          "source": "hist-vax780-1983",
          "locator": "pp. 7, 9"
        },
        "control": {
          "value": "ROM microcode, microsequencer, traps and interrupt arbiter",
          "source": "hist-vax780-1983",
          "locator": "p. 9"
        },
        "io": {
          "value": "SBI bridges to UNIBUS and MASSBUS adapters",
          "source": "hist-vax780-1983",
          "locator": "p. 7"
        },
        "software": {
          "value": "Microcoded complex instructions; separate LSI-11 console control",
          "source": "hist-vax780-1983",
          "locator": "pp. 7–9"
        },
        "workload": {
          "value": "General-purpose numeric, decimal and character processing",
          "source": "hist-vax780-1983",
          "locator": "p. 7"
        }
      },
      "diagram": {
        "title": "Microcode, address translation and an independent console",
        "scope": "The CPU-level paths follow the inspected KA780 figure; system-level I/O follows p. 7.",
        "nodes": [
          {
            "id": "decode",
            "label": "Instruction buffer / decode",
            "subtitle": "COMPLEX OPERATIONS",
            "text": "Supplies decoded instruction information.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-vax780-1983",
            "locator": "p. 9",
            "control": false
          },
          {
            "id": "micro",
            "label": "ROM / microsequencer",
            "subtitle": "OPTIONAL RAM CONTROL STORE",
            "text": "Sequences microinstructions and accepts traps.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-vax780-1983",
            "locator": "p. 9",
            "control": true
          },
          {
            "id": "data",
            "label": "KA780 datapath",
            "subtitle": "32-BIT INTERNAL DATA",
            "text": "Executes register and operand operations.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-vax780-1983",
            "locator": "p. 9",
            "control": false
          },
          {
            "id": "tlb",
            "label": "Translation buffer",
            "subtitle": "VIRTUAL → PHYSICAL",
            "text": "Translates addresses onto the physical address bus.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-vax780-1983",
            "locator": "p. 9",
            "control": false
          },
          {
            "id": "cache",
            "label": "Data cache",
            "subtitle": "CPU MEMORY DATA",
            "text": "Buffers processor data references.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-vax780-1983",
            "locator": "p. 9",
            "control": false
          },
          {
            "id": "sbi",
            "label": "SBI / memory controller",
            "subtitle": "ECC MOS MAIN MEMORY",
            "text": "Connects translated references to memory modules.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-vax780-1983",
            "locator": "pp. 7, 9",
            "control": false
          },
          {
            "id": "io",
            "label": "UNIBUS / MASSBUS adapters",
            "subtitle": "PERIPHERAL BRIDGES",
            "text": "Attach two different external I/O buses.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-vax780-1983",
            "locator": "p. 7",
            "control": false
          },
          {
            "id": "console",
            "label": "LSI-11 console subsystem",
            "subtitle": "Q-BUS / TERMINALS / FLOPPY",
            "text": "Controls diagnostics and console operations.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-vax780-1983",
            "locator": "pp. 7, 9",
            "control": false
          },
          {
            "id": "fpa",
            "label": "Floating-point accelerator",
            "subtitle": "OPTIONAL",
            "text": "Shares register and internal data paths.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-vax780-1983",
            "locator": "p. 9",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "decode",
            "to": "micro",
            "type": "control",
            "source": "hist-vax780-1983",
            "locator": "p. 9",
            "label": ""
          },
          {
            "from": "micro",
            "to": "data",
            "type": "control",
            "source": "hist-vax780-1983",
            "locator": "p. 9 control-store bus",
            "label": ""
          },
          {
            "from": "data",
            "to": "tlb",
            "type": "control",
            "source": "hist-vax780-1983",
            "locator": "p. 9 VA bus",
            "label": ""
          },
          {
            "from": "tlb",
            "to": "sbi",
            "type": "control",
            "source": "hist-vax780-1983",
            "locator": "p. 9 PA bus",
            "label": ""
          },
          {
            "from": "data",
            "to": "cache",
            "type": "data",
            "source": "hist-vax780-1983",
            "locator": "p. 9 MD bus",
            "label": ""
          },
          {
            "from": "cache",
            "to": "data",
            "type": "data",
            "source": "hist-vax780-1983",
            "locator": "p. 9 MD bus",
            "label": ""
          },
          {
            "from": "cache",
            "to": "sbi",
            "type": "data",
            "source": "hist-vax780-1983",
            "locator": "p. 9",
            "label": ""
          },
          {
            "from": "sbi",
            "to": "cache",
            "type": "data",
            "source": "hist-vax780-1983",
            "locator": "p. 9",
            "label": ""
          },
          {
            "from": "sbi",
            "to": "io",
            "type": "data",
            "source": "hist-vax780-1983",
            "locator": "p. 7",
            "label": ""
          },
          {
            "from": "io",
            "to": "sbi",
            "type": "data",
            "source": "hist-vax780-1983",
            "locator": "p. 7",
            "label": ""
          },
          {
            "from": "console",
            "to": "micro",
            "type": "control",
            "source": "hist-vax780-1983",
            "locator": "p. 9 console interface / microsequencer",
            "label": ""
          },
          {
            "from": "console",
            "to": "data",
            "type": "association",
            "source": "hist-vax780-1983",
            "locator": "p. 9 diagnostic signals",
            "label": ""
          },
          {
            "from": "data",
            "to": "fpa",
            "type": "data",
            "source": "hist-vax780-1983",
            "locator": "p. 9 GRD / VB / ID paths",
            "label": ""
          },
          {
            "from": "fpa",
            "to": "data",
            "type": "data",
            "source": "hist-vax780-1983",
            "locator": "p. 9",
            "label": ""
          }
        ]
      },
      "originalCandidate": "VAX-11/780"
    },
    {
      "id": "queue-045",
      "name": "Data General Nova — original 1969 datapath",
      "organization": "Data General Corporation",
      "year": 1969,
      "yearLabel": "1969 maintenance manual",
      "kind": "Four-bit datapath minicomputer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "register-memory",
        "hardwired"
      ],
      "substrates": [
        "integrated",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-nova-1969"
      ],
      "summary": "Four architectural accumulators are implemented around a central MA register and an adder that processes most 16-bit transfers in four-bit steps.",
      "config": "Original Nova CPU, with core memory and I/O-bus/data-channel facilities; later Supernova full-width arithmetic excluded.",
      "gaps": [
        "No installed core capacity is inferred from the manual’s example power calculation.",
        "The original four-bit datapath is deliberately distinguished from later Nova-family implementations."
      ],
      "originalName": "Data General Nova",
      "insight": "Why are the program’s four accumulators not the physical arithmetic accumulator?",
      "fields": {
        "state": {
          "value": "Four program-visible ACs; internal MA, MB, PC and IR",
          "source": "hist-nova-1969",
          "locator": "pp. 2–4"
        },
        "compute": {
          "value": "Most transfers and all arithmetic process four bits in four steps",
          "source": "hist-nova-1969",
          "locator": "p. 3"
        },
        "memory": {
          "value": "Core modules reached over a separate memory bus",
          "source": "hist-nova-1969",
          "locator": "pp. 1, 4"
        },
        "control": {
          "value": "Fetch, defer, execute, data-channel and interrupt states",
          "source": "hist-nova-1969",
          "locator": "p. 3"
        },
        "io": {
          "value": "16-bit parallel I/O; data-channel payload can load MB directly",
          "source": "hist-nova-1969",
          "locator": "p. 3"
        },
        "software": {
          "value": "Stored Nova instructions; indirect program interrupt through locations 0/1",
          "source": "hist-nova-1969",
          "locator": "p. 3"
        },
        "workload": {
          "value": "General-purpose small-computer and peripheral-control tasks",
          "source": "hist-nova-1969",
          "locator": "pp. 1–4"
        }
      },
      "diagram": {
        "title": "Architectural accumulators around the real MA arithmetic register",
        "scope": "Processor data-flow figure p. 4 and explanation pp. 2–3 determine the directed transfers.",
        "nodes": [
          {
            "id": "acs",
            "label": "Four architectural ACs",
            "subtitle": "PROGRAM-VISIBLE REGISTERS",
            "text": "Supply operands and receive shifted/swapped results.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-nova-1969",
            "locator": "pp. 2, 4",
            "control": false
          },
          {
            "id": "adder",
            "label": "Adder / transfer link",
            "subtitle": "FOUR BITS AT A TIME",
            "text": "Performs arithmetic and most register transfers.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-nova-1969",
            "locator": "pp. 2–4",
            "control": false
          },
          {
            "id": "ma",
            "label": "MA register",
            "subtitle": "ADDRESS AND ARITHMETIC",
            "text": "Acts as the central physical accumulator.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-nova-1969",
            "locator": "pp. 2–4",
            "control": false
          },
          {
            "id": "mb",
            "label": "Memory buffer",
            "subtitle": "WORD TRANSFER",
            "text": "Holds memory and direct data-channel input.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-nova-1969",
            "locator": "pp. 3–4",
            "control": false
          },
          {
            "id": "pc",
            "label": "Program counter",
            "subtitle": "SEQUENCE ADDRESS",
            "text": "Loads directly from MB when required.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-nova-1969",
            "locator": "pp. 3–4",
            "control": false
          },
          {
            "id": "ir",
            "label": "Instruction register",
            "subtitle": "MEMORY-BUS INPUT",
            "text": "Captures the instruction operation.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-nova-1969",
            "locator": "pp. 3–4",
            "control": false
          },
          {
            "id": "memory",
            "label": "Memory bus / core",
            "subtitle": "SEPARATE MEMORY PATH",
            "text": "Exchanges words with processor transfer logic.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-nova-1969",
            "locator": "pp. 1, 4",
            "control": false
          },
          {
            "id": "io",
            "label": "I/O bus interface",
            "subtitle": "16-BIT PARALLEL",
            "text": "Outputs MA; inputs programmed data to MA.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-nova-1969",
            "locator": "pp. 3–4",
            "control": false
          },
          {
            "id": "states",
            "label": "DCH / interrupt control",
            "subtitle": "PRIORITY AND MAJOR STATES",
            "text": "Gives data-channel requests priority over interrupts.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-nova-1969",
            "locator": "p. 3",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "acs",
            "to": "adder",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "pp. 2, 4",
            "label": ""
          },
          {
            "from": "adder",
            "to": "acs",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "pp. 2, 4",
            "label": ""
          },
          {
            "from": "ma",
            "to": "adder",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "pp. 2, 4",
            "label": ""
          },
          {
            "from": "adder",
            "to": "ma",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "pp. 2, 4",
            "label": ""
          },
          {
            "from": "mb",
            "to": "adder",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "p. 4",
            "label": ""
          },
          {
            "from": "pc",
            "to": "adder",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "p. 4",
            "label": ""
          },
          {
            "from": "mb",
            "to": "pc",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "p. 3 transfer exception",
            "label": ""
          },
          {
            "from": "memory",
            "to": "ir",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "p. 3 transfer exception",
            "label": ""
          },
          {
            "from": "memory",
            "to": "adder",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "p. 4",
            "label": ""
          },
          {
            "from": "adder",
            "to": "memory",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "p. 4",
            "label": ""
          },
          {
            "from": "ma",
            "to": "io",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "p. 3 all output",
            "label": ""
          },
          {
            "from": "io",
            "to": "ma",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "p. 3 programmed input",
            "label": ""
          },
          {
            "from": "io",
            "to": "mb",
            "type": "data",
            "source": "hist-nova-1969",
            "locator": "p. 3 data-channel input",
            "label": ""
          },
          {
            "from": "io",
            "to": "states",
            "type": "control",
            "source": "hist-nova-1969",
            "locator": "p. 3 DCH / PI",
            "label": ""
          },
          {
            "from": "states",
            "to": "pc",
            "type": "control",
            "source": "hist-nova-1969",
            "locator": "p. 3 interrupt sequence",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Data General Nova"
    },
    {
      "id": "queue-046",
      "name": "HP 3000 Series II Model 9 — 1976",
      "organization": "Hewlett-Packard",
      "year": 1976,
      "yearLabel": "August 1976 manufacturer design account",
      "kind": "Segmented stack computer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "stack"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-hp3000-series2-1976"
      ],
      "summary": "Protected variable-size code/data segments retain the stack-machine interface while privileged bank registers extend physical memory and ECC hardware logs failing components.",
      "config": "Series II Model 9 standard package: 320K-byte fault-control memory, two 47MB disks, tape, console and 16-port asynchronous controller.",
      "gaps": [
        "Four banks of up to 64K words describe architectural capacity, not the Model 9 installed 320K-byte package.",
        "The diagram is a functional composition of the processor and memory designer articles; no undocumented bus protocol is inferred."
      ],
      "originalName": "HP 3000",
      "insight": "How can physical memory grow beyond a 16-bit address without changing user instructions?",
      "fields": {
        "state": {
          "value": "16-bit stack words and automatic top-of-stack registers",
          "source": "hist-hp3000-series2-1976",
          "locator": "pp. 3, 9"
        },
        "compute": {
          "value": "Stack-oriented execution within protected code/data segments",
          "source": "hist-hp3000-series2-1976",
          "locator": "pp. 3–4"
        },
        "memory": {
          "value": "Model 9: 320K bytes; four-bank architectural scheme; single-bit ECC",
          "source": "hist-hp3000-series2-1976",
          "locator": "pp. 4, 7, 9–10"
        },
        "control": {
          "value": "MPE-controlled bases, bounds and three privileged bank registers",
          "source": "hist-hp3000-series2-1976",
          "locator": "pp. 3–5"
        },
        "io": {
          "value": "I/O processor, multiplexer and selector channels set a transfer bank",
          "source": "hist-hp3000-series2-1976",
          "locator": "pp. 4–5"
        },
        "software": {
          "value": "MPE segments/schedules users; IMAGE and five languages in Model 9",
          "source": "hist-hp3000-series2-1976",
          "locator": "pp. 3–7"
        },
        "workload": {
          "value": "Concurrent terminal, batch and database processing",
          "source": "hist-hp3000-series2-1976",
          "locator": "pp. 2, 7"
        }
      },
      "diagram": {
        "title": "Stack segments, privileged bank selection and corrected physical words",
        "scope": "The boundaries are functional roles; ECC paths follow pp. 9–10 and the segment scheme follows pp. 3–5.",
        "nodes": [
          {
            "id": "stack",
            "label": "Stack execution",
            "subtitle": "TOP-OF-STACK REGISTERS",
            "text": "Executes user operations on protected stack state.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-hp3000-series2-1976",
            "locator": "p. 3",
            "control": false
          },
          {
            "id": "bounds",
            "label": "Segment bases / bounds",
            "subtitle": "DL / DB / Z / Q / S / PB / PL",
            "text": "Delimit user data and executable code.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 3–4",
            "control": false
          },
          {
            "id": "banks",
            "label": "Three bank registers",
            "subtitle": "STACK / DB / PB BANK",
            "text": "Append physical bank selection after bounds checks.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-hp3000-series2-1976",
            "locator": "p. 4",
            "control": true
          },
          {
            "id": "mpe",
            "label": "MPE supervisor",
            "subtitle": "PRIVILEGED PLACEMENT",
            "text": "Moves segments and sets protected addressing state.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 3–6",
            "control": true
          },
          {
            "id": "ecc",
            "label": "Memory control / correction",
            "subtitle": "MCL + FCA",
            "text": "Generates check bits and corrects single-bit errors.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 9–10",
            "control": false
          },
          {
            "id": "ram",
            "label": "Semiconductor arrays",
            "subtitle": "16 DATA + 5 CHECK BITS",
            "text": "Store data and distributed check-bit information.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 8–10",
            "control": false
          },
          {
            "id": "channels",
            "label": "I/O processor / channels",
            "subtitle": "SET-BANK OPERATION",
            "text": "Transfer segments through the selected bank.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 4–5",
            "control": false
          },
          {
            "id": "disk",
            "label": "Disk / terminal peripherals",
            "subtitle": "MODEL 9 PACKAGE",
            "text": "Supply backing storage and interactive sessions.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-hp3000-series2-1976",
            "locator": "p. 7",
            "control": false
          },
          {
            "id": "log",
            "label": "Error logging RAM",
            "subtitle": "PHYSICAL FAILURE ID",
            "text": "Records failing board, RAM row and bit information.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-hp3000-series2-1976",
            "locator": "p. 10",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "stack",
            "to": "bounds",
            "type": "control",
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 3–4",
            "label": ""
          },
          {
            "from": "bounds",
            "to": "banks",
            "type": "control",
            "source": "hist-hp3000-series2-1976",
            "locator": "p. 4 bounds then bank",
            "label": ""
          },
          {
            "from": "banks",
            "to": "ecc",
            "type": "control",
            "source": "hist-hp3000-series2-1976",
            "locator": "p. 4 physical location",
            "label": ""
          },
          {
            "from": "stack",
            "to": "ecc",
            "type": "data",
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 3–4, 9 processor memory operations",
            "label": ""
          },
          {
            "from": "ecc",
            "to": "stack",
            "type": "data",
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 3–4, 9–10 corrected reads",
            "label": ""
          },
          {
            "from": "ecc",
            "to": "ram",
            "type": "data",
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 9–10",
            "label": ""
          },
          {
            "from": "ram",
            "to": "ecc",
            "type": "data",
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 9–10",
            "label": ""
          },
          {
            "from": "mpe",
            "to": "bounds",
            "type": "control",
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 3–4",
            "label": ""
          },
          {
            "from": "mpe",
            "to": "banks",
            "type": "control",
            "source": "hist-hp3000-series2-1976",
            "locator": "p. 4",
            "label": ""
          },
          {
            "from": "mpe",
            "to": "channels",
            "type": "control",
            "source": "hist-hp3000-series2-1976",
            "locator": "p. 5 new channel instruction",
            "label": ""
          },
          {
            "from": "channels",
            "to": "ram",
            "type": "data",
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 4–5 I/O to/from memory",
            "label": ""
          },
          {
            "from": "ram",
            "to": "channels",
            "type": "data",
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 4–5",
            "label": ""
          },
          {
            "from": "channels",
            "to": "disk",
            "type": "data",
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 5, 7",
            "label": ""
          },
          {
            "from": "disk",
            "to": "channels",
            "type": "data",
            "source": "hist-hp3000-series2-1976",
            "locator": "pp. 5, 7",
            "label": ""
          },
          {
            "from": "ecc",
            "to": "log",
            "type": "control",
            "source": "hist-hp3000-series2-1976",
            "locator": "p. 10 error code / address",
            "label": ""
          }
        ]
      },
      "originalCandidate": "HP 3000"
    },
    {
      "id": "queue-047",
      "name": "Apollo Guidance Computer — Block II",
      "organization": "MIT Instrumentation Laboratory / Raytheon / NASA",
      "year": 1972,
      "yearLabel": "1972 final designer report on flown Block II",
      "kind": "Spacecraft guidance computer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator",
        "hardwired"
      ],
      "substrates": [
        "integrated",
        "magnetic"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-agc-block2-r700"
      ],
      "summary": "The Block II computer combines rope and erasable core storage in one instruction space, with a shared write bus, special registers and involuntary priority sequences for spacecraft I/O.",
      "config": "Flight-generation Block II architecture: 36,864 fixed and 2048 erasable words. Block I timings and capacities excluded.",
      "gaps": [
        "Microprogram means a sequence of generated control pulses here; no writable control-store RAM is inferred.",
        "This is architectural coverage of flown Block II, not a claim about an individual serial-number computer."
      ],
      "originalName": "Apollo Guidance Computer Block II",
      "insight": "Why is a machine with separate fixed and erasable stores still a common-storage computer?",
      "fields": {
        "state": {
          "value": "15-bit one’s-complement data plus parity in 16-bit memory words",
          "source": "hist-agc-block2-r700",
          "locator": "pp. 32–34"
        },
        "compute": {
          "value": "A/L accumulators and single adder with Block II carry-skip logic",
          "source": "hist-agc-block2-r700",
          "locator": "pp. 67–69"
        },
        "memory": {
          "value": "36,864 fixed rope words; 2048 erasable core words",
          "source": "hist-agc-block2-r700",
          "locator": "p. 29"
        },
        "control": {
          "value": "Clocked sequence pulses, instruction decoding and priority interrupts",
          "source": "hist-agc-block2-r700",
          "locator": "p. 29; Fig. 2-4"
        },
        "io": {
          "value": "Addressed I/O channels, counters and DSKY keyboard/display",
          "source": "hist-agc-block2-r700",
          "locator": "pp. 29–31, 69"
        },
        "software": {
          "value": "Instructions may execute from fixed or erasable memory",
          "source": "hist-agc-block2-r700",
          "locator": "p. 32"
        },
        "workload": {
          "value": "Apollo guidance, navigation and spacecraft control",
          "source": "hist-agc-block2-r700",
          "locator": "Abstract; p. 29"
        }
      },
      "diagram": {
        "title": "Common storage through G, S and the shared write bus",
        "scope": "Original Figure 2-4 and pp. 67–69 define the connections; X’s special direct A input is retained inside the arithmetic node.",
        "nodes": [
          {
            "id": "fixed",
            "label": "Fixed rope memory",
            "subtitle": "36,864 WORDS",
            "text": "Supplies constants and stored instruction words.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-agc-block2-r700",
            "locator": "p. 29; Fig. 2-4",
            "control": false
          },
          {
            "id": "g",
            "label": "G memory buffer",
            "subtitle": "PARITY / SHIFT / CYCLE",
            "text": "Receives fixed reads and mediates erasable words.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-agc-block2-r700",
            "locator": "pp. 29, 67; Fig. 2-4",
            "control": false
          },
          {
            "id": "erase",
            "label": "Erasable core memory",
            "subtitle": "2048 WORDS",
            "text": "Retains mutable data and executable instructions.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-agc-block2-r700",
            "locator": "pp. 29, 32",
            "control": false
          },
          {
            "id": "address",
            "label": "S and bank registers",
            "subtitle": "S / EB / FB",
            "text": "Select memory locations and banked windows.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-agc-block2-r700",
            "locator": "pp. 29–30, 67",
            "control": false
          },
          {
            "id": "bus",
            "label": "Read / write buses",
            "subtitle": "16 SHARED LINES",
            "text": "Move words among connected special registers.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-agc-block2-r700",
            "locator": "pp. 29, 69",
            "control": false
          },
          {
            "id": "regs",
            "label": "A / L / Q / Z",
            "subtitle": "SPECIAL CENTRAL REGISTERS",
            "text": "Hold accumulators, return and sequence addresses.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-agc-block2-r700",
            "locator": "pp. 30, 67",
            "control": false
          },
          {
            "id": "arithmetic",
            "label": "X / Y / adder",
            "subtitle": "CARRY-SKIP ARITHMETIC",
            "text": "Computes sums and assists multiply/divide.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-agc-block2-r700",
            "locator": "pp. 67–69",
            "control": false
          },
          {
            "id": "sequence",
            "label": "SQ / sequence / timing",
            "subtitle": "HARDWIRED CONTROL PULSES",
            "text": "Sequences instructions, memory and priority service.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-agc-block2-r700",
            "locator": "p. 29; Fig. 2-4",
            "control": true
          },
          {
            "id": "io",
            "label": "I/O channels / DSKY",
            "subtitle": "COUNTERS AND PRIORITY",
            "text": "Connect operator requests and spacecraft signals.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-agc-block2-r700",
            "locator": "pp. 29–31, 69",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "address",
            "to": "fixed",
            "type": "control",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "address",
            "to": "erase",
            "type": "control",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "fixed",
            "to": "g",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "erase",
            "to": "g",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "g",
            "to": "erase",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "g",
            "to": "bus",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "bus",
            "to": "g",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "regs",
            "to": "bus",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "bus",
            "to": "regs",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "regs",
            "to": "arithmetic",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "p. 69 dedicated A→X",
            "label": ""
          },
          {
            "from": "bus",
            "to": "arithmetic",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "arithmetic",
            "to": "bus",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "bus",
            "to": "address",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "bus",
            "to": "sequence",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4 SQ",
            "label": ""
          },
          {
            "from": "sequence",
            "to": "regs",
            "type": "control",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "sequence",
            "to": "g",
            "type": "control",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4 memory timing",
            "label": ""
          },
          {
            "from": "io",
            "to": "bus",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "bus",
            "to": "io",
            "type": "data",
            "source": "hist-agc-block2-r700",
            "locator": "Fig. 2-4",
            "label": ""
          },
          {
            "from": "io",
            "to": "sequence",
            "type": "control",
            "source": "hist-agc-block2-r700",
            "locator": "p. 29 priority circuits",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Apollo Guidance Computer Block II"
    },
    {
      "id": "queue-048",
      "name": "IBM PC 5150 — August 1981 16KB base board",
      "organization": "IBM",
      "year": 1981,
      "yearLabel": "August 1981 technical reference",
      "kind": "Expandable personal computer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "register-memory",
        "cisc"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-ibmpc-1981"
      ],
      "summary": "An 8088 exposes an 8-bit system channel around a 16-bit instruction architecture; timer-driven DMA refresh lets inexpensive DRAM coexist with processor and card transfers.",
      "config": "Original 16–64KB motherboard with base 16KB fitted and 40KB ROM; display/diskette and memory cards are options. Later 64–256KB board excluded.",
      "gaps": [
        "The 1981 reference’s expansion ceiling is 256KB; a later 640KB configuration is not retroactively assigned.",
        "A display adapter is required for a usable displayed system but is an expansion option; the diagram shows the system-board boundary."
      ],
      "originalName": "IBM PC 5150",
      "insight": "Why does one DMA channel periodically transfer data that no application requested?",
      "fields": {
        "state": {
          "value": "8088 16-bit operations over an 8-bit external bus",
          "source": "hist-ibmpc-1981",
          "locator": "p. 2-3"
        },
        "compute": {
          "value": "4.77MHz 8088; optional auxiliary processor socket",
          "source": "hist-ibmpc-1981",
          "locator": "p. 2-3"
        },
        "memory": {
          "value": "Base 16KB parity DRAM; 40KB populated ROM",
          "source": "hist-ibmpc-1981",
          "locator": "p. 2-4"
        },
        "control": {
          "value": "8259A interrupts, DMA arbitration and timer-driven refresh",
          "source": "hist-ibmpc-1981",
          "locator": "pp. 2-4, 2-6"
        },
        "io": {
          "value": "Five expansion slots plus keyboard, cassette and speaker",
          "source": "hist-ibmpc-1981",
          "locator": "pp. 2-3–2-5"
        },
        "software": {
          "value": "ROM cassette BASIC, POST, I/O drivers and diskette bootstrap",
          "source": "hist-ibmpc-1981",
          "locator": "p. 2-4"
        },
        "workload": {
          "value": "Personal BASIC, data/word processing and expandable peripheral use",
          "source": "hist-ibmpc-1981",
          "locator": "pp. 1-1–1-3, 2-4"
        }
      },
      "diagram": {
        "title": "An 8-bit channel, parity RAM and DMA-generated refresh",
        "scope": "Board-level roles follow pp. 2-3–2-7; timer channel numbering in the prose is not copied because it differs from customary later descriptions.",
        "nodes": [
          {
            "id": "cpu",
            "label": "Intel 8088",
            "subtitle": "4.77MHz / 16-BIT ISA",
            "text": "Executes instructions through an 8-bit external bus.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-3",
            "control": false
          },
          {
            "id": "bus",
            "label": "Buffers / system channel",
            "subtitle": "20 ADDRESS / 8 DATA",
            "text": "Carries addressed memory and I/O transactions.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ibmpc-1981",
            "locator": "pp. 2-6–2-7",
            "control": false
          },
          {
            "id": "ram",
            "label": "Parity DRAM",
            "subtitle": "16KB FITTED",
            "text": "Holds programs and mutable state.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-4",
            "control": false
          },
          {
            "id": "rom",
            "label": "System ROM",
            "subtitle": "40KB POPULATED",
            "text": "Supplies BASIC, POST, drivers and bootstrap.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-4",
            "control": false
          },
          {
            "id": "dma",
            "label": "DMA controller",
            "subtitle": "FOUR CHANNELS",
            "text": "Arbitrates device transfers and dummy refresh reads.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-4",
            "control": false
          },
          {
            "id": "timer",
            "label": "Timer / counters",
            "subtitle": "PERIODIC REQUESTS",
            "text": "Generate refresh timing, system tick and speaker tone.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-ibmpc-1981",
            "locator": "pp. 2-4–2-5",
            "control": false
          },
          {
            "id": "pic",
            "label": "8259A interrupt controller",
            "subtitle": "EIGHT PRIORITY LEVELS",
            "text": "Combines timer, keyboard and card interrupts.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ibmpc-1981",
            "locator": "pp. 2-4, 2-6",
            "control": true
          },
          {
            "id": "onboard",
            "label": "Keyboard / cassette / speaker",
            "subtitle": "ON-BOARD I/O",
            "text": "Exchange scan codes, audio data and sound.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-5",
            "control": false
          },
          {
            "id": "slots",
            "label": "Five expansion slots",
            "subtitle": "DISPLAY / DISK / MEMORY OPTIONS",
            "text": "Expose the channel to optional adapters.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-ibmpc-1981",
            "locator": "pp. 1-1–1-4, 2-3",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu",
            "to": "bus",
            "type": "data",
            "source": "hist-ibmpc-1981",
            "locator": "pp. 2-6–2-7",
            "label": ""
          },
          {
            "from": "bus",
            "to": "cpu",
            "type": "data",
            "source": "hist-ibmpc-1981",
            "locator": "pp. 2-6–2-7",
            "label": ""
          },
          {
            "from": "bus",
            "to": "ram",
            "type": "data",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-7",
            "label": ""
          },
          {
            "from": "ram",
            "to": "bus",
            "type": "data",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-7",
            "label": ""
          },
          {
            "from": "rom",
            "to": "bus",
            "type": "data",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-7",
            "label": ""
          },
          {
            "from": "timer",
            "to": "dma",
            "type": "control",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-4 refresh request",
            "label": ""
          },
          {
            "from": "dma",
            "to": "bus",
            "type": "control",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-4 memory cycles",
            "label": ""
          },
          {
            "from": "slots",
            "to": "dma",
            "type": "control",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-4 DMA requests",
            "label": ""
          },
          {
            "from": "slots",
            "to": "bus",
            "type": "data",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-3",
            "label": ""
          },
          {
            "from": "bus",
            "to": "slots",
            "type": "data",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-3",
            "label": ""
          },
          {
            "from": "onboard",
            "to": "pic",
            "type": "control",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-4 keyboard IRQ",
            "label": ""
          },
          {
            "from": "timer",
            "to": "pic",
            "type": "control",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-4 periodic IRQ",
            "label": ""
          },
          {
            "from": "pic",
            "to": "cpu",
            "type": "control",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-6",
            "label": ""
          },
          {
            "from": "bus",
            "to": "onboard",
            "type": "data",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-5",
            "label": ""
          },
          {
            "from": "onboard",
            "to": "bus",
            "type": "data",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-5",
            "label": ""
          },
          {
            "from": "timer",
            "to": "onboard",
            "type": "control",
            "source": "hist-ibmpc-1981",
            "locator": "p. 2-5 speaker waveform",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IBM PC 5150"
    },
    {
      "id": "queue-049",
      "name": "Apple II — January 1978 48KB configuration",
      "organization": "Apple Computer",
      "year": 1978,
      "yearLabel": "January 1978 original reference",
      "kind": "Personal computer with shared video memory",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "accumulator",
        "hardwired"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-apple2-redbook"
      ],
      "summary": "The 6502 and video circuitry share dynamic RAM selection, while common oscillator and sync-counter logic produce processor, memory and composite-video timing.",
      "config": "Original Apple II with three 16KB RAM rows (48KB); original ROM/Integer BASIC era, before Apple II Plus and language-card banking.",
      "gaps": [
        "The 48KB choice is a representative supported configuration; mixed 4KB/16KB rows were also allowed.",
        "No Disk II controller is included in this January 1978 baseline.",
        "The diagram abstracts gate-level schematics; it does not claim an independent graphics processor."
      ],
      "originalName": "Apple II",
      "insight": "How do the video counters become memory addresses and later become pixels?",
      "fields": {
        "state": {
          "value": "8-bit data and 16-bit 6502 addresses",
          "source": "hist-apple2-redbook",
          "locator": "Memory p. 134; I/O bus pin descriptions"
        },
        "compute": {
          "value": "6502 at approximately 1.023MHz",
          "source": "hist-apple2-redbook",
          "locator": "Processor clock pin description; Fig. S-3"
        },
        "memory": {
          "value": "Three RAM rows selected by 4K/16K jumper blocks; 48KB configuration",
          "source": "hist-apple2-redbook",
          "locator": "pp. 134–135; Fig. S-6"
        },
        "control": {
          "value": "Common oscillator, sync counters and address-decode soft switches",
          "source": "hist-apple2-redbook",
          "locator": "Figs. S-3, S-4, S-6, S-10"
        },
        "io": {
          "value": "Keyboard, cassette, speaker, game I/O and expansion bus",
          "source": "hist-apple2-redbook",
          "locator": "Fig. S-10; I/O bus descriptions"
        },
        "software": {
          "value": "ROM monitor and original Apple II BASIC routines",
          "source": "hist-apple2-redbook",
          "locator": "ROM listings; Fig. S-5"
        },
        "workload": {
          "value": "Interactive BASIC, text and color graphics",
          "source": "hist-apple2-redbook",
          "locator": "Getting Started; graphics and memory-map sections"
        }
      },
      "diagram": {
        "title": "Video timing shares RAM selection with the 6502",
        "scope": "Original schematic signal names establish the clock, address-select, latched-data and video paths.",
        "nodes": [
          {
            "id": "cpu",
            "label": "6502 processor",
            "subtitle": "8 DATA / 16 ADDRESS",
            "text": "Runs stored instructions using the system bus.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-apple2-redbook",
            "locator": "Memory p. 134; I/O bus pin descriptions",
            "control": false
          },
          {
            "id": "bus",
            "label": "System bus",
            "subtitle": "ADDRESS / DATA",
            "text": "Links CPU, ROM and decoded I/O.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-apple2-redbook",
            "locator": "Figs. S-5, S-6, S-10",
            "control": false
          },
          {
            "id": "rom",
            "label": "ROM array",
            "subtitle": "MONITOR / BASIC ERA",
            "text": "Drives selected instruction and routine bytes.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-5",
            "control": false
          },
          {
            "id": "ram",
            "label": "Three dynamic RAM rows",
            "subtitle": "48KB CONFIGURATION",
            "text": "Supply working and display data.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-apple2-redbook",
            "locator": "pp. 134–135; Fig. S-6",
            "control": false
          },
          {
            "id": "select",
            "label": "RAM address selection",
            "subtitle": "JUMPERS / VIDEO MODES",
            "text": "Combines address and mode inputs for row/column select.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-6",
            "control": false
          },
          {
            "id": "timing",
            "label": "Oscillator / sync counters",
            "subtitle": "CPU / MEMORY / VIDEO CLOCKS",
            "text": "Generate phase clocks and scan address signals.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-apple2-redbook",
            "locator": "Figs. S-3–S-4",
            "control": true
          },
          {
            "id": "video",
            "label": "Latched data / video generator",
            "subtitle": "CHARACTER / PIXEL SERIALIZATION",
            "text": "Converts RAM data into composite video.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-11",
            "control": false
          },
          {
            "id": "decode",
            "label": "Address-decode switches",
            "subtitle": "TEXT / MIX / PAGE / HIRES",
            "text": "Latch display mode and select on-board functions.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-10",
            "control": false
          },
          {
            "id": "io",
            "label": "Keyboard / cassette / game / sound",
            "subtitle": "ON-BOARD AND EXPANSION I/O",
            "text": "Exchange input bits and output transitions.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-10; I/O bus descriptions",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu",
            "to": "bus",
            "type": "data",
            "source": "hist-apple2-redbook",
            "locator": "I/O bus descriptions",
            "label": ""
          },
          {
            "from": "bus",
            "to": "cpu",
            "type": "data",
            "source": "hist-apple2-redbook",
            "locator": "I/O bus descriptions",
            "label": ""
          },
          {
            "from": "rom",
            "to": "bus",
            "type": "data",
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-5",
            "label": ""
          },
          {
            "from": "bus",
            "to": "select",
            "type": "control",
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-6 AD inputs",
            "label": ""
          },
          {
            "from": "timing",
            "to": "select",
            "type": "control",
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-6 phase/sync inputs",
            "label": ""
          },
          {
            "from": "select",
            "to": "ram",
            "type": "control",
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-6",
            "label": ""
          },
          {
            "from": "ram",
            "to": "video",
            "type": "data",
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-11 latched RAM data",
            "label": ""
          },
          {
            "from": "ram",
            "to": "bus",
            "type": "data",
            "source": "hist-apple2-redbook",
            "locator": "Memory pp. 134–135; system-bus schematics",
            "label": ""
          },
          {
            "from": "bus",
            "to": "ram",
            "type": "data",
            "source": "hist-apple2-redbook",
            "locator": "Memory pp. 134–135",
            "label": ""
          },
          {
            "from": "timing",
            "to": "cpu",
            "type": "control",
            "source": "hist-apple2-redbook",
            "locator": "clock pin description; Fig. S-3",
            "label": ""
          },
          {
            "from": "timing",
            "to": "video",
            "type": "control",
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-11",
            "label": ""
          },
          {
            "from": "bus",
            "to": "decode",
            "type": "control",
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-10",
            "label": ""
          },
          {
            "from": "decode",
            "to": "select",
            "type": "control",
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-6 mode inputs",
            "label": ""
          },
          {
            "from": "decode",
            "to": "video",
            "type": "control",
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-11 mode inputs",
            "label": ""
          },
          {
            "from": "io",
            "to": "bus",
            "type": "data",
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-10",
            "label": ""
          },
          {
            "from": "decode",
            "to": "io",
            "type": "control",
            "source": "hist-apple2-redbook",
            "locator": "Fig. S-10",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Apple II"
    },
    {
      "id": "queue-050",
      "name": "Apple Macintosh 128K — original hardware",
      "organization": "Apple Computer",
      "year": 1984,
      "yearLabel": "Original 128K model, documented in 1985",
      "kind": "Integrated graphical personal computer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "register-memory",
        "cisc"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-mac128-inside3"
      ],
      "summary": "CPU, monochrome video, sound and disk-speed control share scheduled accesses to working RAM; ROM supplies the Toolbox and operating-system routines.",
      "config": "Original 128K Macintosh with original ROM interface, 512×342 display and IWM disk controller; 512K-specific offsets and later Plus/SE changes excluded.",
      "gaps": [
        "No MMU or cache is inferred from the MC68000’s address-space size.",
        "The chapter covers two RAM capacities; this record retains only the 128K mapping and buffers."
      ],
      "originalName": "Apple Macintosh 128K",
      "insight": "Why does the processor’s available RAM bandwidth depend on where the display beam is?",
      "fields": {
        "state": {
          "value": "MC68000 registers, RAM heaps, stack and exception vectors",
          "source": "hist-mac128-inside3",
          "locator": "p. III-17"
        },
        "compute": {
          "value": "7.8336MHz MC68000; memory-mapped device operations",
          "source": "hist-mac128-inside3",
          "locator": "p. III-17"
        },
        "memory": {
          "value": "128K working RAM; shared screen/sound buffers and system ROM",
          "source": "hist-mac128-inside3",
          "locator": "pp. III-17–III-21"
        },
        "control": {
          "value": "Alternating CPU/video RAM cycles during active scan",
          "source": "hist-mac128-inside3",
          "locator": "p. III-18"
        },
        "io": {
          "value": "VIA mouse/keyboard, SCC serial and IWM disk control",
          "source": "hist-mac128-inside3",
          "locator": "pp. III-17, III-22–III-25"
        },
        "software": {
          "value": "Toolbox and operating-system routines in ROM",
          "source": "hist-mac128-inside3",
          "locator": "p. III-18"
        },
        "workload": {
          "value": "Bitmapped interactive applications using system software",
          "source": "hist-mac128-inside3",
          "locator": "pp. III-17–III-19"
        }
      },
      "diagram": {
        "title": "Scheduled RAM use by CPU, video and sound",
        "scope": "Data-flow abstraction derived from the hardware chapter; interleaving is a memory scheduling relationship, not a second CPU.",
        "nodes": [
          {
            "id": "cpu",
            "label": "MC68000",
            "subtitle": "7.8336MHz",
            "text": "Runs applications, traps and ROM routines.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-mac128-inside3",
            "locator": "p. III-17",
            "control": false
          },
          {
            "id": "ram",
            "label": "128K working RAM",
            "subtitle": "HEAPS / STACK / BUFFERS",
            "text": "Stores program state, video and sound samples.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-mac128-inside3",
            "locator": "pp. III-17–III-21",
            "control": false
          },
          {
            "id": "rom",
            "label": "System ROM",
            "subtitle": "TOOLBOX / OS ROUTINES",
            "text": "Supplies persistent code at full processor rate.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-mac128-inside3",
            "locator": "p. III-18",
            "control": false
          },
          {
            "id": "video",
            "label": "Video scan interface",
            "subtitle": "512 × 342 / 1 BIT",
            "text": "Reads screen buffers in interleaved RAM cycles.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-mac128-inside3",
            "locator": "pp. III-18–III-19",
            "control": false
          },
          {
            "id": "sound",
            "label": "Sound / disk-speed fetch",
            "subtitle": "PER-SCAN-LINE ACCESS",
            "text": "Reads buffer words after each scan line.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-mac128-inside3",
            "locator": "pp. III-18, III-21",
            "control": false
          },
          {
            "id": "via",
            "label": "6522 VIA",
            "subtitle": "TIMERS / KEYBOARD / MOUSE",
            "text": "Controls peripheral signals and vertical-blank IRQ.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-mac128-inside3",
            "locator": "pp. III-17–III-18",
            "control": false
          },
          {
            "id": "scc",
            "label": "Z8530 SCC",
            "subtitle": "TWO RS422 PORTS",
            "text": "Transfers serial data for printer/modem use.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-mac128-inside3",
            "locator": "p. III-22",
            "control": false
          },
          {
            "id": "iwm",
            "label": "IWM disk controller",
            "subtitle": "FLOPPY INTERFACE",
            "text": "Controls disk data operations.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-mac128-inside3",
            "locator": "pp. III-17, III-25",
            "control": false
          },
          {
            "id": "human",
            "label": "Keyboard / mouse / display",
            "subtitle": "INTERACTIVE DEVICES",
            "text": "Connects user actions and visible output.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-mac128-inside3",
            "locator": "pp. III-17–III-19",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu",
            "to": "ram",
            "type": "data",
            "source": "hist-mac128-inside3",
            "locator": "p. III-17",
            "label": ""
          },
          {
            "from": "ram",
            "to": "cpu",
            "type": "data",
            "source": "hist-mac128-inside3",
            "locator": "p. III-17",
            "label": ""
          },
          {
            "from": "rom",
            "to": "cpu",
            "type": "data",
            "source": "hist-mac128-inside3",
            "locator": "p. III-18",
            "label": ""
          },
          {
            "from": "ram",
            "to": "video",
            "type": "data",
            "source": "hist-mac128-inside3",
            "locator": "p. III-18",
            "label": ""
          },
          {
            "from": "video",
            "to": "ram",
            "type": "control",
            "source": "hist-mac128-inside3",
            "locator": "p. III-18 interleaved access",
            "label": ""
          },
          {
            "from": "ram",
            "to": "sound",
            "type": "data",
            "source": "hist-mac128-inside3",
            "locator": "p. III-18",
            "label": ""
          },
          {
            "from": "sound",
            "to": "ram",
            "type": "control",
            "source": "hist-mac128-inside3",
            "locator": "p. III-18 scheduled access",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "via",
            "type": "data",
            "source": "hist-mac128-inside3",
            "locator": "p. III-17 mapped I/O",
            "label": ""
          },
          {
            "from": "via",
            "to": "cpu",
            "type": "control",
            "source": "hist-mac128-inside3",
            "locator": "p. III-18 blanking interrupt",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "scc",
            "type": "data",
            "source": "hist-mac128-inside3",
            "locator": "pp. III-17, III-22",
            "label": ""
          },
          {
            "from": "scc",
            "to": "cpu",
            "type": "data",
            "source": "hist-mac128-inside3",
            "locator": "pp. III-17, III-22",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "iwm",
            "type": "data",
            "source": "hist-mac128-inside3",
            "locator": "p. III-17",
            "label": ""
          },
          {
            "from": "iwm",
            "to": "cpu",
            "type": "data",
            "source": "hist-mac128-inside3",
            "locator": "p. III-17",
            "label": ""
          },
          {
            "from": "human",
            "to": "via",
            "type": "data",
            "source": "hist-mac128-inside3",
            "locator": "p. III-17 keyboard/mouse",
            "label": ""
          },
          {
            "from": "video",
            "to": "human",
            "type": "data",
            "source": "hist-mac128-inside3",
            "locator": "pp. III-18–III-19",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Apple Macintosh 128K"
    },
    {
      "id": "queue-051",
      "name": "Acorn Archimedes A440 — original 400-series board",
      "organization": "Acorn Computers",
      "year": 1988,
      "yearLabel": "November 1988 service-manual configuration",
      "kind": "RISC personal computer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "risc",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-archimedes-a440"
      ],
      "summary": "MEMC translates and arbitrates a shared 32-bit memory system, streaming display and sound bursts to VIDC while IOC bridges slower peripheral cycles.",
      "config": "Original A440 with 4MB DRAM, ARM second-generation processor and Arthur-era ROM; 400/1 MEMC1a and later RISC OS machines excluded.",
      "gaps": [
        "Architectural 64MB addressability is distinct from installed 4MB DRAM.",
        "The cited service manual is specific to the original A440; it does not establish every Archimedes model."
      ],
      "originalName": "Acorn Archimedes",
      "insight": "How do video and sound DMA share a high-bandwidth memory bus with a small RISC CPU?",
      "fields": {
        "state": {
          "value": "32-bit ARM data, 26-bit addresses and mapped device registers",
          "source": "hist-archimedes-a440",
          "locator": "pp. 5, 10–11"
        },
        "compute": {
          "value": "Pipelined 32-bit reduced-instruction-set ARM",
          "source": "hist-archimedes-a440",
          "locator": "p. 10"
        },
        "memory": {
          "value": "4MB DRAM; MEMC logical-to-physical translation and protection",
          "source": "hist-archimedes-a440",
          "locator": "p. 10"
        },
        "control": {
          "value": "MEMC clocks/refresh/DMA and IOC interrupts/timers",
          "source": "hist-archimedes-a440",
          "locator": "pp. 10–11"
        },
        "io": {
          "value": "VIDC display/audio; IOC-controlled 16-bit peripheral bus and podules",
          "source": "hist-archimedes-a440",
          "locator": "pp. 10–12"
        },
        "software": {
          "value": "Arthur ROM environment; compiler-oriented ARM instruction set",
          "source": "hist-archimedes-a440",
          "locator": "pp. 5–6, 10"
        },
        "workload": {
          "value": "Interactive graphics, sound and general personal computing",
          "source": "hist-archimedes-a440",
          "locator": "pp. 5–6, 10–11"
        }
      },
      "diagram": {
        "title": "Four-chip architecture with burst video and sound DMA",
        "scope": "The main system data bus carries RAM payload; MEMC supplies address/timing/DMA control, and IOC controls the latched slow I/O bus.",
        "nodes": [
          {
            "id": "arm",
            "label": "ARM processor",
            "subtitle": "PIPELINED 32-BIT RISC",
            "text": "Executes instructions on the main system data bus.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-archimedes-a440",
            "locator": "p. 10",
            "control": false
          },
          {
            "id": "memc",
            "label": "MEMC",
            "subtitle": "TRANSLATION / TIMING / DMA",
            "text": "Maps addresses and generates memory/DMA cycles.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-archimedes-a440",
            "locator": "p. 10",
            "control": true
          },
          {
            "id": "dram",
            "label": "4MB DRAM",
            "subtitle": "SHARED MAIN STORAGE",
            "text": "Serves CPU and four-word VIDC bursts.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-archimedes-a440",
            "locator": "p. 10",
            "control": false
          },
          {
            "id": "rom",
            "label": "Arthur ROM",
            "subtitle": "SYSTEM SOFTWARE",
            "text": "Supplies boot and operating-environment instructions.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-archimedes-a440",
            "locator": "pp. 5–6; p. 10 diagram",
            "control": false
          },
          {
            "id": "vidc",
            "label": "VIDC",
            "subtitle": "VIDEO / CURSOR / SOUND FIFOs",
            "text": "Consumes DMA words and generates video/audio.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-archimedes-a440",
            "locator": "pp. 10–11",
            "control": false
          },
          {
            "id": "av",
            "label": "Display / stereo sound",
            "subtitle": "PALETTE / DAC OUTPUTS",
            "text": "Presents pixels, cursor and eight sound channels.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-archimedes-a440",
            "locator": "pp. 10–11",
            "control": false
          },
          {
            "id": "ioc",
            "label": "IOC and data latches",
            "subtitle": "INTERRUPTS / SLOW CYCLES",
            "text": "Bridges main data bus to timed I/O accesses.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-archimedes-a440",
            "locator": "pp. 11–12",
            "control": false
          },
          {
            "id": "periph",
            "label": "Disk / serial / keyboard / mouse",
            "subtitle": "16-BIT I/O BUS",
            "text": "Provide storage and interactive input.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-archimedes-a440",
            "locator": "pp. 10–12",
            "control": false
          },
          {
            "id": "podule",
            "label": "Expansion podules",
            "subtitle": "IOC OR MEMC HANDSHAKE",
            "text": "Extend the mapped peripheral system.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-archimedes-a440",
            "locator": "pp. 11–12",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "arm",
            "to": "dram",
            "type": "data",
            "source": "hist-archimedes-a440",
            "locator": "p. 10 main data bus",
            "label": ""
          },
          {
            "from": "dram",
            "to": "arm",
            "type": "data",
            "source": "hist-archimedes-a440",
            "locator": "p. 10",
            "label": ""
          },
          {
            "from": "arm",
            "to": "memc",
            "type": "control",
            "source": "hist-archimedes-a440",
            "locator": "p. 10 address bus",
            "label": ""
          },
          {
            "from": "memc",
            "to": "dram",
            "type": "control",
            "source": "hist-archimedes-a440",
            "locator": "p. 10 refresh/address timing",
            "label": ""
          },
          {
            "from": "rom",
            "to": "arm",
            "type": "data",
            "source": "hist-archimedes-a440",
            "locator": "p. 10 main data bus",
            "label": ""
          },
          {
            "from": "vidc",
            "to": "memc",
            "type": "control",
            "source": "hist-archimedes-a440",
            "locator": "p. 10 DMA request",
            "label": ""
          },
          {
            "from": "memc",
            "to": "vidc",
            "type": "control",
            "source": "hist-archimedes-a440",
            "locator": "p. 10 DMA address generators",
            "label": ""
          },
          {
            "from": "dram",
            "to": "vidc",
            "type": "data",
            "source": "hist-archimedes-a440",
            "locator": "p. 10 four-word bursts",
            "label": ""
          },
          {
            "from": "vidc",
            "to": "av",
            "type": "data",
            "source": "hist-archimedes-a440",
            "locator": "pp. 10–11",
            "label": ""
          },
          {
            "from": "arm",
            "to": "ioc",
            "type": "data",
            "source": "hist-archimedes-a440",
            "locator": "p. 10 data latch",
            "label": ""
          },
          {
            "from": "ioc",
            "to": "arm",
            "type": "data",
            "source": "hist-archimedes-a440",
            "locator": "p. 10 data latch",
            "label": ""
          },
          {
            "from": "ioc",
            "to": "periph",
            "type": "data",
            "source": "hist-archimedes-a440",
            "locator": "pp. 10–12 I/O bus",
            "label": ""
          },
          {
            "from": "periph",
            "to": "ioc",
            "type": "data",
            "source": "hist-archimedes-a440",
            "locator": "pp. 10–12",
            "label": ""
          },
          {
            "from": "ioc",
            "to": "podule",
            "type": "control",
            "source": "hist-archimedes-a440",
            "locator": "pp. 11–12",
            "label": ""
          },
          {
            "from": "podule",
            "to": "memc",
            "type": "control",
            "source": "hist-archimedes-a440",
            "locator": "p. 11 non-IOC handshake",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Acorn Archimedes"
    },
    {
      "id": "queue-052",
      "name": "Sun-1 workstation — July 1982 reference",
      "organization": "Sun Microsystems",
      "year": 1982,
      "yearLabel": "27 July 1982 reference draft",
      "kind": "Network graphics workstation",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "register-memory",
        "cisc",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-sun1-1982"
      ],
      "summary": "A 68000 processor uses context, segment and page maps for protected references; a separate bitmapped graphics board implements programmable Boolean raster functions.",
      "config": "10MHz 68000 board with 256KB parity RAM and graphics board; 3Mbit Ethernet and disk controllers remain optional. Original Sun-1, not 68010 Sun-2.",
      "gaps": [
        "The manual describes future 68010 compatibility; this record retains the installed 68000.",
        "The stated MMU mechanisms are not a claim that 68000 transparently restarts all demand-page faults.",
        "The 1024×1024 frame buffer displays only 1024×800 pixels."
      ],
      "originalName": "Sun-1",
      "insight": "How is a graphics memory Boolean operation different from drawing each pixel in CPU software?",
      "fields": {
        "state": {
          "value": "68000 registers plus one-bit graphics pixels",
          "source": "hist-sun1-1982",
          "locator": "pp. 4, 51"
        },
        "compute": {
          "value": "10MHz 68000 and graphics RasterOp function unit",
          "source": "hist-sun1-1982",
          "locator": "pp. 4, 51–53"
        },
        "memory": {
          "value": "256KB parity RAM; 2KB pages and 16 concurrently mapped contexts",
          "source": "hist-sun1-1982",
          "locator": "pp. 4, 37–38"
        },
        "control": {
          "value": "Context → segment → page translation with access protection",
          "source": "hist-sun1-1982",
          "locator": "pp. 37–39"
        },
        "io": {
          "value": "Multibus, serial/timer ports; optional 3Mbit Ethernet",
          "source": "hist-sun1-1982",
          "locator": "pp. 3–5, 11"
        },
        "software": {
          "value": "C programming interfaces; MMU designed for multitasking UNIX-like OS",
          "source": "hist-sun1-1982",
          "locator": "pp. 2, 37"
        },
        "workload": {
          "value": "Interactive bitmapped graphics and network workstation use",
          "source": "hist-sun1-1982",
          "locator": "pp. 1, 51–55"
        }
      },
      "diagram": {
        "title": "Protected CPU references and a separate RasterOp graphics engine",
        "scope": "MMU roles follow pp. 37–39; graphics read/modify/write follows pp. 51–55.",
        "nodes": [
          {
            "id": "cpu",
            "label": "68000 processor",
            "subtitle": "10MHz",
            "text": "Issues instruction, memory and device references.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-sun1-1982",
            "locator": "p. 4",
            "control": false
          },
          {
            "id": "maps",
            "label": "Context / segment / page maps",
            "subtitle": "2KB PAGES / 16 CONTEXTS",
            "text": "Translate and protect all processor references.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-sun1-1982",
            "locator": "pp. 37–39",
            "control": true
          },
          {
            "id": "ram",
            "label": "On-board parity RAM",
            "subtitle": "256KB",
            "text": "Serves processor storage over a fast memory path.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-sun1-1982",
            "locator": "pp. 3–4",
            "control": false
          },
          {
            "id": "bus",
            "label": "Multibus",
            "subtitle": "ASYNCHRONOUS I/O",
            "text": "Connects graphics and optional peripheral boards.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-sun1-1982",
            "locator": "pp. 1, 3",
            "control": false
          },
          {
            "id": "raster",
            "label": "Raster-function unit",
            "subtitle": "256 BOOLEAN FUNCTIONS",
            "text": "Combines source, destination and pattern bits.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-sun1-1982",
            "locator": "pp. 51–54",
            "control": false
          },
          {
            "id": "frame",
            "label": "Graphics frame buffer",
            "subtitle": "1024 × 1024 × 1 BIT",
            "text": "Retains visible and off-screen bitmap state.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-sun1-1982",
            "locator": "p. 51",
            "control": false
          },
          {
            "id": "display",
            "label": "Video display",
            "subtitle": "1024 × 800 VISIBLE",
            "text": "Scans the visible part of frame memory.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-sun1-1982",
            "locator": "p. 51",
            "control": false
          },
          {
            "id": "serial",
            "label": "UART / timers / parallel input",
            "subtitle": "ON-BOARD INTERFACES",
            "text": "Provide serial communication, timing and mouse input.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-sun1-1982",
            "locator": "pp. 1, 4–5",
            "control": false
          },
          {
            "id": "network",
            "label": "Ethernet board",
            "subtitle": "OPTIONAL 3Mbit/s",
            "text": "Connects the workstation to an Ethernet-1 LAN.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-sun1-1982",
            "locator": "pp. 1, 11",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu",
            "to": "maps",
            "type": "control",
            "source": "hist-sun1-1982",
            "locator": "p. 37 all references",
            "label": ""
          },
          {
            "from": "maps",
            "to": "ram",
            "type": "control",
            "source": "hist-sun1-1982",
            "locator": "pp. 37–38",
            "label": ""
          },
          {
            "from": "maps",
            "to": "bus",
            "type": "control",
            "source": "hist-sun1-1982",
            "locator": "pp. 37–38",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "ram",
            "type": "data",
            "source": "hist-sun1-1982",
            "locator": "pp. 3–4 memory bus",
            "label": ""
          },
          {
            "from": "ram",
            "to": "cpu",
            "type": "data",
            "source": "hist-sun1-1982",
            "locator": "pp. 3–4",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "bus",
            "type": "data",
            "source": "hist-sun1-1982",
            "locator": "p. 3",
            "label": ""
          },
          {
            "from": "bus",
            "to": "cpu",
            "type": "data",
            "source": "hist-sun1-1982",
            "locator": "p. 3",
            "label": ""
          },
          {
            "from": "bus",
            "to": "raster",
            "type": "data",
            "source": "hist-sun1-1982",
            "locator": "pp. 51–54",
            "label": ""
          },
          {
            "from": "frame",
            "to": "raster",
            "type": "data",
            "source": "hist-sun1-1982",
            "locator": "pp. 51–54 destination/source reads",
            "label": ""
          },
          {
            "from": "raster",
            "to": "frame",
            "type": "data",
            "source": "hist-sun1-1982",
            "locator": "pp. 51–54 result",
            "label": ""
          },
          {
            "from": "frame",
            "to": "display",
            "type": "data",
            "source": "hist-sun1-1982",
            "locator": "p. 51",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "serial",
            "type": "data",
            "source": "hist-sun1-1982",
            "locator": "pp. 4–5",
            "label": ""
          },
          {
            "from": "serial",
            "to": "cpu",
            "type": "control",
            "source": "hist-sun1-1982",
            "locator": "p. 5 timer interrupts",
            "label": ""
          },
          {
            "from": "bus",
            "to": "network",
            "type": "data",
            "source": "hist-sun1-1982",
            "locator": "p. 11",
            "label": ""
          },
          {
            "from": "network",
            "to": "bus",
            "type": "data",
            "source": "hist-sun1-1982",
            "locator": "p. 11",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Sun-1"
    },
    {
      "id": "queue-053",
      "name": "Sun SPARCstation 1 — 20MHz S4 system",
      "organization": "Sun Microsystems",
      "year": 1990,
      "yearLabel": "1990–91 service reference for original 20MHz model",
      "kind": "Cached SPARC workstation",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "risc",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-sparcstation1-field"
      ],
      "summary": "The S4 chipset separates the CPU’s cached address/data paths from SBus, with a shared DMA bridge for Ethernet and SCSI and a separate narrow peripheral bus.",
      "config": "Original 20MHz SPARCstation 1; not the 25MHz SPARCstation 1+. Installed SIMM total unspecified; SBus framebuffer shown as an attached board.",
      "gaps": [
        "The combined service manual has inconsistent DRAM wording; no installed total is inferred.",
        "Clock speed and early/late audio distinctions prevent accidentally assigning 1+ revisions to the original."
      ],
      "originalName": "Sun SPARCstation 1",
      "insight": "Which transfers use S4 DMA and which are handled by the CPU cache controller?",
      "fields": {
        "state": {
          "value": "SPARC instruction unit and floating-point coprocessor",
          "source": "hist-sparcstation1-field",
          "locator": "p. 7"
        },
        "compute": {
          "value": "Original SPARCstation 1 IU: 20MHz",
          "source": "hist-sparcstation1-field",
          "locator": "p. 7"
        },
        "memory": {
          "value": "64KB write-through cache, 16-byte lines; SIMM main memory",
          "source": "hist-sparcstation1-field",
          "locator": "pp. 8, 11–13"
        },
        "control": {
          "value": "S4 MMU maps and protects process and device addresses",
          "source": "hist-sparcstation1-field",
          "locator": "p. 11"
        },
        "io": {
          "value": "SBus; shared S4 DMA for Ethernet/SCSI; eight-bit I/O bus",
          "source": "hist-sparcstation1-field",
          "locator": "pp. 6, 8–12"
        },
        "software": {
          "value": "Boot PROM Forth toolkit and SunOS boot path",
          "source": "hist-sparcstation1-field",
          "locator": "pp. 8–9"
        },
        "workload": {
          "value": "Interactive graphics, network and general workstation use",
          "source": "hist-sparcstation1-field",
          "locator": "pp. 7–13"
        }
      },
      "diagram": {
        "title": "S4 cached CPU path and Ethernet/SCSI DMA bridge",
        "scope": "Original Figure 1-4 gives the physical bus relationships; descriptions pp. 7–12 explain their distinct roles.",
        "nodes": [
          {
            "id": "cpu",
            "label": "SPARC IU and FPU",
            "subtitle": "ORIGINAL 20MHz CPU CORE",
            "text": "Execute integer and floating-point operations.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-sparcstation1-field",
            "locator": "p. 7",
            "control": false
          },
          {
            "id": "cache",
            "label": "S4 cache / buffer / RAMs",
            "subtitle": "64KB WRITE THROUGH",
            "text": "Compare tags and control CPU address/data paths.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-sparcstation1-field",
            "locator": "p. 8",
            "control": false
          },
          {
            "id": "mmu",
            "label": "S4 MMU",
            "subtitle": "VIRTUAL → PHYSICAL",
            "text": "Maps addresses and enforces page protections.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-sparcstation1-field",
            "locator": "p. 11",
            "control": false
          },
          {
            "id": "bus",
            "label": "SBus",
            "subtitle": "32-BIT SYNCHRONOUS",
            "text": "Links memory-side transfers and three board slots.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-sparcstation1-field",
            "locator": "pp. 6, 12",
            "control": false
          },
          {
            "id": "memory",
            "label": "S4 RAM / SIMMs",
            "subtitle": "MAIN DRAM",
            "text": "Serve memory requests from the shared system path.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-sparcstation1-field",
            "locator": "pp. 6, 11–13",
            "control": false
          },
          {
            "id": "dma",
            "label": "S4 DMA",
            "subtitle": "ETHERNET / SCSI BRIDGE",
            "text": "Connects both high-rate controllers to SBus.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-sparcstation1-field",
            "locator": "p. 11",
            "control": false
          },
          {
            "id": "devices",
            "label": "LANCE / SCSI controllers",
            "subtitle": "NETWORK / DISK",
            "text": "Drive external network and storage transfers.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-sparcstation1-field",
            "locator": "pp. 11–12",
            "control": false
          },
          {
            "id": "narrow",
            "label": "Eight-bit I/O bus",
            "subtitle": "PROM / SCC / TOD / AUDIO",
            "text": "Connects boot, serial and low-rate devices.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-sparcstation1-field",
            "locator": "pp. 6, 8–10",
            "control": false
          },
          {
            "id": "video",
            "label": "SBus framebuffer board",
            "subtitle": "S4 VIDEO / VRAM",
            "text": "Holds and scans display pixels.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-sparcstation1-field",
            "locator": "p. 6 Fig. 1-4",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu",
            "to": "cache",
            "type": "data",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4",
            "label": ""
          },
          {
            "from": "cache",
            "to": "cpu",
            "type": "data",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4",
            "label": ""
          },
          {
            "from": "cache",
            "to": "mmu",
            "type": "control",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4 address path",
            "label": ""
          },
          {
            "from": "mmu",
            "to": "bus",
            "type": "control",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4",
            "label": ""
          },
          {
            "from": "cache",
            "to": "bus",
            "type": "data",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4 S4 buffer",
            "label": ""
          },
          {
            "from": "bus",
            "to": "cache",
            "type": "data",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4",
            "label": ""
          },
          {
            "from": "bus",
            "to": "memory",
            "type": "data",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4",
            "label": ""
          },
          {
            "from": "memory",
            "to": "bus",
            "type": "data",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4",
            "label": ""
          },
          {
            "from": "devices",
            "to": "dma",
            "type": "data",
            "source": "hist-sparcstation1-field",
            "locator": "p. 11",
            "label": ""
          },
          {
            "from": "dma",
            "to": "devices",
            "type": "data",
            "source": "hist-sparcstation1-field",
            "locator": "p. 11",
            "label": ""
          },
          {
            "from": "dma",
            "to": "bus",
            "type": "data",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4",
            "label": ""
          },
          {
            "from": "bus",
            "to": "dma",
            "type": "data",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4",
            "label": ""
          },
          {
            "from": "bus",
            "to": "narrow",
            "type": "association",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4 I/O data bus",
            "label": ""
          },
          {
            "from": "bus",
            "to": "video",
            "type": "data",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4",
            "label": ""
          },
          {
            "from": "video",
            "to": "bus",
            "type": "data",
            "source": "hist-sparcstation1-field",
            "locator": "Fig. 1-4",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Sun SPARCstation 1"
    },
    {
      "id": "queue-054",
      "name": "SGI IRIS 4D/GT — 1988 graphics-system configuration",
      "organization": "Silicon Graphics",
      "year": 1988,
      "yearLabel": "1988 designer architecture paper",
      "kind": "Parallel graphics workstation subsystem",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "risc",
        "heterogeneous",
        "pipelined",
        "simd"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-sgi-gt-akeley",
        "hist-sgi-gt-identity"
      ],
      "summary": "A RISC host feeds a geometry pipeline, scan conversion processors and an interleaved array of pixel engines; independent display processors interpret window-tagged framebuffer pixels.",
      "config": "Five-board graphics implementation documented by Akeley/Jermoluk; generic multi-RISC host interface. Exact host SKU, CPU count and installed host RAM remain unassigned.",
      "gaps": [
        "This covers the GT graphics configuration, not every IRIS 4D host or Personal IRIS.",
        "SIMD refers to parallel vector-component operations in the scan-conversion engines, not a claim that all processors share one instruction stream.",
        "Published benchmark conditions are not generalized to arbitrary scene workloads."
      ],
      "originalName": "SGI IRIS 4D",
      "insight": "Why are floating geometry, scan conversion and framebuffer pixel operations separate processor organizations?",
      "fields": {
        "state": {
          "value": "32-bit floating geometry and 96-bit framebuffer pixels",
          "source": "hist-sgi-gt-akeley",
          "locator": "pp. 241, 243–244"
        },
        "compute": {
          "value": "Five pipelined geometry engines; five span and 20 image engines",
          "source": "hist-sgi-gt-akeley",
          "locator": "pp. 241–244"
        },
        "memory": {
          "value": "512-word input FIFO; two 256-vertex buffers; 1280×1024 framebuffer",
          "source": "hist-sgi-gt-akeley",
          "locator": "pp. 241, 243"
        },
        "control": {
          "value": "Hardware pipeline flow control and window/context state",
          "source": "hist-sgi-gt-akeley",
          "locator": "pp. 241, 243–244"
        },
        "io": {
          "value": "64-bit synchronous host bus and parallel display/DAC output",
          "source": "hist-sgi-gt-akeley",
          "locator": "pp. 241–244"
        },
        "software": {
          "value": "Immediate-mode graphics commands in application-language subroutines",
          "source": "hist-sgi-gt-akeley",
          "locator": "p. 241 §3.1"
        },
        "workload": {
          "value": "Interactive lighted, shaded and depth-buffered polygon rendering",
          "source": "hist-sgi-gt-akeley",
          "locator": "pp. 239, 244"
        }
      },
      "diagram": {
        "title": "Geometry pipeline, interleaved raster engines and per-window display",
        "scope": "The graph follows the paper’s four hardware subsystems; it combines related stages while retaining the actual fan-out to five span and 20 image engines.",
        "nodes": [
          {
            "id": "host",
            "label": "RISC host / 64-bit bus",
            "subtitle": "APPLICATION-DRIVEN TRANSFERS",
            "text": "Submits immediate-mode vectors from main memory.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 241 §3.1",
            "control": false
          },
          {
            "id": "fifo",
            "label": "FIFO / format converter",
            "subtitle": "512 WORDS / IEEE FLOAT",
            "text": "Buffers input and normalizes coordinate formats.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 241 §3.2.1",
            "control": false
          },
          {
            "id": "geometry",
            "label": "Five geometry engines",
            "subtitle": "TRANSFORM / LIGHT / CLIP",
            "text": "Pipeline coordinate and lighting operations.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-sgi-gt-akeley",
            "locator": "pp. 241, 243 §3.2",
            "control": false
          },
          {
            "id": "polygon",
            "label": "Vertex buffers / polygon CPU",
            "subtitle": "TWO × 256 VERTICES",
            "text": "Sorts vertices and decomposes polygons into trapezoids.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 243 §3.3",
            "control": false
          },
          {
            "id": "edge",
            "label": "Edge processor",
            "subtitle": "PARALLEL COMPONENT ITERATION",
            "text": "Produces corrected vertical-span specifications.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 243 §3.3",
            "control": false
          },
          {
            "id": "span",
            "label": "Five span processors",
            "subtitle": "EVERY FIFTH COLUMN",
            "text": "Interpolate color/depth into individual pixels.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 243 §3.3",
            "control": false
          },
          {
            "id": "image",
            "label": "20 image engines / VRAM",
            "subtitle": "5 × 4 INTERLEAVING",
            "text": "Apply replace, depth and blend algorithms to pixels.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-sgi-gt-akeley",
            "locator": "pp. 243–244 §3.4",
            "control": false
          },
          {
            "id": "display",
            "label": "Five display processors",
            "subtitle": "WINDOW-ID INTERPRETATION",
            "text": "Choose image/overlay interpretation per pixel.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 244 §3.5",
            "control": false
          },
          {
            "id": "monitor",
            "label": "DAC / monitor output",
            "subtitle": "RGB AND ALPHA",
            "text": "Presents continuously scanned framebuffer values.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-sgi-gt-akeley",
            "locator": "pp. 242, 244",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "fifo",
            "type": "data",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 241 §3.1",
            "label": ""
          },
          {
            "from": "fifo",
            "to": "host",
            "type": "control",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 241 high/low-water interrupts",
            "label": ""
          },
          {
            "from": "fifo",
            "to": "geometry",
            "type": "data",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 241 §3.2",
            "label": ""
          },
          {
            "from": "geometry",
            "to": "polygon",
            "type": "data",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 243 vertex buffers",
            "label": ""
          },
          {
            "from": "polygon",
            "to": "edge",
            "type": "data",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 243 slopes and edge coordinates",
            "label": ""
          },
          {
            "from": "edge",
            "to": "span",
            "type": "data",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 243 span definitions",
            "label": ""
          },
          {
            "from": "span",
            "to": "image",
            "type": "data",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 243 four image engines per span CPU",
            "label": ""
          },
          {
            "from": "image",
            "to": "display",
            "type": "data",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 244 §3.5",
            "label": ""
          },
          {
            "from": "display",
            "to": "monitor",
            "type": "data",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 244 §3.5",
            "label": ""
          },
          {
            "from": "host",
            "to": "geometry",
            "type": "control",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 244 §3.6 context restore",
            "label": ""
          },
          {
            "from": "geometry",
            "to": "host",
            "type": "data",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 244 §3.6 context dump",
            "label": ""
          },
          {
            "from": "polygon",
            "to": "host",
            "type": "association",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 244 shadow-state maintenance",
            "label": ""
          },
          {
            "from": "host",
            "to": "image",
            "type": "association",
            "source": "hist-sgi-gt-akeley",
            "locator": "p. 245 pixel read/write support",
            "label": ""
          }
        ]
      },
      "originalCandidate": "SGI IRIS 4D"
    },
    {
      "id": "queue-055",
      "name": "Symbolics 3600 — February 1983 system",
      "organization": "Symbolics",
      "year": 1983,
      "yearLabel": "February 1983 technical summary",
      "kind": "Tagged Lisp workstation",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "stack",
        "microcoded",
        "pipelined",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "lambda"
      ],
      "aliases": [],
      "sources": [
        "hist-symbolics3600-1983"
      ],
      "summary": "Typed stack operations use dedicated buffers and parallel type checks, while an instruction-fetch unit dispatches microcode and a separate 68000 front end handles slower I/O.",
      "config": "Original February 1983 3600, 36-bit tagged architecture; later 3640/3670 and Ivory formats excluded.",
      "gaps": [
        "The lambda/functional tag identifies supported function application and lexical closures; Zetalisp also includes mutation, processes and object-oriented features.",
        "The stack-oriented ISA is not claimed to be a pure stack machine.",
        "The minimum 256K-word RAM is a configuration option; installed capacity is not assigned."
      ],
      "originalName": "Symbolics 3600",
      "insight": "How do Lisp function calls and typed objects shape the processor’s stack, cache and exception mechanisms?",
      "fields": {
        "state": {
          "value": "36-bit tagged words: 32 data bits and four tag bits",
          "source": "hist-symbolics3600-1983",
          "locator": "p. 7"
        },
        "compute": {
          "value": "Stack-oriented execution with hardware type checking beside arithmetic",
          "source": "hist-symbolics3600-1983",
          "locator": "pp. 83, 88"
        },
        "memory": {
          "value": "1K-word instruction cache; two 1K-word stack buffers; demand-paged memory",
          "source": "hist-symbolics3600-1983",
          "locator": "pp. 93–96"
        },
        "control": {
          "value": "IFU dispatch to 8K-word × 112-bit microcode; hardware microtasks",
          "source": "hist-symbolics3600-1983",
          "locator": "pp. 89–90"
        },
        "io": {
          "value": "L-bus DMA; 68000 FEP and separate 68000 console",
          "source": "hist-symbolics3600-1983",
          "locator": "pp. 100, 105, 108"
        },
        "software": {
          "value": "Zetalisp function calls and lexical closures; interactive compiler/environment",
          "source": "hist-symbolics3600-1983",
          "locator": "pp. 6, 83"
        },
        "workload": {
          "value": "Interactive Lisp, symbolic mathematics and development",
          "source": "hist-symbolics3600-1983",
          "locator": "p. 6"
        }
      },
      "diagram": {
        "title": "Instruction dispatch and typed stack execution on the L bus",
        "scope": "Reconstructed from inspected Fig. 23 plus stack-buffer and front-end descriptions; no later Ivory features are merged.",
        "nodes": [
          {
            "id": "fetch",
            "label": "Instruction-fetch unit",
            "subtitle": "PREFETCH / BRANCH / DECODE",
            "text": "Fills instruction cache and produces microcode addresses.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-symbolics3600-1983",
            "locator": "pp. 89–90",
            "control": false
          },
          {
            "id": "icache",
            "label": "Instruction cache",
            "subtitle": "1K WORDS / 2K INSTRUCTIONS",
            "text": "Holds decoded-path instruction words for dispatch.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-symbolics3600-1983",
            "locator": "pp. 89, 93",
            "control": false
          },
          {
            "id": "micro",
            "label": "Control store / microtasks",
            "subtitle": "8K × 112-BIT WORDS",
            "text": "Sequences Lisp and peripheral microtasks.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-symbolics3600-1983",
            "locator": "p. 89",
            "control": true
          },
          {
            "id": "execute",
            "label": "Execution engine / tags",
            "subtitle": "TYPE CHECK WITH ARITHMETIC",
            "text": "Computes results or traps for another operand type.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-symbolics3600-1983",
            "locator": "p. 88",
            "control": false
          },
          {
            "id": "stack",
            "label": "Two stack buffers",
            "subtitle": "TWO × 1K WORDS",
            "text": "Cache top stack pages with automatic pointers.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-symbolics3600-1983",
            "locator": "pp. 93–94",
            "control": false
          },
          {
            "id": "maps",
            "label": "Virtual-memory map",
            "subtitle": "HARDWARE / MICROCODE / LISP",
            "text": "Translates Lisp pointers and handles missing pages.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-symbolics3600-1983",
            "locator": "pp. 94–96",
            "control": false
          },
          {
            "id": "memory",
            "label": "L bus / ECC memory",
            "subtitle": "44-BIT PHYSICAL WORDS",
            "text": "Connects memory, processor and high-speed devices.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-symbolics3600-1983",
            "locator": "pp. 94, 100",
            "control": false
          },
          {
            "id": "fep",
            "label": "68000 front-end processor",
            "subtitle": "LOW-RATE I/O / DIAGNOSTICS",
            "text": "Routes serial and MULTIBUS I/O to L bus.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-symbolics3600-1983",
            "locator": "p. 105",
            "control": false
          },
          {
            "id": "console",
            "label": "Separate 68000 console",
            "subtitle": "1150 × 900 / KEYBOARD / MOUSE",
            "text": "Controls the user display and input interface.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-symbolics3600-1983",
            "locator": "pp. 105, 108",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "memory",
            "to": "fetch",
            "type": "data",
            "source": "hist-symbolics3600-1983",
            "locator": "Fig. 23 ECC→PF",
            "label": ""
          },
          {
            "from": "fetch",
            "to": "icache",
            "type": "data",
            "source": "hist-symbolics3600-1983",
            "locator": "pp. 89, 93",
            "label": ""
          },
          {
            "from": "icache",
            "to": "micro",
            "type": "control",
            "source": "hist-symbolics3600-1983",
            "locator": "Fig. 23 dispatch address",
            "label": ""
          },
          {
            "from": "micro",
            "to": "execute",
            "type": "control",
            "source": "hist-symbolics3600-1983",
            "locator": "Fig. 23 112-bit microcode",
            "label": ""
          },
          {
            "from": "stack",
            "to": "execute",
            "type": "data",
            "source": "hist-symbolics3600-1983",
            "locator": "p. 88 ADD operands",
            "label": ""
          },
          {
            "from": "execute",
            "to": "stack",
            "type": "data",
            "source": "hist-symbolics3600-1983",
            "locator": "p. 88 push result",
            "label": ""
          },
          {
            "from": "execute",
            "to": "micro",
            "type": "control",
            "source": "hist-symbolics3600-1983",
            "locator": "p. 88 type/overflow traps",
            "label": ""
          },
          {
            "from": "execute",
            "to": "maps",
            "type": "control",
            "source": "hist-symbolics3600-1983",
            "locator": "Fig. 23 datapath output",
            "label": ""
          },
          {
            "from": "maps",
            "to": "memory",
            "type": "control",
            "source": "hist-symbolics3600-1983",
            "locator": "Fig. 23",
            "label": ""
          },
          {
            "from": "memory",
            "to": "stack",
            "type": "data",
            "source": "hist-symbolics3600-1983",
            "locator": "pp. 93–94 page fills",
            "label": ""
          },
          {
            "from": "stack",
            "to": "memory",
            "type": "data",
            "source": "hist-symbolics3600-1983",
            "locator": "p. 93 page replacement",
            "label": ""
          },
          {
            "from": "fep",
            "to": "memory",
            "type": "data",
            "source": "hist-symbolics3600-1983",
            "locator": "p. 105 DMA",
            "label": ""
          },
          {
            "from": "memory",
            "to": "fep",
            "type": "data",
            "source": "hist-symbolics3600-1983",
            "locator": "p. 105",
            "label": ""
          },
          {
            "from": "console",
            "to": "fep",
            "type": "data",
            "source": "hist-symbolics3600-1983",
            "locator": "p. 105 dedicated console serial line",
            "label": ""
          },
          {
            "from": "fep",
            "to": "console",
            "type": "data",
            "source": "hist-symbolics3600-1983",
            "locator": "p. 105",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Symbolics 3600"
    },
    {
      "id": "queue-056",
      "name": "LMI Lambda — 1984 Lisp / optional UNIX configuration",
      "organization": "Lisp Machine, Inc.",
      "year": 1984,
      "yearLabel": "1984 field-service configuration",
      "kind": "Modular Lisp workstation",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "microcoded",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "hist-lmi-lambda-service",
        "hist-lmi-lambda-overview"
      ],
      "summary": "A four-board Lisp processor shares NuBus resources with an optional independent UNIX processor; an 8088 diagnostic unit bridges standard Multibus peripherals.",
      "config": "32-bit Lisp configuration with half-megabyte ECC memory modules; optional 68000 UNIX board and standard disk/tape/network interfaces. Proposed 40-bit mode excluded.",
      "gaps": [
        "The 1982 overview describes a future 40-bit option; this record does not assert that it shipped.",
        "The optional UNIX processor’s presence is a configuration choice, not a property of every Lambda.",
        "Detailed internal RG/MI/CM/DP transfers require a processor logic manual; those connections are not invented."
      ],
      "originalName": "LMI Lambda",
      "insight": "Why is a diagnostic microcomputer also the bridge between two system buses?",
      "fields": {
        "state": {
          "value": "32-bit Lisp word: 24-bit pointer, five type bits, three storage bits",
          "source": "hist-lmi-lambda-overview",
          "locator": "p. 2 32-bit configuration"
        },
        "compute": {
          "value": "Independent Lisp processor; optional 68000 with 4K-word cache",
          "source": "hist-lmi-lambda-service",
          "locator": "pp. 3-3–3-4"
        },
        "memory": {
          "value": "Half-megabyte ECC boards; one-bit correction/two-bit detection",
          "source": "hist-lmi-lambda-service",
          "locator": "p. 3-3"
        },
        "control": {
          "value": "8088 SDU diagnoses, clocks NuBus and boots Lisp/UNIX",
          "source": "hist-lmi-lambda-service",
          "locator": "p. 3-2"
        },
        "io": {
          "value": "NuBus to Multibus bridge; SMD disk, tape and Ethernet cards",
          "source": "hist-lmi-lambda-service",
          "locator": "pp. 3-2–3-4"
        },
        "software": {
          "value": "Boot selects Lisp microcode and software band; optional UNIX",
          "source": "hist-lmi-lambda-service",
          "locator": "pp. 6-23–6-24; p. 3-4"
        },
        "workload": {
          "value": "Dedicated Lisp environment and optional independent UNIX services",
          "source": "hist-lmi-lambda-service",
          "locator": "pp. 3-3–3-4"
        }
      },
      "diagram": {
        "title": "Lisp and optional UNIX around NuBus, with an 8088 bridge",
        "scope": "Bus participation follows the manufacturer overview; module roles and installed-era options follow the 1984 service manual.",
        "nodes": [
          {
            "id": "lisp",
            "label": "Four-board Lisp processor",
            "subtitle": "RG / MI / CM / DP",
            "text": "Executes the Lisp microcode and loaded software band.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-lmi-lambda-service",
            "locator": "pp. 3-3, 6-23",
            "control": false
          },
          {
            "id": "nubus",
            "label": "NuBus backplane",
            "subtitle": "32-BIT MODULAR SYSTEM",
            "text": "Links processors, memory and system interfaces.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-lmi-lambda-overview",
            "locator": "p. 1",
            "control": false
          },
          {
            "id": "memory",
            "label": "ECC memory boards",
            "subtitle": "HALF-MEGABYTE MODULES",
            "text": "Supply corrected shared system storage.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-3",
            "control": false
          },
          {
            "id": "unix",
            "label": "68000 UNIX processor",
            "subtitle": "OPTIONAL / 4K-WORD CACHE",
            "text": "Runs an independent UNIX execution environment.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-4",
            "control": false
          },
          {
            "id": "sdu",
            "label": "8088 system diagnostic unit",
            "subtitle": "CLOCK / BOOT / BUS CONVERSION",
            "text": "Connects NuBus and Multibus and runs diagnostics.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-2",
            "control": true
          },
          {
            "id": "multi",
            "label": "Multibus",
            "subtitle": "16 DATA / 20 ADDRESS",
            "text": "Hosts standard peripheral control boards.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-2",
            "control": false
          },
          {
            "id": "disk",
            "label": "SMD controller / Eagle disk",
            "subtitle": "INTERPHASE 2181",
            "text": "Acts as bus master during disk transfers.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-3",
            "control": false
          },
          {
            "id": "net",
            "label": "Tape / Ethernet cards",
            "subtitle": "CPC / 3COM CONTROLLERS",
            "text": "Provide streaming tape and network interfaces.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-lmi-lambda-service",
            "locator": "pp. 3-3–3-4",
            "control": false
          },
          {
            "id": "console",
            "label": "Display / keyboard / mouse",
            "subtitle": "USER CONSOLE",
            "text": "Provides the high-resolution Lisp user interface.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "lisp",
            "to": "nubus",
            "type": "data",
            "source": "hist-lmi-lambda-overview",
            "locator": "p. 1 modular processor bus",
            "label": ""
          },
          {
            "from": "nubus",
            "to": "lisp",
            "type": "data",
            "source": "hist-lmi-lambda-overview",
            "locator": "p. 1",
            "label": ""
          },
          {
            "from": "nubus",
            "to": "memory",
            "type": "data",
            "source": "hist-lmi-lambda-overview",
            "locator": "p. 1 memory modules",
            "label": ""
          },
          {
            "from": "memory",
            "to": "nubus",
            "type": "data",
            "source": "hist-lmi-lambda-overview",
            "locator": "p. 1",
            "label": ""
          },
          {
            "from": "unix",
            "to": "nubus",
            "type": "data",
            "source": "hist-lmi-lambda-overview",
            "locator": "p. 1 optional processor",
            "label": ""
          },
          {
            "from": "nubus",
            "to": "unix",
            "type": "data",
            "source": "hist-lmi-lambda-overview",
            "locator": "p. 1",
            "label": ""
          },
          {
            "from": "nubus",
            "to": "sdu",
            "type": "data",
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-2 bus converter",
            "label": ""
          },
          {
            "from": "sdu",
            "to": "nubus",
            "type": "data",
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-2",
            "label": ""
          },
          {
            "from": "sdu",
            "to": "multi",
            "type": "data",
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-2",
            "label": ""
          },
          {
            "from": "multi",
            "to": "sdu",
            "type": "data",
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-2",
            "label": ""
          },
          {
            "from": "disk",
            "to": "multi",
            "type": "data",
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-3 bus master",
            "label": ""
          },
          {
            "from": "multi",
            "to": "disk",
            "type": "data",
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-3",
            "label": ""
          },
          {
            "from": "net",
            "to": "multi",
            "type": "data",
            "source": "hist-lmi-lambda-service",
            "locator": "pp. 3-3–3-4",
            "label": ""
          },
          {
            "from": "multi",
            "to": "net",
            "type": "data",
            "source": "hist-lmi-lambda-service",
            "locator": "pp. 3-3–3-4",
            "label": ""
          },
          {
            "from": "console",
            "to": "lisp",
            "type": "association",
            "source": "hist-lmi-lambda-service",
            "locator": "p. 3-1 cabled user console",
            "label": ""
          }
        ]
      },
      "originalCandidate": "LMI Lambda"
    },
    {
      "id": "queue-057",
      "name": "Commodore Amiga 1000 — original NTSC architecture",
      "organization": "Commodore-Amiga",
      "year": 1986,
      "yearLabel": "1985–86 original-model service documents",
      "kind": "Heterogeneous multimedia personal computer",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-amiga1000-repair",
        "hist-amiga-copper-1989"
      ],
      "summary": "Agnus arbitrates shared display memory and runs DMA, blitter and beam-synchronized coprocessor work, while CPU-side RAM becomes protected system code after disk boot.",
      "config": "NTSC original A1000 with 256KB chip RAM, optional 256KB front expansion and separate 256KB protected processor RAM on daughterboard. Later Fat Agnus and ROM-based A500 boot excluded.",
      "gaps": [
        "The protected processor RAM is often called WCS; it stores system software, not CPU microinstructions.",
        "Component manual clock-crystal typography is inconsistent; the explicitly stated 7.15909MHz CPU clock is used.",
        "The later reference is used only for common Copper semantics and the explicit A1000 chip-memory ceiling."
      ],
      "originalName": "Commodore Amiga 1000",
      "insight": "How can the CPU execute protected boot-loaded code while custom chips consume shared RAM bandwidth?",
      "fields": {
        "state": {
          "value": "68000 16/32-bit processor and memory-mapped custom registers",
          "source": "hist-amiga1000-repair",
          "locator": "pp. 1-1–1-2"
        },
        "compute": {
          "value": "7.15909MHz NTSC CPU; Agnus blitter and display coprocessor",
          "source": "hist-amiga1000-repair",
          "locator": "pp. 1-2, 1-6"
        },
        "memory": {
          "value": "256KB shared display RAM; 256KB protected processor RAM",
          "source": "hist-amiga1000-repair",
          "locator": "pp. 1-2–1-3"
        },
        "control": {
          "value": "PAL bus arbitration delays DTACK while Agnus holds display bus",
          "source": "hist-amiga1000-repair",
          "locator": "p. 1-3"
        },
        "io": {
          "value": "Denise RGB; Paula audio/disk/serial; two 8520 peripheral chips",
          "source": "hist-amiga1000-repair",
          "locator": "pp. 1-2, 1-8–1-11"
        },
        "software": {
          "value": "Boot ROM loads disk code into subsequently write-protected RAM",
          "source": "hist-amiga1000-repair",
          "locator": "pp. 1-1–1-2"
        },
        "workload": {
          "value": "Concurrent graphics, animation, sound and personal computing",
          "source": "hist-amiga1000-repair",
          "locator": "pp. 1-1, 1-6–1-11"
        }
      },
      "diagram": {
        "title": "CPU-side protected code and shared custom-chip memory",
        "scope": "Original service Fig. p. 1-4 supplies bus relationships; the graph combines two CPU-side memories into one labeled boot/code domain.",
        "nodes": [
          {
            "id": "cpu",
            "label": "68000 CPU",
            "subtitle": "7.15909MHz NTSC",
            "text": "Executes boot, system and application instructions.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-amiga1000-repair",
            "locator": "pp. 1-1–1-2",
            "control": false
          },
          {
            "id": "private",
            "label": "Boot ROM / protected RAM",
            "subtitle": "256KB PROCESSOR RAM",
            "text": "Loads system code then prevents further writes.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-amiga1000-repair",
            "locator": "pp. 1-1–1-2",
            "control": false
          },
          {
            "id": "bridge",
            "label": "Bus control / multiplexers",
            "subtitle": "DTACK / DBR ARBITRATION",
            "text": "Connects CPU and display buses when available.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-3",
            "control": true
          },
          {
            "id": "chip",
            "label": "Display / chip RAM",
            "subtitle": "256KB + 256KB OPTION",
            "text": "Stores instructions, images, audio and DMA lists.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-3",
            "control": false
          },
          {
            "id": "agnus",
            "label": "Agnus",
            "subtitle": "DMA / BLITTER / COPPER",
            "text": "Addresses chip RAM and synchronizes display work.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-amiga1000-repair",
            "locator": "pp. 1-2, 1-6",
            "control": false
          },
          {
            "id": "denise",
            "label": "Denise",
            "subtitle": "PALETTE / SPRITES / RGB",
            "text": "Turns fetched display values into video output.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-amiga1000-repair",
            "locator": "pp. 1-8–1-9",
            "control": false
          },
          {
            "id": "paula",
            "label": "Paula",
            "subtitle": "FOUR AUDIO VOICES / I/O",
            "text": "Handles audio, disk data, serial and interrupts.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-amiga1000-repair",
            "locator": "pp. 1-10–1-11",
            "control": false
          },
          {
            "id": "cia",
            "label": "Two 8520 I/O chips",
            "subtitle": "TIMERS / CONTROL LINES",
            "text": "Control keyboard, disk status and peripheral signals.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-2",
            "control": false
          },
          {
            "id": "periph",
            "label": "Display / audio / disk / input",
            "subtitle": "EXTERNAL DEVICES",
            "text": "Receive video/audio and provide storage/user data.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-amiga1000-repair",
            "locator": "pp. 1-4, 1-8–1-11",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "private",
            "to": "cpu",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "pp. 1-1–1-2",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "private",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-2 loading before protection",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "bridge",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-4",
            "label": ""
          },
          {
            "from": "bridge",
            "to": "cpu",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-4",
            "label": ""
          },
          {
            "from": "bridge",
            "to": "chip",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-4",
            "label": ""
          },
          {
            "from": "chip",
            "to": "bridge",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-4",
            "label": ""
          },
          {
            "from": "agnus",
            "to": "bridge",
            "type": "control",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-3 DBR",
            "label": ""
          },
          {
            "from": "bridge",
            "to": "cpu",
            "type": "control",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-3 DTACK",
            "label": ""
          },
          {
            "from": "agnus",
            "to": "chip",
            "type": "control",
            "source": "hist-amiga1000-repair",
            "locator": "pp. 1-2–1-3 address/refresh",
            "label": ""
          },
          {
            "from": "chip",
            "to": "agnus",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-4",
            "label": ""
          },
          {
            "from": "agnus",
            "to": "chip",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-6 blitter writes",
            "label": ""
          },
          {
            "from": "chip",
            "to": "denise",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-4 shared data bus",
            "label": ""
          },
          {
            "from": "chip",
            "to": "paula",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-4",
            "label": ""
          },
          {
            "from": "agnus",
            "to": "denise",
            "type": "control",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-2 register-address bus",
            "label": ""
          },
          {
            "from": "agnus",
            "to": "paula",
            "type": "control",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-2 register-address bus",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "cia",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-2",
            "label": ""
          },
          {
            "from": "cia",
            "to": "periph",
            "type": "control",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-2",
            "label": ""
          },
          {
            "from": "denise",
            "to": "periph",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-8 RGB",
            "label": ""
          },
          {
            "from": "paula",
            "to": "periph",
            "type": "data",
            "source": "hist-amiga1000-repair",
            "locator": "p. 1-10 audio/disk",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Amiga 1000"
    },
    {
      "id": "queue-058",
      "name": "Nintendo NES-001 — NTSC control-deck organization",
      "organization": "Nintendo",
      "year": 1990,
      "yearLabel": "1990 service reference for NTSC front-loader",
      "kind": "Cartridge-programmed game console",
      "status": "dossier",
      "track": "mini",
      "trackName": "Minicomputers, workstations & personal systems",
      "discoveryParadigms": [
        "digital"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "stored-program",
        "unified",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "hist-nes-noa1990",
        "hist-nes-nakagawa-patent"
      ],
      "summary": "Separate CPU and picture-processing memory paths meet at the cartridge connector, while clock and reset circuitry coordinate game execution and NTSC output.",
      "config": "NTSC front-loading control deck documented in Rev11/90 service workbook; PAL, Famicom and NES-101 differences excluded. Cartridge mapper configuration unspecified.",
      "gaps": [
        "The 2KiB RAM interpretation follows the schematic’s 11 address/eight data pins; no cartridge RAM or mapper capacity is inferred.",
        "The patent corroborates cartridge/reset roles only: its illustrative CPU/PPU part numbers do not identify installed NES hardware.",
        "The diagram omits chip-internal sprite, palette and sound-channel details not established by the inspected service pages."
      ],
      "originalName": "Nintendo Entertainment System",
      "insight": "Why does the cartridge participate in both the CPU’s program path and the PPU’s picture path?",
      "fields": {
        "state": {
          "value": "Eight CPU data lines and separate PPU data/address path",
          "source": "hist-nes-noa1990",
          "locator": "Appendix B schematic, CPU U6 / PPU U5"
        },
        "compute": {
          "value": "CPU executes cartridge program; PPU generates picture data",
          "source": "hist-nes-noa1990",
          "locator": "Appendix B functional sections (PDF 95)"
        },
        "memory": {
          "value": "Separate WRAM and VRAM, each with 11 address and eight data lines",
          "source": "hist-nes-noa1990",
          "locator": "Appendix B schematic U1 / U4 (PDF 96)"
        },
        "control": {
          "value": "Shared 21MHz timing source; CIC reset reaches CPU and PPU",
          "source": "hist-nes-noa1990",
          "locator": "Appendix B functional sections and schematic"
        },
        "io": {
          "value": "Buffered controller ports and direct/RF audio/video output",
          "source": "hist-nes-noa1990",
          "locator": "Appendix B input/display sections"
        },
        "software": {
          "value": "Stored game instructions reside in the Game Pak",
          "source": "hist-nes-noa1990",
          "locator": "Appendix B program section"
        },
        "workload": {
          "value": "Interactive television video games",
          "source": "hist-nes-noa1990",
          "locator": "System Overview; Appendix B functional sections"
        }
      },
      "diagram": {
        "title": "CPU program path, PPU picture path and cartridge boundary",
        "scope": "Independent conceptual graph derived from device roles and connectivity; it does not duplicate the original circuit drawing or its layout.",
        "nodes": [
          {
            "id": "cpu",
            "label": "CPU U6",
            "subtitle": "EIGHT-BIT DATA PATH",
            "text": "Executes Game Pak instructions and generates sound.",
            "x": 28,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-nes-noa1990",
            "locator": "Appendix B program section / schematic",
            "control": false
          },
          {
            "id": "wram",
            "label": "Work RAM U1",
            "subtitle": "11 ADDRESS / 8 DATA",
            "text": "Retains mutable CPU-side state.",
            "x": 300,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-nes-noa1990",
            "locator": "Appendix B schematic",
            "control": false
          },
          {
            "id": "ppu",
            "label": "PPU U5 / address latch",
            "subtitle": "PICTURE PROCESSING",
            "text": "Accesses picture data and generates video.",
            "x": 572,
            "y": 20,
            "w": 202,
            "h": 66,
            "source": "hist-nes-noa1990",
            "locator": "Appendix B display section / schematic",
            "control": false
          },
          {
            "id": "vram",
            "label": "Video RAM U4",
            "subtitle": "11 ADDRESS / 8 DATA",
            "text": "Retains PPU-side display data.",
            "x": 28,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-nes-noa1990",
            "locator": "Appendix B schematic",
            "control": false
          },
          {
            "id": "pak",
            "label": "72-pin Game Pak interface",
            "subtitle": "PROGRAM / PICTURE / CIC LINES",
            "text": "Exposes cartridge memory and authentication signals.",
            "x": 300,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-nes-noa1990",
            "locator": "Appendix B schematic P1",
            "control": false
          },
          {
            "id": "input",
            "label": "Controller port buffers",
            "subtitle": "TWO INPUT PORTS",
            "text": "Buffer and protect user input signals.",
            "x": 572,
            "y": 170,
            "w": 202,
            "h": 66,
            "source": "hist-nes-noa1990",
            "locator": "Appendix B input section",
            "control": false
          },
          {
            "id": "clock",
            "label": "System timing source",
            "subtitle": "21MHz MASTER SIGNAL",
            "text": "Supplies timing to CPU and PPU.",
            "x": 28,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-nes-noa1990",
            "locator": "Appendix B timing section",
            "control": true
          },
          {
            "id": "reset",
            "label": "CIC / reset circuitry",
            "subtitle": "CPU AND PPU RESET",
            "text": "Coordinates reset with the cartridge interface.",
            "x": 300,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-nes-noa1990",
            "locator": "Appendix B reset section",
            "control": true
          },
          {
            "id": "output",
            "label": "Audio / video / RF module",
            "subtitle": "NTSC TV OUTPUT",
            "text": "Presents CPU sound and PPU image signals.",
            "x": 572,
            "y": 320,
            "w": 202,
            "h": 66,
            "source": "hist-nes-noa1990",
            "locator": "Appendix B display/program sections",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "wram",
            "to": "cpu",
            "type": "data",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B schematic U1↔U6",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "wram",
            "type": "data",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B schematic",
            "label": ""
          },
          {
            "from": "pak",
            "to": "cpu",
            "type": "data",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B program section / P1 data lines",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "pak",
            "type": "control",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B schematic CPU address lines",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "ppu",
            "type": "data",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B schematic U6 data↔U5 D0–D7",
            "label": ""
          },
          {
            "from": "ppu",
            "to": "cpu",
            "type": "control",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B schematic PPU INT→CPU NMI",
            "label": ""
          },
          {
            "from": "vram",
            "to": "ppu",
            "type": "data",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B schematic U4 / address latch",
            "label": ""
          },
          {
            "from": "ppu",
            "to": "vram",
            "type": "data",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B schematic",
            "label": ""
          },
          {
            "from": "pak",
            "to": "ppu",
            "type": "data",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B schematic P1 picture lines",
            "label": ""
          },
          {
            "from": "ppu",
            "to": "pak",
            "type": "control",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B schematic PPU address lines",
            "label": ""
          },
          {
            "from": "input",
            "to": "cpu",
            "type": "data",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B input section / schematic",
            "label": ""
          },
          {
            "from": "clock",
            "to": "cpu",
            "type": "control",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B timing section",
            "label": ""
          },
          {
            "from": "clock",
            "to": "ppu",
            "type": "control",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B timing section",
            "label": ""
          },
          {
            "from": "reset",
            "to": "cpu",
            "type": "control",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B reset section",
            "label": ""
          },
          {
            "from": "reset",
            "to": "ppu",
            "type": "control",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B reset section",
            "label": ""
          },
          {
            "from": "pak",
            "to": "reset",
            "type": "association",
            "source": "hist-nes-nakagawa-patent",
            "locator": "Description Fig. 2 lock/key role",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "output",
            "type": "data",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B program section sound",
            "label": ""
          },
          {
            "from": "ppu",
            "to": "output",
            "type": "data",
            "source": "hist-nes-noa1990",
            "locator": "Appendix B display section video",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Nintendo Entertainment System"
    },
    {
      "id": "queue-059",
      "name": "Ferranti Atlas — Manchester baseline",
      "organization": "Ferranti / University of Manchester",
      "year": 1962,
      "yearLabel": "1962 designer paper",
      "kind": "Built system configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "accumulator",
        "pipelined"
      ],
      "substrates": [
        "transistor"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-atlas-basic",
        "parallel-atlas-stores"
      ],
      "summary": "Automatic core/drum transfers support a one-level user store alongside separate arithmetic and executive resources.",
      "config": "Manchester/MUSE baseline in the 1962 paper; Atlas 2 and later installations are separate.",
      "gaps": [
        "The graph omits page replacement and associative translation detail; it is the system organization, not a timing model.",
        "The original paper distinguishes physical store capacities from addressable space."
      ],
      "insight": "Which storage movements disappear from the programmer’s view?",
      "fields": {
        "state": {
          "value": "48-bit words; 24-bit half-words",
          "source": "parallel-atlas-stores",
          "locator": "p.278, basic machine"
        },
        "compute": {
          "value": "Main accumulator and independent B-arithmetic",
          "source": "parallel-atlas-stores",
          "locator": "p.277, basic machine"
        },
        "memory": {
          "value": "16K core words and 96K drum words in the baseline",
          "source": "parallel-atlas-stores",
          "locator": "p.277, central store"
        },
        "control": {
          "value": "Main, extracode, and interrupt controls",
          "source": "parallel-atlas-stores",
          "locator": "pp.277–278"
        },
        "io": {
          "value": "Peripheral command registers in V-store",
          "source": "parallel-atlas-stores",
          "locator": "p.277, V-store"
        },
        "software": {
          "value": "Fixed-store extracodes and supervisory routines",
          "source": "parallel-atlas-basic",
          "locator": "§2, basic machine"
        },
        "workload": {
          "value": "Multiprogrammed general-purpose computation",
          "source": "parallel-atlas-basic",
          "locator": "Introduction"
        }
      },
      "diagram": {
        "title": "One-level user storage and private executive resources",
        "scope": "Logical relationships from the original basic-machine description; drum/tape reach arithmetic through core.",
        "width": 1145,
        "height": 460,
        "nodes": [
          {
            "id": "a",
            "label": "Main accumulator",
            "subtitle": "ARITHMETIC",
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            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "control": false
          },
          {
            "id": "b",
            "label": "B-store + B arithmetic",
            "subtitle": "INDEX / CONTROL",
            "text": "Independent arithmetic path.",
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            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "control": false
          },
          {
            "id": "fixed",
            "label": "Fixed store",
            "subtitle": "EXECUTIVE / EXTRACODES",
            "text": "Read-only routines.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "control": false
          },
          {
            "id": "work",
            "label": "Subsidiary core",
            "subtitle": "PRIVATE WORKSPACE",
            "text": "Executive working state.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "control": false
          },
          {
            "id": "core",
            "label": "Main core store",
            "subtitle": "4 × 4K WORD STACKS",
            "text": "Immediate user storage.",
            "x": 250,
            "y": 190,
            "w": 184,
            "h": 68,
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "control": false
          },
          {
            "id": "transfer",
            "label": "Automatic transfers",
            "subtitle": "ONE-LEVEL STORE",
            "text": "Moves core/drum blocks.",
            "x": 480,
            "y": 190,
            "w": 184,
            "h": 68,
            "source": "parallel-atlas-basic",
            "locator": "Summary",
            "control": true
          },
          {
            "id": "drum",
            "label": "Drum store",
            "subtitle": "BACKING LEVEL",
            "text": "512-word block transfers.",
            "x": 710,
            "y": 190,
            "w": 184,
            "h": 68,
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "control": false
          },
          {
            "id": "tape",
            "label": "Tape store",
            "subtitle": "PERSISTENT BACKING",
            "text": "Transfers through core.",
            "x": 20,
            "y": 350,
            "w": 184,
            "h": 68,
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "control": false
          },
          {
            "id": "v",
            "label": "V-store registers",
            "subtitle": "PERIPHERAL COMMANDS",
            "text": "Addressed device control.",
            "x": 710,
            "y": 350,
            "w": 184,
            "h": 68,
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "control": true
          }
        ],
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          {
            "from": "core",
            "to": "a",
            "type": "data",
            "source": "parallel-atlas-basic",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "a",
            "to": "core",
            "type": "data",
            "source": "parallel-atlas-basic",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "core",
            "to": "b",
            "type": "data",
            "source": "parallel-atlas-basic",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "b",
            "to": "core",
            "type": "data",
            "source": "parallel-atlas-basic",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "fixed",
            "to": "a",
            "type": "data",
            "source": "parallel-atlas-basic",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "fixed",
            "to": "b",
            "type": "data",
            "source": "parallel-atlas-basic",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "fixed",
            "to": "work",
            "type": "association",
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "label": ""
          },
          {
            "from": "core",
            "to": "transfer",
            "type": "association",
            "source": "parallel-atlas-basic",
            "locator": "Summary",
            "label": ""
          },
          {
            "from": "transfer",
            "to": "drum",
            "type": "association",
            "source": "parallel-atlas-basic",
            "locator": "Summary",
            "label": ""
          },
          {
            "from": "drum",
            "to": "core",
            "type": "data",
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "label": ""
          },
          {
            "from": "core",
            "to": "drum",
            "type": "data",
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "label": ""
          },
          {
            "from": "tape",
            "to": "core",
            "type": "data",
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "label": ""
          },
          {
            "from": "core",
            "to": "tape",
            "type": "data",
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "label": ""
          },
          {
            "from": "b",
            "to": "v",
            "type": "control",
            "source": "parallel-atlas-stores",
            "locator": "p.277",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Ferranti Atlas"
    },
    {
      "id": "queue-060",
      "name": "CDC 7600 — preliminary reference organization",
      "organization": "Control Data Corporation",
      "year": null,
      "yearLabel": "Undated preliminary manual",
      "kind": "Documented preliminary system configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
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      "paradigms": [
        "digital",
        "parallel"
      ],
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        "stored-program",
        "scalar",
        "pipelined",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-7600"
      ],
      "summary": "Nine segmented arithmetic units operate through register banks, two memory classes, and autonomous peripheral processors.",
      "config": "The preliminary manual’s 64Kword SCM/512Kword LCM organization; production revisions and draft timing are outside scope.",
      "gaps": [
        "The scan does not establish a reliable publication date or final production clock.",
        "The draft describes capacities and revisions that must not be silently merged with later installations."
      ],
      "insight": "How do instruction buffering and peripheral processors relieve the central processor?",
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        "state": {
          "value": "60-bit CPU words;12-bit PPU words",
          "source": "parallel-7600",
          "locator": "p.1-1"
        },
        "compute": {
          "value": "Nine arithmetic units; X/A/B register banks",
          "source": "parallel-7600",
          "locator": "pp.1-6–1-8, Fig.1-2"
        },
        "memory": {
          "value": "32-bank Small Core and8-bank Large Core Memory",
          "source": "parallel-7600",
          "locator": "pp.1-5–1-6"
        },
        "control": {
          "value": "Twelve-word instruction stack; current-instruction control",
          "source": "parallel-7600",
          "locator": "p.1-8"
        },
        "io": {
          "value": "Fifteen CPU channels; assembly/disassembly to PPUs",
          "source": "parallel-7600",
          "locator": "pp.1-1–1-4"
        },
        "software": {
          "value": "Resident SCM monitor with LCM overlays",
          "source": "parallel-7600",
          "locator": "p.1-4"
        },
        "workload": {
          "value": "FORTRAN and general arithmetic programs",
          "source": "parallel-7600",
          "locator": "pp.1-0,1-4"
        }
      },
      "diagram": {
        "title": "Segmented computation and peripheral autonomy",
        "scope": "Selected preliminary reference paths. X, A and B roles are separated; channels convert CPU and PPU word sizes.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "stack",
            "label": "Instruction stack",
            "subtitle": "12 CPU WORDS",
            "text": "Buffers instruction sequences.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-7600",
            "locator": "p.1-8",
            "control": false
          },
          {
            "id": "ctrl",
            "label": "Instruction control",
            "subtitle": "CURRENT WORD",
            "text": "Decodes buffered instructions.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-7600",
            "locator": "Fig.1-2",
            "control": true
          },
          {
            "id": "x",
            "label": "X registers",
            "subtitle": "8 ×60 BITS",
            "text": "Arithmetic operands/results.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-7600",
            "locator": "p.1-8",
            "control": false
          },
          {
            "id": "fu",
            "label": "Nine arithmetic units",
            "subtitle": "SEGMENTED UNITS",
            "text": "Independent arithmetic paths.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-7600",
            "locator": "pp.1-6–1-7",
            "control": false
          },
          {
            "id": "ab",
            "label": "A / B registers",
            "subtitle": "18-BIT ADDRESS / INDEX",
            "text": "A controls associated X transfer.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-7600",
            "locator": "p.1-8",
            "control": false
          },
          {
            "id": "scm",
            "label": "Small Core Memory",
            "subtitle": "64KWORDS /32 BANKS",
            "text": "Instructions, active data, monitor.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-7600",
            "locator": "p.1-5",
            "control": false
          },
          {
            "id": "lcm",
            "label": "Large Core Memory",
            "subtitle": "512KWORDS /8 BANKS",
            "text": "Larger working store.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-7600",
            "locator": "p.1-6",
            "control": false
          },
          {
            "id": "io",
            "label": "CPU I/O section",
            "subtitle": "15 DUPLEX CHANNELS",
            "text": "60/12-bit assembly.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-7600",
            "locator": "pp.1-3–1-4",
            "control": false
          },
          {
            "id": "ppu",
            "label": "Peripheral processors",
            "subtitle": "12-BIT /LOCAL CORE",
            "text": "Independent device work.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-7600",
            "locator": "pp.1-1–1-3",
            "control": false
          },
          {
            "id": "dev",
            "label": "Equipment controllers",
            "subtitle": "PERIPHERAL EQUIPMENT",
            "text": "Tape, disk, cards, display.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-7600",
            "locator": "Fig.1-1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "scm",
            "to": "stack",
            "type": "data",
            "source": "parallel-7600",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "stack",
            "to": "ctrl",
            "type": "control",
            "source": "parallel-7600",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "ctrl",
            "to": "fu",
            "type": "control",
            "source": "parallel-7600",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "x",
            "to": "fu",
            "type": "data",
            "source": "parallel-7600",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "fu",
            "to": "x",
            "type": "data",
            "source": "parallel-7600",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "ab",
            "to": "scm",
            "type": "control",
            "source": "parallel-7600",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "scm",
            "to": "x",
            "type": "data",
            "source": "parallel-7600",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "x",
            "to": "scm",
            "type": "data",
            "source": "parallel-7600",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "lcm",
            "to": "x",
            "type": "data",
            "source": "parallel-7600",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "x",
            "to": "lcm",
            "type": "data",
            "source": "parallel-7600",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "scm",
            "to": "lcm",
            "type": "data",
            "source": "parallel-7600",
            "locator": "Fig.1-1",
            "label": ""
          },
          {
            "from": "scm",
            "to": "io",
            "type": "data",
            "source": "parallel-7600",
            "locator": "Fig.1-1",
            "label": ""
          },
          {
            "from": "io",
            "to": "ppu",
            "type": "data",
            "source": "parallel-7600",
            "locator": "pp.1-3–1-4",
            "label": ""
          },
          {
            "from": "ppu",
            "to": "dev",
            "type": "data",
            "source": "parallel-7600",
            "locator": "Fig.1-1",
            "label": ""
          }
        ]
      },
      "originalCandidate": "CDC 7600"
    },
    {
      "id": "queue-061",
      "name": "CDC STAR-100 — revision09 basic system",
      "organization": "Control Data Corporation",
      "year": 1975,
      "yearLabel": "December1975 manual revision",
      "kind": "Commercial reference configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "vector",
        "pipelined",
        "microcoded"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-star"
      ],
      "summary": "Memory-to-memory streams pass through alignment networks and arithmetic pipes, alongside register and string operations.",
      "config": "Basic524288-word system with four I/O channels in60256000-09; optional memory/channel expansions are excluded.",
      "gaps": [
        "The hardware register file supports addressing/scalar work; it is not a Cray-style vector-register file.",
        "Full vector startup timing and software OS configuration are not reconstructed."
      ],
      "insight": "What changes when vectors stream from memory instead of living in vector registers?",
      "fields": {
        "state": {
          "value": "64-bit words;32/64-bit floating operands; bit/byte strings",
          "source": "parallel-star",
          "locator": "p.1-1"
        },
        "compute": {
          "value": "Two floating pipes and separate string unit",
          "source": "parallel-star",
          "locator": "pp.1-1,1-4"
        },
        "memory": {
          "value": "524288 words,32 core banks; virtual addressing",
          "source": "parallel-star",
          "locator": "pp.1-3,2-1"
        },
        "control": {
          "value": "Stream instruction control and vector-setup microcode",
          "source": "parallel-star",
          "locator": "p.1-1"
        },
        "io": {
          "value": "SAC-controlled16-bit channels and peripheral stations",
          "source": "parallel-star",
          "locator": "p.1-2"
        },
        "software": {
          "value": "Register, vector, string and macro instruction interface",
          "source": "parallel-star",
          "locator": "§§3,6"
        },
        "workload": {
          "value": "Long floating-point arrays and string processing",
          "source": "parallel-star",
          "locator": "p.1-1"
        }
      },
      "diagram": {
        "title": "Memory streams, alignment, arithmetic, and writeback",
        "scope": "Conceptual decomposition of the stream unit. Three read buses and two write paths are aggregated by role.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "mcs",
            "label": "Core memory",
            "subtitle": "32 BANKS /SUPERWORDS",
            "text": "Holds vectors and instructions.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-star",
            "locator": "§2",
            "control": false
          },
          {
            "id": "sac",
            "label": "Storage Access Control",
            "subtitle": "TRANSLATION /ARBITRATION",
            "text": "Memory and I/O access.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-star",
            "locator": "§3, Fig.3-1",
            "control": false
          },
          {
            "id": "input",
            "label": "Stream input buffers",
            "subtitle": "READ STREAMS A /B",
            "text": "Aligns operand traffic.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-star",
            "locator": "p.3-23",
            "control": false
          },
          {
            "id": "align",
            "label": "Operand shift network",
            "subtitle": "32-BIT ALIGNMENT",
            "text": "Pairs floating operands.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-star",
            "locator": "p.3-26",
            "control": false
          },
          {
            "id": "fp",
            "label": "Floating pipes1 /2",
            "subtitle": "DUAL SEGMENTED PIPES",
            "text": "Floating arithmetic.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-star",
            "locator": "Figs.3-12/3-13",
            "control": false
          },
          {
            "id": "instr",
            "label": "Instruction stack/control",
            "subtitle": "FOUR SUPERWORDS",
            "text": "Stream setup and microcode.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-star",
            "locator": "pp.3-20–3-22",
            "control": true
          },
          {
            "id": "rf",
            "label": "Register file",
            "subtitle": "256 ×64 BITS",
            "text": "Addressing and register operands.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-star",
            "locator": "pp.3-23–3-25",
            "control": false
          },
          {
            "id": "string",
            "label": "String unit",
            "subtitle": "BIT /BYTE STREAMS",
            "text": "Logical and numeric strings.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-star",
            "locator": "p.3-27",
            "control": false
          },
          {
            "id": "write",
            "label": "Data interchange/writeback",
            "subtitle": "C-STREAM REALIGNMENT",
            "text": "Routes results to storage.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-star",
            "locator": "p.3-26",
            "control": false
          },
          {
            "id": "io",
            "label": "I/O channels/stations",
            "subtitle": "FOUR BASIC CHANNELS",
            "text": "MCU and device stations.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-star",
            "locator": "pp.1-2–1-4",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "mcs",
            "to": "sac",
            "type": "data",
            "source": "parallel-star",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "sac",
            "to": "input",
            "type": "data",
            "source": "parallel-star",
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            "label": ""
          },
          {
            "from": "sac",
            "to": "instr",
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          },
          {
            "from": "instr",
            "to": "input",
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            "label": ""
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          {
            "from": "input",
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          },
          {
            "from": "rf",
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            "label": ""
          },
          {
            "from": "align",
            "to": "fp",
            "type": "data",
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            "label": ""
          },
          {
            "from": "fp",
            "to": "write",
            "type": "data",
            "source": "parallel-star",
            "locator": "p.3-26",
            "label": ""
          },
          {
            "from": "input",
            "to": "string",
            "type": "data",
            "source": "parallel-star",
            "locator": "p.3-27",
            "label": ""
          },
          {
            "from": "string",
            "to": "write",
            "type": "data",
            "source": "parallel-star",
            "locator": "p.3-26",
            "label": ""
          },
          {
            "from": "write",
            "to": "sac",
            "type": "data",
            "source": "parallel-star",
            "locator": "p.3-26",
            "label": ""
          },
          {
            "from": "sac",
            "to": "mcs",
            "type": "data",
            "source": "parallel-star",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "sac",
            "to": "io",
            "type": "data",
            "source": "parallel-star",
            "locator": "p.1-2",
            "label": ""
          }
        ]
      },
      "originalCandidate": "CDC STAR-100"
    },
    {
      "id": "queue-062",
      "name": "Cray X-MP/24 —1984 reference",
      "organization": "Cray Research",
      "year": 1984,
      "yearLabel": "July1984 revisionA manual",
      "kind": "Commercial system configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
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        "stored-program",
        "vector",
        "smp",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-xmp"
      ],
      "summary": "Two vector CPUs share memory and register clusters; flexible chaining overlaps dependent vector operations.",
      "config": "X-MP/24: two CPUs and four million64-bit words; optional SSD represented separately.",
      "gaps": [
        "Port C also serves scalar traffic; the graph expands its vector-store role.",
        "Two simultaneous loads do not guarantee conflict-free bank access."
      ],
      "insight": "How do dual reads, a store port, and chaining expose different kinds of concurrency?",
      "fields": {
        "state": {
          "value": "64-bit data; eight64-element V registers/CPU",
          "source": "parallel-xmp",
          "locator": "p.4-9"
        },
        "compute": {
          "value": "Two scalar/vector CPUs",
          "source": "parallel-xmp",
          "locator": "pp.1-1–1-3"
        },
        "memory": {
          "value": "4Mword shared Central Memory",
          "source": "parallel-xmp",
          "locator": "p.1-3"
        },
        "control": {
          "value": "Per-CPU issue plus shared-register clusters/semaphores",
          "source": "parallel-xmp",
          "locator": "pp.2-10–2-13"
        },
        "io": {
          "value": "Separate I/O Subsystem; optional SSD",
          "source": "parallel-xmp",
          "locator": "§1"
        },
        "software": {
          "value": "COS; FORTRAN compiler handles long-vector loops",
          "source": "parallel-xmp",
          "locator": "§1; p.4-11"
        },
        "workload": {
          "value": "Scientific scalar/vector and multitasking programs",
          "source": "parallel-xmp",
          "locator": "§1"
        }
      },
      "diagram": {
        "title": "Dual-CPU sharing and flexible vector chaining",
        "scope": "CPU0 expanded; CPU1 aggregated. Chaining forwards a result stream through the destination register.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "issue",
            "label": "CPU0 instruction issue",
            "subtitle": "RESERVATION CHECKS",
            "text": "Issues independent work.",
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            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-xmp",
            "locator": "§§3–4",
            "control": true
          },
          {
            "id": "v",
            "label": "CPU0 vector registers",
            "subtitle": "8 ×64 ELEMENTS",
            "text": "Operands and result streams.",
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            "w": 184,
            "h": 68,
            "source": "parallel-xmp",
            "locator": "p.4-9",
            "control": false
          },
          {
            "id": "fu",
            "label": "CPU0 vector units",
            "subtitle": "PIPELINED ARITHMETIC",
            "text": "Computes and chains.",
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            "h": 68,
            "source": "parallel-xmp",
            "locator": "pp.4-11–4-12",
            "control": false
          },
          {
            "id": "read",
            "label": "CPU0 read portsA/B",
            "subtitle": "TWO BLOCK READS",
            "text": "Independent read reservations.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-xmp",
            "locator": "pp.2-4–2-5",
            "control": false
          },
          {
            "id": "store",
            "label": "CPU0 portC",
            "subtitle": "VECTOR STORE /SCALAR",
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            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-xmp",
            "locator": "p.2-5",
            "control": false
          },
          {
            "id": "memory",
            "label": "Central Memory",
            "subtitle": "4MWORDS /BANKED",
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            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-xmp",
            "locator": "§2",
            "control": false
          },
          {
            "id": "cpu1",
            "label": "CPU1",
            "subtitle": "INDEPENDENT CONTROL",
            "text": "Same execution organization.",
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            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-xmp",
            "locator": "Fig.1-2",
            "control": false
          },
          {
            "id": "cluster",
            "label": "Shared clusters",
            "subtitle": "SB /ST /SEMAPHORES",
            "text": "Communication/synchronization.",
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            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-xmp",
            "locator": "pp.2-11–2-13",
            "control": true
          },
          {
            "id": "ios",
            "label": "I/O Subsystem",
            "subtitle": "IOPs /BUFFER MEMORY",
            "text": "Coordinates with COS.",
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            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-xmp",
            "locator": "§1",
            "control": false
          },
          {
            "id": "ssd",
            "label": "Optional SSD",
            "subtitle": "SOLID-STATE STORAGE",
            "text": "High-speed storage channels.",
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            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-xmp",
            "locator": "§1",
            "control": false
          }
        ],
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            "to": "v",
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            "label": ""
          },
          {
            "from": "memory",
            "to": "read",
            "type": "data",
            "source": "parallel-xmp",
            "locator": "p.2-5",
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          {
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          {
            "from": "v",
            "to": "fu",
            "type": "data",
            "source": "parallel-xmp",
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          },
          {
            "from": "fu",
            "to": "v",
            "type": "data",
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            "label": "result stream"
          },
          {
            "from": "v",
            "to": "store",
            "type": "data",
            "source": "parallel-xmp",
            "locator": "p.2-5",
            "label": ""
          },
          {
            "from": "store",
            "to": "memory",
            "type": "data",
            "source": "parallel-xmp",
            "locator": "p.2-5",
            "label": ""
          },
          {
            "from": "cpu1",
            "to": "memory",
            "type": "data",
            "source": "parallel-xmp",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "memory",
            "to": "cpu1",
            "type": "data",
            "source": "parallel-xmp",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "issue",
            "to": "cluster",
            "type": "association",
            "source": "parallel-xmp",
            "locator": "p.2-11",
            "label": ""
          },
          {
            "from": "cpu1",
            "to": "cluster",
            "type": "association",
            "source": "parallel-xmp",
            "locator": "p.2-11",
            "label": ""
          },
          {
            "from": "ios",
            "to": "memory",
            "type": "data",
            "source": "parallel-xmp",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "ssd",
            "to": "memory",
            "type": "data",
            "source": "parallel-xmp",
            "locator": "§1",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Cray X-MP"
    },
    {
      "id": "queue-063",
      "name": "Cray-2 — four-background-processor system",
      "organization": "Cray Research",
      "year": 1985,
      "yearLabel": "May 1985 manual configuration",
      "kind": "Commercial system configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
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        "stored-program",
        "vector",
        "smp",
        "heterogeneous",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-cray2"
      ],
      "summary": "Four vector/scalar background processors share Common Memory while a foreground processor supervises execution and I/O.",
      "config": "HR-2000 four-background-processor configuration; later memory variants are excluded.",
      "gaps": [
        "Local Memory and Common Memory have different roles; the graph does not imply a coherent cache hierarchy.",
        "Ports and functional units are aggregated; exact reservation timing needs instruction-specific treatment."
      ],
      "insight": "Why separate foreground supervision from background arithmetic?",
      "fields": {
        "state": {
          "value": "64-bit scalar/vector operands",
          "source": "parallel-cray2",
          "locator": "§1.2; §2"
        },
        "compute": {
          "value": "Four background processors; one foreground processor",
          "source": "parallel-cray2",
          "locator": "§1.1.2"
        },
        "memory": {
          "value": "Shared Common Memory plus per-processor Local Memory",
          "source": "parallel-cray2",
          "locator": "§1.1; §4"
        },
        "control": {
          "value": "Independent issue controls and semaphore flags",
          "source": "parallel-cray2",
          "locator": "§2.1"
        },
        "io": {
          "value": "Foreground channels connect memory and external interfaces",
          "source": "parallel-cray2",
          "locator": "§5.1–5.2"
        },
        "software": {
          "value": "CAL Version2 instruction interface",
          "source": "parallel-cray2",
          "locator": "§1.3; §3"
        },
        "workload": {
          "value": "Scalar/vector jobs or cooperating parallel work",
          "source": "parallel-cray2",
          "locator": "§1.1"
        }
      },
      "diagram": {
        "title": "Foreground supervision and one expanded background processor",
        "scope": "BP0 is expanded; BP1–3 are aggregated. Lines summarize documented transfers/control, not module wiring.",
        "width": 1145,
        "height": 460,
        "nodes": [
          {
            "id": "fg",
            "label": "Foreground processor",
            "subtitle": "SYSTEM SUPERVISION",
            "text": "Supervises background work.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cray2",
            "locator": "§1.1.2",
            "control": true
          },
          {
            "id": "issue",
            "label": "BP0 issue control",
            "subtitle": "INSTRUCTION BUFFERS",
            "text": "Issues background instructions.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cray2",
            "locator": "§2.1",
            "control": true
          },
          {
            "id": "regs",
            "label": "BP0 A/S/V registers",
            "subtitle": "OPERANDS / RESULTS",
            "text": "Registers feed arithmetic.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cray2",
            "locator": "Fig.2-1",
            "control": false
          },
          {
            "id": "fu",
            "label": "BP0 functional units",
            "subtitle": "SCALAR + VECTOR",
            "text": "Pipelined computation.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cray2",
            "locator": "Fig.2-1",
            "control": false
          },
          {
            "id": "local",
            "label": "BP0 Local Memory",
            "subtitle": "TEMPORARY DATA",
            "text": "Processor-local storage.",
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            "y": 190,
            "w": 184,
            "h": 68,
            "source": "parallel-cray2",
            "locator": "§1.1; §2",
            "control": false
          },
          {
            "id": "common",
            "label": "Common Memory",
            "subtitle": "SHARED MEMORY",
            "text": "Accessible by all BPs.",
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            "y": 350,
            "w": 184,
            "h": 68,
            "source": "parallel-cray2",
            "locator": "§4",
            "control": false
          },
          {
            "id": "other",
            "label": "Background processors1–3",
            "subtitle": "SAME ORGANIZATION",
            "text": "Independent cooperating BPs.",
            "x": 710,
            "y": 350,
            "w": 184,
            "h": 68,
            "source": "parallel-cray2",
            "locator": "§1.1.2",
            "control": false
          },
          {
            "id": "channels",
            "label": "Foreground channels",
            "subtitle": "I/O DATA PATH",
            "text": "Synchronous channel loops.",
            "x": 20,
            "y": 190,
            "w": 184,
            "h": 68,
            "source": "parallel-cray2",
            "locator": "§5.1",
            "control": false
          },
          {
            "id": "external",
            "label": "Disks / front ends",
            "subtitle": "EXTERNAL INTERFACES",
            "text": "Configured I/O equipment.",
            "x": 20,
            "y": 350,
            "w": 184,
            "h": 68,
            "source": "parallel-cray2",
            "locator": "§5.3–5.4",
            "control": false
          }
        ],
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          {
            "from": "fg",
            "to": "issue",
            "type": "control",
            "source": "parallel-cray2",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "issue",
            "to": "regs",
            "type": "control",
            "source": "parallel-cray2",
            "locator": "Fig.2-1",
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          },
          {
            "from": "regs",
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            "source": "parallel-cray2",
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          },
          {
            "from": "fu",
            "to": "regs",
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          },
          {
            "from": "regs",
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          },
          {
            "from": "local",
            "to": "regs",
            "type": "data",
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          },
          {
            "from": "regs",
            "to": "common",
            "type": "data",
            "source": "parallel-cray2",
            "locator": "Fig.2-1",
            "label": ""
          },
          {
            "from": "common",
            "to": "regs",
            "type": "data",
            "source": "parallel-cray2",
            "locator": "Fig.2-1",
            "label": ""
          },
          {
            "from": "other",
            "to": "common",
            "type": "data",
            "source": "parallel-cray2",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "common",
            "to": "other",
            "type": "data",
            "source": "parallel-cray2",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "fg",
            "to": "channels",
            "type": "control",
            "source": "parallel-cray2",
            "locator": "§5",
            "label": ""
          },
          {
            "from": "channels",
            "to": "common",
            "type": "data",
            "source": "parallel-cray2",
            "locator": "Fig.1-2",
            "label": ""
          },
          {
            "from": "external",
            "to": "channels",
            "type": "data",
            "source": "parallel-cray2",
            "locator": "§5",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Cray-2"
    },
    {
      "id": "queue-064",
      "name": "Cray Y-MP8/832",
      "organization": "Cray Research",
      "year": 1990,
      "yearLabel": "June 1990 model832 specification",
      "kind": "Documented commercial configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "vector",
        "smp",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-ymp"
      ],
      "summary": "Eight register-vector CPUs share interleaved memory and synchronization registers, with a separate I/O subsystem.",
      "config": "Model832: eight CPUs and32Mwords, as documented in HR-04001-0C; not a named installation.",
      "gaps": [
        "Optional SSD and peripheral counts depend on the site.",
        "The graph expands CPU0’s vector path and aggregates its other units."
      ],
      "insight": "Which resources are private to each CPU and which coordinate the machine?",
      "fields": {
        "state": {
          "value": "64-bit data; eight64-element vector registers per CPU",
          "source": "parallel-ymp",
          "locator": "Y-MP8 specification, p.2-69"
        },
        "compute": {
          "value": "Eight CPUs",
          "source": "parallel-ymp",
          "locator": "Model832 table, p.2-70"
        },
        "memory": {
          "value": "32Mwords shared Central Memory",
          "source": "parallel-ymp",
          "locator": "Model832 table, p.2-70"
        },
        "control": {
          "value": "Per-CPU issue; shared address/scalar/semaphore clusters",
          "source": "parallel-ymp",
          "locator": "§2, interprocessor communication"
        },
        "io": {
          "value": "I/O processors, Buffer Memory, and optional SSD",
          "source": "parallel-ymp",
          "locator": "§§1,3–4"
        },
        "software": {
          "value": "UNICOS or COS; CFT/CFT77 and multitasking support",
          "source": "parallel-ymp",
          "locator": "§6"
        },
        "workload": {
          "value": "Scalar, vector, and multiprocessor programs",
          "source": "parallel-ymp",
          "locator": "§1"
        }
      },
      "diagram": {
        "title": "Eight CPUs, shared-memory coordination, separate I/O",
        "scope": "One CPU is expanded. Optional SSD is labeled as optional; this is not a maximal installation diagram.",
        "width": 1145,
        "height": 460,
        "nodes": [
          {
            "id": "issue",
            "label": "CPU0 control",
            "subtitle": "INSTRUCTION ISSUE",
            "text": "Coordinates execution.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ymp",
            "locator": "§2",
            "control": true
          },
          {
            "id": "v",
            "label": "CPU0 V registers",
            "subtitle": "VECTOR OPERANDS",
            "text": "Eight register vectors.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ymp",
            "locator": "§2, vector registers",
            "control": false
          },
          {
            "id": "fu",
            "label": "CPU0 arithmetic",
            "subtitle": "FUNCTIONAL UNITS",
            "text": "Scalar/vector results.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ymp",
            "locator": "§2, computation",
            "control": false
          },
          {
            "id": "cpus",
            "label": "CPUs1–7",
            "subtitle": "PRIVATE EXECUTION",
            "text": "Same CPU organization.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ymp",
            "locator": "Model832",
            "control": false
          },
          {
            "id": "shared",
            "label": "Shared-register clusters",
            "subtitle": "SB / ST / SEMAPHORES",
            "text": "Interprocessor communication.",
            "x": 710,
            "y": 190,
            "w": 184,
            "h": 68,
            "source": "parallel-ymp",
            "locator": "§2, shared resources",
            "control": true
          },
          {
            "id": "mem",
            "label": "Central Memory",
            "subtitle": "32MWORDS / INTERLEAVED",
            "text": "Shared data storage.",
            "x": 250,
            "y": 190,
            "w": 184,
            "h": 68,
            "source": "parallel-ymp",
            "locator": "Model832; §2",
            "control": false
          },
          {
            "id": "iop",
            "label": "I/O processors",
            "subtitle": "SEPARATE I/O SUBSYSTEM",
            "text": "Device and channel handling.",
            "x": 20,
            "y": 350,
            "w": 184,
            "h": 68,
            "source": "parallel-ymp",
            "locator": "§3",
            "control": false
          },
          {
            "id": "buffer",
            "label": "Buffer Memory",
            "subtitle": "I/O STAGING",
            "text": "Shared among IOPs.",
            "x": 250,
            "y": 350,
            "w": 184,
            "h": 68,
            "source": "parallel-ymp",
            "locator": "§3",
            "control": false
          },
          {
            "id": "ssd",
            "label": "Optional SSD",
            "subtitle": "TEMPORARY STORAGE",
            "text": "Separate high-speed channels.",
            "x": 480,
            "y": 350,
            "w": 184,
            "h": 68,
            "source": "parallel-ymp",
            "locator": "§4",
            "control": false
          },
          {
            "id": "devices",
            "label": "Front ends / disks",
            "subtitle": "CONFIGURED DEVICES",
            "text": "External data paths.",
            "x": 710,
            "y": 350,
            "w": 184,
            "h": 68,
            "source": "parallel-ymp",
            "locator": "§§1,3",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "issue",
            "to": "v",
            "type": "control",
            "source": "parallel-ymp",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "v",
            "to": "fu",
            "type": "data",
            "source": "parallel-ymp",
            "locator": "§2, computation",
            "label": ""
          },
          {
            "from": "fu",
            "to": "v",
            "type": "data",
            "source": "parallel-ymp",
            "locator": "§2, computation",
            "label": ""
          },
          {
            "from": "v",
            "to": "mem",
            "type": "data",
            "source": "parallel-ymp",
            "locator": "§2, computation",
            "label": ""
          },
          {
            "from": "mem",
            "to": "v",
            "type": "data",
            "source": "parallel-ymp",
            "locator": "§2, computation",
            "label": ""
          },
          {
            "from": "cpus",
            "to": "mem",
            "type": "data",
            "source": "parallel-ymp",
            "locator": "§2, shared resources",
            "label": ""
          },
          {
            "from": "issue",
            "to": "shared",
            "type": "association",
            "source": "parallel-ymp",
            "locator": "§2, shared registers",
            "label": ""
          },
          {
            "from": "cpus",
            "to": "shared",
            "type": "association",
            "source": "parallel-ymp",
            "locator": "§2, shared registers",
            "label": ""
          },
          {
            "from": "iop",
            "to": "buffer",
            "type": "data",
            "source": "parallel-ymp",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "buffer",
            "to": "mem",
            "type": "data",
            "source": "parallel-ymp",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "mem",
            "to": "ssd",
            "type": "data",
            "source": "parallel-ymp",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "ssd",
            "to": "mem",
            "type": "data",
            "source": "parallel-ymp",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "devices",
            "to": "iop",
            "type": "data",
            "source": "parallel-ymp",
            "locator": "§3",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Cray Y-MP"
    },
    {
      "id": "queue-065",
      "name": "Cray T3D —1993 two-PE-node organization",
      "organization": "Cray Research",
      "year": 1993,
      "yearLabel": "September1993 original manual",
      "kind": "Commercial reference configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "distributed",
        "numa",
        "risc"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-t3d"
      ],
      "summary": "Two independent processing elements share each torus-node interface and block-transfer engine.",
      "config": "HR-04033 architecture with32–2048 PEs; graph depicts one node, without asserting a specific installed size.",
      "gaps": [
        "A reference node, not a named installation; capacities remain parameterized.",
        "Global addressability does not establish automatic coherent caching of all remote data."
      ],
      "insight": "Which resources are private to a PE and shared by its partner?",
      "fields": {
        "state": {
          "value": "64-bit integer/floating registers",
          "source": "parallel-t3d",
          "locator": "p.1-3"
        },
        "compute": {
          "value": "Two DEC RISC microprocessors per node",
          "source": "parallel-t3d",
          "locator": "pp.1-3–1-4"
        },
        "memory": {
          "value": "Per-PE DRAM; globally accessible shared address space",
          "source": "parallel-t3d",
          "locator": "pp.1-3,3-15"
        },
        "control": {
          "value": "Independent PEs with shared node support",
          "source": "parallel-t3d",
          "locator": "p.1-4"
        },
        "io": {
          "value": "Torus gateways connect a Cray IOS-E host",
          "source": "parallel-t3d",
          "locator": "pp.1-1,1-6"
        },
        "software": {
          "value": "Applications compile on the host and execute on T3D",
          "source": "parallel-t3d",
          "locator": "p.1-1"
        },
        "workload": {
          "value": "Data parallel, work sharing, and message passing",
          "source": "parallel-t3d",
          "locator": "p.1-1"
        }
      },
      "diagram": {
        "title": "Two PEs share torus access and bulk transfer",
        "scope": "Support circuits are explicit. Torus is aggregated, with gateway/host boundary preserved.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cpu0",
            "label": "PE0 microprocessor",
            "subtitle": "PRIVATE EXECUTION",
            "text": "64-bit RISC computation.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-t3d",
            "locator": "p.1-3",
            "control": false
          },
          {
            "id": "mem0",
            "label": "PE0 local DRAM",
            "subtitle": "GLOBAL ADDRESSABLE",
            "text": "Private physical placement.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-t3d",
            "locator": "p.3-15",
            "control": false
          },
          {
            "id": "cpu1",
            "label": "PE1 microprocessor",
            "subtitle": "PRIVATE EXECUTION",
            "text": "Independent partner.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-t3d",
            "locator": "p.1-4",
            "control": false
          },
          {
            "id": "mem1",
            "label": "PE1 local DRAM",
            "subtitle": "GLOBAL ADDRESSABLE",
            "text": "Private physical placement.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-t3d",
            "locator": "p.3-15",
            "control": false
          },
          {
            "id": "support",
            "label": "PE support circuits",
            "subtitle": "ADDRESS /CONTROL",
            "text": "Extend processor interface.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-t3d",
            "locator": "p.1-3",
            "control": true
          },
          {
            "id": "blt",
            "label": "Block-transfer engine",
            "subtitle": "SHARED DMA",
            "text": "Asynchronous redistribution.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-t3d",
            "locator": "p.1-4",
            "control": false
          },
          {
            "id": "ni",
            "label": "Node network interface",
            "subtitle": "SHARED BY TWO PEs",
            "text": "Formats and steers transfers.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-t3d",
            "locator": "p.1-4",
            "control": false
          },
          {
            "id": "router",
            "label": "Network router",
            "subtitle": "±X /±Y /±Z",
            "text": "Node communication links.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-t3d",
            "locator": "Fig.1-4",
            "control": false
          },
          {
            "id": "torus",
            "label": "Other torus nodes",
            "subtitle": "3D INTERCONNECT",
            "text": "Remote PEs and memories.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-t3d",
            "locator": "pp.1-5,2-1",
            "control": false
          },
          {
            "id": "gateway",
            "label": "I/O gateway /host",
            "subtitle": "IOS-E CONNECTION",
            "text": "Data and control to host.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-t3d",
            "locator": "pp.1-1,1-6",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu0",
            "to": "mem0",
            "type": "data",
            "source": "parallel-t3d",
            "locator": "p.1-3",
            "label": ""
          },
          {
            "from": "mem0",
            "to": "cpu0",
            "type": "data",
            "source": "parallel-t3d",
            "locator": "p.1-3",
            "label": ""
          },
          {
            "from": "cpu1",
            "to": "mem1",
            "type": "data",
            "source": "parallel-t3d",
            "locator": "p.1-3",
            "label": ""
          },
          {
            "from": "cpu0",
            "to": "support",
            "type": "association",
            "source": "parallel-t3d",
            "locator": "p.1-3",
            "label": ""
          },
          {
            "from": "cpu0",
            "to": "ni",
            "type": "data",
            "source": "parallel-t3d",
            "locator": "Fig.1-3",
            "label": ""
          },
          {
            "from": "cpu1",
            "to": "ni",
            "type": "data",
            "source": "parallel-t3d",
            "locator": "Fig.1-3",
            "label": ""
          },
          {
            "from": "cpu0",
            "to": "blt",
            "type": "control",
            "source": "parallel-t3d",
            "locator": "Fig.1-3",
            "label": ""
          },
          {
            "from": "cpu1",
            "to": "blt",
            "type": "control",
            "source": "parallel-t3d",
            "locator": "Fig.1-3",
            "label": ""
          },
          {
            "from": "blt",
            "to": "ni",
            "type": "control",
            "source": "parallel-t3d",
            "locator": "Fig.1-3",
            "label": ""
          },
          {
            "from": "ni",
            "to": "router",
            "type": "data",
            "source": "parallel-t3d",
            "locator": "Fig.1-4",
            "label": ""
          },
          {
            "from": "router",
            "to": "torus",
            "type": "data",
            "source": "parallel-t3d",
            "locator": "Fig.1-4",
            "label": ""
          },
          {
            "from": "torus",
            "to": "router",
            "type": "data",
            "source": "parallel-t3d",
            "locator": "Fig.1-4",
            "label": ""
          },
          {
            "from": "torus",
            "to": "gateway",
            "type": "data",
            "source": "parallel-t3d",
            "locator": "Fig.1-1",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Cray T3D"
    },
    {
      "id": "queue-066",
      "name": "Cray T3E — initial21164 organization",
      "organization": "Cray Research",
      "year": 1996,
      "yearLabel": "1996 designer publications",
      "kind": "Commercial reference architecture",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "distributed",
        "numa",
        "risc"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-t3e-scott",
        "parallel-t3e-system"
      ],
      "summary": "External E-registers pipeline remote memory operations while local references use cache and stream-buffer paths.",
      "config": "Initial Alpha21164 T3E architecture; node count is parameterized rather than assigned to a site.",
      "gaps": [
        "Remote global addressing differs from a general coherent NUMA load/store machine.",
        "The graph does not assign the paper’s maximum processor count to every T3E."
      ],
      "insight": "Why use explicit E-registers instead of caching remote data?",
      "fields": {
        "state": {
          "value": "64-bit Alpha data; memory-mapped E-registers",
          "source": "parallel-t3e-scott",
          "locator": "§§3–4"
        },
        "compute": {
          "value": "One Alpha21164 per network node",
          "source": "parallel-t3e-system",
          "locator": "p.384"
        },
        "memory": {
          "value": "Distributed global memory; local-only caching",
          "source": "parallel-t3e-scott",
          "locator": "§3"
        },
        "control": {
          "value": "E-register operations, atomics, virtual barriers",
          "source": "parallel-t3e-scott",
          "locator": "§§4–7"
        },
        "io": {
          "value": "GigaRing attachment",
          "source": "parallel-t3e-system",
          "locator": "pp.384–385"
        },
        "software": {
          "value": "Self-hosted UNICOS/mk; Fortran/C/C++ and messaging",
          "source": "parallel-t3e-system",
          "locator": "pp.385–386"
        },
        "workload": {
          "value": "Scalable scientific MIMD applications",
          "source": "parallel-t3e-system",
          "locator": "pp.383–384"
        }
      },
      "diagram": {
        "title": "Cached local access and explicit global communication",
        "scope": "Selected source-node and destination-node resources; an adaptive3D torus carries global requests.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cpu",
            "label": "Alpha21164",
            "subtitle": "ONE PER NODE",
            "text": "Executes application.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-t3e-system",
            "locator": "p.384",
            "control": false
          },
          {
            "id": "cache",
            "label": "On-chip caches",
            "subtitle": "LOCAL DATA ONLY",
            "text": "Filtered remote probes.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-t3e-scott",
            "locator": "§3",
            "control": false
          },
          {
            "id": "stream",
            "label": "Stream buffers",
            "subtitle": "LOCAL PREFETCH",
            "text": "Detects reference streams.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-t3e-system",
            "locator": "p.384",
            "control": false
          },
          {
            "id": "local",
            "label": "Local memory",
            "subtitle": "GLOBAL ADDRESSABLE",
            "text": "Also serves remote traffic.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-t3e-scott",
            "locator": "§3",
            "control": false
          },
          {
            "id": "eregs",
            "label": "External E-registers",
            "subtitle": "EXPLICIT GLOBAL OPS",
            "text": "Operands and returned values.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-t3e-scott",
            "locator": "§4",
            "control": false
          },
          {
            "id": "backmap",
            "label": "Cache backmap",
            "subtitle": "COHERENCE FILTER",
            "text": "Probes dirty/invalidate state.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-t3e-scott",
            "locator": "§3",
            "control": true
          },
          {
            "id": "torus",
            "label": "Adaptive3D torus",
            "subtitle": "ONE PE /NODE",
            "text": "Remote request/reply network.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-t3e-system",
            "locator": "p.384",
            "control": false
          },
          {
            "id": "remote",
            "label": "Remote memory/interface",
            "subtitle": "GLOBAL TRANSLATION",
            "text": "Target-side access and atomics.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-t3e-scott",
            "locator": "§§4–5",
            "control": false
          },
          {
            "id": "barrier",
            "label": "Virtual barrier trees",
            "subtitle": "EMBEDDED IN TORUS",
            "text": "Barrier/eureka operations.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-t3e-scott",
            "locator": "§7",
            "control": true
          },
          {
            "id": "io",
            "label": "GigaRing I/O",
            "subtitle": "SELF-HOSTED SYSTEM",
            "text": "Scalable external attachment.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-t3e-system",
            "locator": "p.385",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu",
            "to": "cache",
            "type": "data",
            "source": "parallel-t3e-scott",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "cache",
            "to": "stream",
            "type": "data",
            "source": "parallel-t3e-scott",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "stream",
            "to": "local",
            "type": "data",
            "source": "parallel-t3e-scott",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "eregs",
            "type": "data",
            "source": "parallel-t3e-scott",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "eregs",
            "to": "cpu",
            "type": "data",
            "source": "parallel-t3e-scott",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "eregs",
            "to": "torus",
            "type": "data",
            "source": "parallel-t3e-scott",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "torus",
            "to": "remote",
            "type": "data",
            "source": "parallel-t3e-scott",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "remote",
            "to": "torus",
            "type": "data",
            "source": "parallel-t3e-scott",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "torus",
            "to": "local",
            "type": "data",
            "source": "parallel-t3e-scott",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "torus",
            "to": "backmap",
            "type": "control",
            "source": "parallel-t3e-scott",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "backmap",
            "to": "cache",
            "type": "control",
            "source": "parallel-t3e-scott",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "barrier",
            "to": "torus",
            "type": "association",
            "source": "parallel-t3e-scott",
            "locator": "§7",
            "label": ""
          },
          {
            "from": "io",
            "to": "torus",
            "type": "association",
            "source": "parallel-t3e-system",
            "locator": "pp.384–385",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Cray T3E"
    },
    {
      "id": "queue-067",
      "name": "NEC SX-2 — Fuchu benchmark configuration",
      "organization": "NEC",
      "year": 1987,
      "yearLabel": "1987 report of1985–1986 measurements",
      "kind": "Measured commercial system",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "vector",
        "heterogeneous",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-sx2-lanl"
      ],
      "summary": "A control processor handles system work while a scalar/vector arithmetic processor executes compute-bound programs.",
      "config": "NEC Fuchu SX-2 configuration characterized by LA-UR-87-227; later SX-2A excluded.",
      "gaps": [
        "Memory bank count/capacity for this exact test is not established reliably.",
        "No I/O throughput was measured."
      ],
      "insight": "Which tasks belong to the control processor?",
      "fields": {
        "state": {
          "value": "Vector register-to-register arithmetic",
          "source": "parallel-sx2-lanl",
          "locator": "§2"
        },
        "compute": {
          "value": "Four vector functional-unit sets",
          "source": "parallel-sx2-lanl",
          "locator": "§2"
        },
        "memory": {
          "value": "40×256-element vector capacity; scalar64KB cache",
          "source": "parallel-sx2-lanl",
          "locator": "§2"
        },
        "control": {
          "value": "Separate control and arithmetic processors",
          "source": "parallel-sx2-lanl",
          "locator": "§2"
        },
        "io": {
          "value": "Control processor handles terminals and I/O",
          "source": "parallel-sx2-lanl",
          "locator": "§2"
        },
        "software": {
          "value": "Fortran with vectorizing compiler directives",
          "source": "parallel-sx2-lanl",
          "locator": "§3"
        },
        "workload": {
          "value": "Los Alamos scientific benchmarks and HYDRO",
          "source": "parallel-sx2-lanl",
          "locator": "§3"
        }
      },
      "diagram": {
        "title": "System control and four-way vector arithmetic",
        "scope": "Logical decomposition of the reported SX-2; memory ports share aggregate bandwidth.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cp",
            "label": "Control processor",
            "subtitle": "SYSTEM /UTILITIES",
            "text": "Handles program development and terminal work.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "control": false
          },
          {
            "id": "io",
            "label": "Terminals /I/O",
            "subtitle": "CONTROL-PROCESSOR WORK",
            "text": "Connects the system to external activity.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "control": false
          },
          {
            "id": "scalar",
            "label": "AP scalar module",
            "subtitle": "128 REGISTERS",
            "text": "Executes scalar portions of user programs.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "control": false
          },
          {
            "id": "cache",
            "label": "Scalar cache",
            "subtitle": "64KB",
            "text": "Buffers scalar memory accesses.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "control": false
          },
          {
            "id": "memory",
            "label": "Main memory",
            "subtitle": "BANKED STORAGE",
            "text": "Supplies scalar and vector paths.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "control": false
          },
          {
            "id": "paths",
            "label": "Vector load/store paths",
            "subtitle": "8 LOAD /4 STORE",
            "text": "Shares a limited aggregate memory interface.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "control": false
          },
          {
            "id": "vr",
            "label": "Vector register capacity",
            "subtitle": "40×256 ELEMENTS",
            "text": "Buffers operands for vector execution.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "control": false
          },
          {
            "id": "pipes",
            "label": "Four functional-unit sets",
            "subtitle": "INTERLEAVED ELEMENTS",
            "text": "Each set computes every fourth element.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cp",
            "to": "io",
            "type": "control",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "io",
            "to": "cp",
            "type": "data",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "cp",
            "to": "scalar",
            "type": "association",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": "system/user work split"
          },
          {
            "from": "memory",
            "to": "cache",
            "type": "data",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "cache",
            "to": "scalar",
            "type": "data",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "scalar",
            "to": "cache",
            "type": "data",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "cache",
            "to": "memory",
            "type": "data",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "memory",
            "to": "paths",
            "type": "data",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "paths",
            "to": "memory",
            "type": "data",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "paths",
            "to": "vr",
            "type": "data",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "vr",
            "to": "paths",
            "type": "data",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "vr",
            "to": "pipes",
            "type": "data",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "pipes",
            "to": "vr",
            "type": "data",
            "source": "parallel-sx2-lanl",
            "locator": "§2",
            "label": ""
          }
        ]
      },
      "originalCandidate": "NEC SX-2"
    },
    {
      "id": "queue-068",
      "name": "NEC SX-Aurora TSUBASA —Type10AE engine",
      "organization": "NEC",
      "year": null,
      "yearLabel": "First-generation Type10AE specification",
      "kind": "Commercial accelerator configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "vector",
        "heterogeneous",
        "smp",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-aurora-arch",
        "parallel-aurora-card",
        "parallel-aurora-soft"
      ],
      "summary": "A PCIe vector engine combines eight vector cores, shared last-level cache, and six HBM2 stacks under a Linux host.",
      "config": "One Type10AE Vector Engine with eight cores and48GB; later10-core/16-core cards are excluded.",
      "gaps": [
        "The cited pages are undated living specifications; the timeline does not infer a launch date.",
        "The64-register diagram describes per-core state, not a shared register file."
      ],
      "insight": "How is a vector application divided between the x86 host and engine?",
      "fields": {
        "state": {
          "value": "64 vector registers/core;256 eight-byte entries/register",
          "source": "parallel-aurora-arch",
          "locator": "Vector processing"
        },
        "compute": {
          "value": "Eight vector cores; three FMA units/core",
          "source": "parallel-aurora-arch",
          "locator": "Vector core /Vector processing"
        },
        "memory": {
          "value": "16MB shared cache;48GB across six HBM2 stacks",
          "source": "parallel-aurora-card",
          "locator": "Type10AE table and package paragraph"
        },
        "control": {
          "value": "Host OS services and engine application execution",
          "source": "parallel-aurora-soft",
          "locator": "Vector Host and Vector Engine"
        },
        "io": {
          "value": "PCIe host attachment; inter-engine communication",
          "source": "parallel-aurora-arch",
          "locator": "Communication"
        },
        "software": {
          "value": "Linux; vectorizing Fortran/C++; OpenMP and MPI",
          "source": "parallel-aurora-soft",
          "locator": "Software environment"
        },
        "workload": {
          "value": "Vectorized scientific applications",
          "source": "parallel-aurora-soft",
          "locator": "Compilers"
        }
      },
      "diagram": {
        "title": "Host services, vector datapath, and HBM locality",
        "scope": "One vector core expanded; seven peers share the last-level cache and HBM resources.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "host",
            "label": "x86 Vector Host",
            "subtitle": "LINUX SERVICES",
            "text": "System calls and scheduling.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-soft",
            "locator": "Host/engine software",
            "control": true
          },
          {
            "id": "interface",
            "label": "Kernel interface /PCIe",
            "subtitle": "HOST–ENGINE BOUNDARY",
            "text": "OS and data communication.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-soft",
            "locator": "Linux kernel module",
            "control": false
          },
          {
            "id": "core",
            "label": "Vector core0",
            "subtitle": "APPLICATION EXECUTION",
            "text": "Private scalar/vector control.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-arch",
            "locator": "Vector core",
            "control": true
          },
          {
            "id": "vr",
            "label": "Vector registers",
            "subtitle": "64 ×256 ENTRIES",
            "text": "Eight-byte vector elements.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-arch",
            "locator": "Vector processing",
            "control": false
          },
          {
            "id": "cross",
            "label": "Register crossbar",
            "subtitle": "NONBLOCKING PATHS",
            "text": "Connects registers and units.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-arch",
            "locator": "Vector processing",
            "control": false
          },
          {
            "id": "units",
            "label": "Vector functional units",
            "subtitle": "3 FMA +DIV/SQRT",
            "text": "Arithmetic and logical units.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-arch",
            "locator": "Vector processing",
            "control": false
          },
          {
            "id": "peers",
            "label": "Vector cores1–7",
            "subtitle": "SAME CORE DESIGN",
            "text": "Private vector computation.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-card",
            "locator": "Type10AE table",
            "control": false
          },
          {
            "id": "llc",
            "label": "Shared LLC",
            "subtitle": "16MB WRITE-BACK",
            "text": "128-byte cache lines.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-arch",
            "locator": "Cache",
            "control": false
          },
          {
            "id": "hbm",
            "label": "Six HBM2 stacks",
            "subtitle": "48GB ON PACKAGE",
            "text": "Common engine memory.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-card",
            "locator": "First-generation package /Type10AE",
            "control": false
          },
          {
            "id": "comm",
            "label": "Other engines /network",
            "subtitle": "PLATFORM-DEPENDENT",
            "text": "Engine communication.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-arch",
            "locator": "Communication",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "interface",
            "type": "control",
            "source": "parallel-aurora-soft",
            "locator": "Host/engine software",
            "label": ""
          },
          {
            "from": "interface",
            "to": "core",
            "type": "data",
            "source": "parallel-aurora-arch",
            "locator": "Communication",
            "label": ""
          },
          {
            "from": "core",
            "to": "vr",
            "type": "control",
            "source": "parallel-aurora-arch",
            "locator": "Vector core",
            "label": ""
          },
          {
            "from": "vr",
            "to": "cross",
            "type": "data",
            "source": "parallel-aurora-arch",
            "locator": "Vector processing",
            "label": ""
          },
          {
            "from": "cross",
            "to": "units",
            "type": "data",
            "source": "parallel-aurora-arch",
            "locator": "Vector processing",
            "label": ""
          },
          {
            "from": "units",
            "to": "cross",
            "type": "data",
            "source": "parallel-aurora-arch",
            "locator": "Vector processing",
            "label": ""
          },
          {
            "from": "cross",
            "to": "vr",
            "type": "data",
            "source": "parallel-aurora-arch",
            "locator": "Vector processing",
            "label": ""
          },
          {
            "from": "core",
            "to": "llc",
            "type": "data",
            "source": "parallel-aurora-arch",
            "locator": "Cache",
            "label": ""
          },
          {
            "from": "peers",
            "to": "llc",
            "type": "data",
            "source": "parallel-aurora-arch",
            "locator": "Cache",
            "label": ""
          },
          {
            "from": "llc",
            "to": "hbm",
            "type": "data",
            "source": "parallel-aurora-arch",
            "locator": "Memory",
            "label": ""
          },
          {
            "from": "hbm",
            "to": "llc",
            "type": "data",
            "source": "parallel-aurora-arch",
            "locator": "Memory",
            "label": ""
          },
          {
            "from": "interface",
            "to": "comm",
            "type": "data",
            "source": "parallel-aurora-arch",
            "locator": "Communication",
            "label": ""
          }
        ]
      },
      "originalCandidate": "NEC SX-Aurora TSUBASA"
    },
    {
      "id": "queue-069",
      "name": "Fujitsu VP-200 — Numazu64MB system",
      "organization": "Fujitsu",
      "year": 1985,
      "yearLabel": "October1985 report;1984 installed-system corroboration",
      "kind": "Measured commercial vector computer",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "vector",
        "register-memory",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-vp200-anl",
        "parallel-vp200-miura"
      ],
      "summary": "Concurrent scalar/vector units use dynamically partitioned vector storage and two bidirectional memory pipelines.",
      "config": "Numazu VP-200 with64MB; timing organization from ANL-85-19.",
      "gaps": [
        "Some report tables describe Amdahl maximum offerings rather than this installed capacity.",
        "No integrated extended store is assumed."
      ],
      "insight": "How does register length trade against register count?",
      "fields": {
        "state": {
          "value": "IBM370-compatible scalar data/instructions;64-bit vectors",
          "source": "parallel-vp200-anl",
          "locator": "§2.2"
        },
        "compute": {
          "value": "Independent scalar and vector units",
          "source": "parallel-vp200-anl",
          "locator": "§2.2"
        },
        "memory": {
          "value": "8192-word configurable vector store;64KB scalar cache",
          "source": "parallel-vp200-anl",
          "locator": "§§2.2,3.4.3"
        },
        "control": {
          "value": "Overlapped pipelines; load/store chaining",
          "source": "parallel-vp200-anl",
          "locator": "§3.4.4"
        },
        "io": {
          "value": "IBM-compatible channels and front-end links",
          "source": "parallel-vp200-anl",
          "locator": "§2.2"
        },
        "software": {
          "value": "FORTRAN compiler, interactive vectorizer and debugging aids",
          "source": "parallel-vp200-miura",
          "locator": "p.319 Q&A"
        },
        "workload": {
          "value": "FFT, matrix algebra and molecular dynamics",
          "source": "parallel-vp200-miura",
          "locator": "pp.317–318"
        }
      },
      "diagram": {
        "title": "Configurable vector storage and two memory pipelines",
        "scope": "Numazu system roles; functional pipes aggregated by arithmetic category.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "front",
            "label": "M-series front end",
            "subtitle": "TOOLS /SYSTEM WORK",
            "text": "Runs development and supervisory tasks.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-vp200-miura",
            "locator": "Table3; p.319",
            "control": false
          },
          {
            "id": "chan",
            "label": "Compatible channels",
            "subtitle": "FRONT END /DEVICES",
            "text": "Connects mainframe-compatible peripherals.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-vp200-anl",
            "locator": "§2.2",
            "control": false
          },
          {
            "id": "mem",
            "label": "Main storage",
            "subtitle": "64MB TESTED",
            "text": "Supplies independent scalar/vector accesses.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-vp200-anl",
            "locator": "§3.4.1",
            "control": false
          },
          {
            "id": "cache",
            "label": "Scalar buffer storage",
            "subtitle": "64KB",
            "text": "Buffers scalar operands and instructions.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-vp200-anl",
            "locator": "§3.4.3",
            "control": false
          },
          {
            "id": "scalar",
            "label": "Scalar execution unit",
            "subtitle": "GPR /FP REGISTERS",
            "text": "Runs370-compatible scalar instructions.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-vp200-anl",
            "locator": "§2.2, Fig.2",
            "control": false
          },
          {
            "id": "ls",
            "label": "Two load/store pipes",
            "subtitle": "BIDIRECTIONAL",
            "text": "Move vector operands and results.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-vp200-anl",
            "locator": "§3.4.4",
            "control": false
          },
          {
            "id": "vr",
            "label": "Configurable vector store",
            "subtitle": "8192 WORDS",
            "text": "Partitions capacity into variable register lengths.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-vp200-anl",
            "locator": "§2.2",
            "control": false
          },
          {
            "id": "mask",
            "label": "Mask registers /unit",
            "subtitle": "CONDITIONAL VECTORS",
            "text": "Controls selected vector elements.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-vp200-anl",
            "locator": "Fig.2",
            "control": false
          },
          {
            "id": "fp",
            "label": "Add/logical /multiply /divide",
            "subtitle": "VECTOR PIPELINES",
            "text": "Operate concurrently on register vectors.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-vp200-anl",
            "locator": "Fig.2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "front",
            "to": "chan",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "chan",
            "to": "front",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "chan",
            "to": "mem",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "mem",
            "to": "cache",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "§3.4.3",
            "label": ""
          },
          {
            "from": "cache",
            "to": "scalar",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "scalar",
            "to": "cache",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "cache",
            "to": "mem",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "mem",
            "to": "ls",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "§3.4.4",
            "label": ""
          },
          {
            "from": "ls",
            "to": "mem",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "§3.4.4",
            "label": ""
          },
          {
            "from": "ls",
            "to": "vr",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "vr",
            "to": "ls",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "vr",
            "to": "fp",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "fp",
            "to": "vr",
            "type": "data",
            "source": "parallel-vp200-anl",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "mask",
            "to": "vr",
            "type": "control",
            "source": "parallel-vp200-anl",
            "locator": "Fig.2",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Fujitsu VP200"
    },
    {
      "id": "queue-070",
      "name": "Hitachi S-810/20 — 1983 reference architecture",
      "organization": "Hitachi",
      "year": 1983,
      "yearLabel": "August1983 designer paper",
      "kind": "Commercial reference design before shipment",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "vector",
        "register-memory",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-hitachi-s810"
      ],
      "summary": "Scalar EXVP dispatch launches groups of vector instructions; separate extended storage substitutes for temporary disk datasets.",
      "config": "Model20 reference organization; paper specifies capacities as options, not one installed machine.",
      "gaps": [
        "Fig.8 is Model10; its exact pipe counts are not attributed to Model20.",
        "Maximum memory capacities are optional limits, not installed values."
      ],
      "insight": "What does EXVP hand over to the vector unit?",
      "fields": {
        "state": {
          "value": "32/64-bit floating-point and32-bit integer vectors",
          "source": "parallel-hitachi-s810",
          "locator": "Fig.2; Table1"
        },
        "compute": {
          "value": "Concurrent scalar and vector pipelines",
          "source": "parallel-hitachi-s810",
          "locator": "§5.1"
        },
        "memory": {
          "value": "32×256-word vector registers;256KB scalar buffer",
          "source": "parallel-hitachi-s810",
          "locator": "§5.1"
        },
        "control": {
          "value": "Scalar setup and EXVP vector-sequence launch",
          "source": "parallel-hitachi-s810",
          "locator": "§4.1, Fig.6"
        },
        "io": {
          "value": "Channels plus separate extended-store transfers",
          "source": "parallel-hitachi-s810",
          "locator": "§§3.2,4.2"
        },
        "software": {
          "value": "VOS3/HAP,FORTRAN,VECTIZER,MATRIX/HAP",
          "source": "parallel-hitachi-s810",
          "locator": "§6"
        },
        "workload": {
          "value": "Large scientific and engineering calculations",
          "source": "parallel-hitachi-s810",
          "locator": "§1"
        }
      },
      "diagram": {
        "title": "EXVP launch, vector paths, and extended datasets",
        "scope": "Model20 logical roles; optional storage represented without installed capacity.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "scalar",
            "label": "Scalar processing unit",
            "subtitle": "M-SERIES COMPATIBILITY",
            "text": "Prepares vector addresses and element counts.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-hitachi-s810",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "buf",
            "label": "Scalar buffer storage",
            "subtitle": "256KB /MODEL20",
            "text": "Supplies scalar code and operands.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-hitachi-s810",
            "locator": "§5.1",
            "control": false
          },
          {
            "id": "ctrl",
            "label": "Vector sequence control",
            "subtitle": "EXVP LAUNCH",
            "text": "Executes a prepared vector instruction group.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-hitachi-s810",
            "locator": "Fig.6",
            "control": true
          },
          {
            "id": "addr",
            "label": "Vector address /mask state",
            "subtitle": "ADDRESS /SELECTED ELEMENTS",
            "text": "Controls addressing and conditional vector work.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-hitachi-s810",
            "locator": "Figs.2,8",
            "control": false
          },
          {
            "id": "main",
            "label": "Main storage",
            "subtitle": "CONFIGURABLE CAPACITY",
            "text": "Feeds vector paths and scalar buffer.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-hitachi-s810",
            "locator": "Fig.3",
            "control": false
          },
          {
            "id": "ls",
            "label": "Vector load/store paths",
            "subtitle": "PARALLEL TRANSFERS",
            "text": "Transfers vector elements independently.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-hitachi-s810",
            "locator": "§5.2",
            "control": false
          },
          {
            "id": "vr",
            "label": "Vector registers",
            "subtitle": "32×256 WORDS",
            "text": "Buffers operands/results for pipelines.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-hitachi-s810",
            "locator": "§5.1",
            "control": false
          },
          {
            "id": "fu",
            "label": "Vector arithmetic /mask units",
            "subtitle": "MULTIPLE PIPELINES",
            "text": "Runs independent vector operations concurrently.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-hitachi-s810",
            "locator": "§5.2",
            "control": false
          },
          {
            "id": "extended",
            "label": "Extended semiconductor store",
            "subtitle": "TEMPORARY DATASETS",
            "text": "Moves blocks through special transfer instructions.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-hitachi-s810",
            "locator": "§4.2",
            "control": false
          },
          {
            "id": "io",
            "label": "Channels /disk /service",
            "subtitle": "EXTERNAL SYSTEM WORK",
            "text": "Provides peripherals and diagnostic support.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-hitachi-s810",
            "locator": "Fig.3",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "buf",
            "to": "scalar",
            "type": "data",
            "source": "parallel-hitachi-s810",
            "locator": "§5.1",
            "label": ""
          },
          {
            "from": "scalar",
            "to": "ctrl",
            "type": "control",
            "source": "parallel-hitachi-s810",
            "locator": "Fig.6",
            "label": ""
          },
          {
            "from": "scalar",
            "to": "addr",
            "type": "control",
            "source": "parallel-hitachi-s810",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "ctrl",
            "to": "fu",
            "type": "control",
            "source": "parallel-hitachi-s810",
            "locator": "Fig.6",
            "label": ""
          },
          {
            "from": "addr",
            "to": "ls",
            "type": "control",
            "source": "parallel-hitachi-s810",
            "locator": "Fig.8",
            "label": ""
          },
          {
            "from": "main",
            "to": "buf",
            "type": "data",
            "source": "parallel-hitachi-s810",
            "locator": "Fig.8",
            "label": ""
          },
          {
            "from": "buf",
            "to": "main",
            "type": "data",
            "source": "parallel-hitachi-s810",
            "locator": "Fig.8",
            "label": ""
          },
          {
            "from": "main",
            "to": "ls",
            "type": "data",
            "source": "parallel-hitachi-s810",
            "locator": "§5.2",
            "label": ""
          },
          {
            "from": "ls",
            "to": "main",
            "type": "data",
            "source": "parallel-hitachi-s810",
            "locator": "§5.2",
            "label": ""
          },
          {
            "from": "ls",
            "to": "vr",
            "type": "data",
            "source": "parallel-hitachi-s810",
            "locator": "Fig.8",
            "label": ""
          },
          {
            "from": "vr",
            "to": "ls",
            "type": "data",
            "source": "parallel-hitachi-s810",
            "locator": "Fig.8",
            "label": ""
          },
          {
            "from": "vr",
            "to": "fu",
            "type": "data",
            "source": "parallel-hitachi-s810",
            "locator": "Fig.8",
            "label": ""
          },
          {
            "from": "fu",
            "to": "vr",
            "type": "data",
            "source": "parallel-hitachi-s810",
            "locator": "Fig.8",
            "label": ""
          },
          {
            "from": "main",
            "to": "extended",
            "type": "data",
            "source": "parallel-hitachi-s810",
            "locator": "§4.2",
            "label": ""
          },
          {
            "from": "extended",
            "to": "main",
            "type": "data",
            "source": "parallel-hitachi-s810",
            "locator": "§4.2",
            "label": ""
          },
          {
            "from": "io",
            "to": "main",
            "type": "data",
            "source": "parallel-hitachi-s810",
            "locator": "Fig.3",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Hitachi S-810"
    },
    {
      "id": "queue-071",
      "name": "Earth Simulator —ES1",
      "organization": "JAMSTEC /NEC",
      "year": 2002,
      "yearLabel": "ES1 installation completed February2002",
      "kind": "Built supercomputer installation",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "vector",
        "smp",
        "distributed",
        "mimd",
        "superscalar"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-es1-system",
        "parallel-es1-ap",
        "parallel-es1-pn",
        "parallel-es1-network",
        "parallel-es1-software"
      ],
      "summary": "Shared-memory vector nodes connect through a single-stage crossbar, with hardware support for inter-node array movement.",
      "config": "Original640-node ES1 installation; ES2 and subsequent Earth Simulators are distinct.",
      "gaps": [
        "Vector pipeline sets are aggregated by function; this is not a cycle-level AP model.",
        "OS and file-system internals require their dedicated manuals."
      ],
      "insight": "Where does vector locality end and inter-node communication begin?",
      "fields": {
        "state": {
          "value": "Scalar state and72 vector registers/AP",
          "source": "parallel-es1-ap",
          "locator": "Vector Unit"
        },
        "compute": {
          "value": "640 nodes ×8 arithmetic processors",
          "source": "parallel-es1-system",
          "locator": "System"
        },
        "memory": {
          "value": "16GB shared/node;2048 banks",
          "source": "parallel-es1-pn",
          "locator": "Processor Node"
        },
        "control": {
          "value": "Independent scalar units and vector pipelines",
          "source": "parallel-es1-ap",
          "locator": "Arithmetic Processor"
        },
        "io": {
          "value": "Per-node RCU and I/O processor",
          "source": "parallel-es1-system",
          "locator": "System"
        },
        "software": {
          "value": "MPI and High Performance Fortran interfaces",
          "source": "parallel-es1-software",
          "locator": "Programming Environment"
        },
        "workload": {
          "value": "Earth-system numerical simulation",
          "source": "parallel-es1-system",
          "locator": "System overview"
        }
      },
      "diagram": {
        "title": "Vector APs inside a shared-memory node, crossbar outside",
        "scope": "One AP and one node expanded. Seven sibling APs and639 remote nodes are aggregated.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "su",
            "label": "AP0 scalar unit",
            "subtitle": "4-WAY SUPERSCALAR",
            "text": "Branch and scalar execution.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-es1-ap",
            "locator": "Scalar Unit",
            "control": true
          },
          {
            "id": "vreg",
            "label": "AP0 vector registers",
            "subtitle": "72 ×256 ENTRIES",
            "text": "Vector operands/results.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-es1-ap",
            "locator": "Vector Unit",
            "control": false
          },
          {
            "id": "vp",
            "label": "AP0 vector pipelines",
            "subtitle": "8 SETS ×6 TYPES",
            "text": "Add,multiply,divide,logic,etc.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-es1-ap",
            "locator": "Vector Unit",
            "control": false
          },
          {
            "id": "mc",
            "label": "AP0 memory control",
            "subtitle": "LOAD /STORE ACCESS",
            "text": "Main-memory interface.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-es1-ap",
            "locator": "Arithmetic Processor",
            "control": false
          },
          {
            "id": "siblings",
            "label": "Seven sibling APs",
            "subtitle": "SHARED-MEMORY NODE",
            "text": "Same AP design.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-es1-system",
            "locator": "System",
            "control": false
          },
          {
            "id": "mem",
            "label": "Node shared memory",
            "subtitle": "16GB /2048 BANKS",
            "text": "Interleaved main storage.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-es1-pn",
            "locator": "Processor Node",
            "control": false
          },
          {
            "id": "rcu",
            "label": "Remote access control",
            "subtitle": "ARRAY TRANSFERS",
            "text": "Inter-node communication.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-es1-network",
            "locator": "Interconnection Network",
            "control": false
          },
          {
            "id": "crossbar",
            "label": "640×640 crossbar",
            "subtitle": "SINGLE STAGE",
            "text": "Connects processing nodes.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-es1-system",
            "locator": "System",
            "control": false
          },
          {
            "id": "remote",
            "label": "Other639 nodes",
            "subtitle": "SAME PN ORGANIZATION",
            "text": "Remote node endpoints.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-es1-system",
            "locator": "System",
            "control": false
          },
          {
            "id": "iop",
            "label": "Node I/O processor",
            "subtitle": "EXTERNAL I/O",
            "text": "PN I/O resource.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-es1-system",
            "locator": "System",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "su",
            "to": "vp",
            "type": "control",
            "source": "parallel-es1-ap",
            "locator": "Arithmetic Processor",
            "label": ""
          },
          {
            "from": "vreg",
            "to": "vp",
            "type": "data",
            "source": "parallel-es1-ap",
            "locator": "Vector Unit",
            "label": ""
          },
          {
            "from": "vp",
            "to": "vreg",
            "type": "data",
            "source": "parallel-es1-ap",
            "locator": "Vector Unit",
            "label": ""
          },
          {
            "from": "vp",
            "to": "mc",
            "type": "data",
            "source": "parallel-es1-ap",
            "locator": "Vector Unit",
            "label": ""
          },
          {
            "from": "mc",
            "to": "mem",
            "type": "data",
            "source": "parallel-es1-ap",
            "locator": "Arithmetic Processor",
            "label": ""
          },
          {
            "from": "mem",
            "to": "mc",
            "type": "data",
            "source": "parallel-es1-ap",
            "locator": "Arithmetic Processor",
            "label": ""
          },
          {
            "from": "siblings",
            "to": "mem",
            "type": "data",
            "source": "parallel-es1-system",
            "locator": "System",
            "label": ""
          },
          {
            "from": "mem",
            "to": "rcu",
            "type": "data",
            "source": "parallel-es1-network",
            "locator": "RCU description",
            "label": ""
          },
          {
            "from": "rcu",
            "to": "mem",
            "type": "data",
            "source": "parallel-es1-network",
            "locator": "RCU description",
            "label": ""
          },
          {
            "from": "rcu",
            "to": "crossbar",
            "type": "data",
            "source": "parallel-es1-network",
            "locator": "Interconnection Network",
            "label": ""
          },
          {
            "from": "crossbar",
            "to": "remote",
            "type": "data",
            "source": "parallel-es1-system",
            "locator": "System",
            "label": ""
          },
          {
            "from": "remote",
            "to": "crossbar",
            "type": "data",
            "source": "parallel-es1-system",
            "locator": "System",
            "label": ""
          },
          {
            "from": "iop",
            "to": "mem",
            "type": "association",
            "source": "parallel-es1-system",
            "locator": "System",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Earth Simulator"
    },
    {
      "id": "queue-072",
      "name": "K computer — full-operation system",
      "organization": "RIKEN /Fujitsu",
      "year": 2012,
      "yearLabel": "Full operation June2012",
      "kind": "Built supercomputer installation",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "simd",
        "distributed",
        "risc",
        "smp"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-k-system",
        "parallel-k-handout"
      ],
      "summary": "Eight-core SPARC nodes communicate through Tofu, while jobs stage files between local and global storage.",
      "config": "RIKEN K computer at full operation; processor-node and two-level-storage organization in the official handout.",
      "gaps": [
        "Job-visible tori are embeddings in the physical6D network.",
        "The graph abstracts rack wiring and does not equate I/O nodes with compute nodes."
      ],
      "insight": "Why distinguish physical6D links, logical job tori, and staged file I/O?",
      "fields": {
        "state": {
          "value": "SPARC scalar and SIMD register state",
          "source": "parallel-k-handout",
          "locator": "p.1, CPU block"
        },
        "compute": {
          "value": "One eight-core SPARC64VIIIfx per compute node",
          "source": "parallel-k-handout",
          "locator": "p.1, node"
        },
        "memory": {
          "value": "16GiB/node; shared6MB L2 per CPU",
          "source": "parallel-k-handout",
          "locator": "p.1"
        },
        "control": {
          "value": "Linux and parallel job management",
          "source": "parallel-k-handout",
          "locator": "pp.1–2"
        },
        "io": {
          "value": "Tofu ICC; I/O nodes; local/global storage",
          "source": "parallel-k-handout",
          "locator": "pp.1–2"
        },
        "software": {
          "value": "Fortran/C/C++; OpenMP3 and MPI2.1-based stack",
          "source": "parallel-k-handout",
          "locator": "p.2"
        },
        "workload": {
          "value": "Large-scale scientific simulation",
          "source": "parallel-k-system",
          "locator": "System overview"
        }
      },
      "diagram": {
        "title": "Compute-node locality, Tofu, and two-level storage",
        "scope": "One node expanded. Storage paths are distinct from the job’s logical communication topology.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cores",
            "label": "Eight SPARC cores",
            "subtitle": "SCALAR +SIMD",
            "text": "Private execution resources.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-k-handout",
            "locator": "p.1",
            "control": false
          },
          {
            "id": "l1",
            "label": "Private L1 caches",
            "subtitle": "32KB I /32KB D",
            "text": "Per-core instruction/data.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-k-handout",
            "locator": "p.1",
            "control": false
          },
          {
            "id": "l2",
            "label": "Shared L2 cache",
            "subtitle": "6MB /CPU",
            "text": "On-chip shared level.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-k-handout",
            "locator": "p.1",
            "control": false
          },
          {
            "id": "mem",
            "label": "Node memory",
            "subtitle": "16GiB",
            "text": "CPU-attached main memory.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-k-handout",
            "locator": "p.1",
            "control": false
          },
          {
            "id": "icc",
            "label": "Tofu ICC",
            "subtitle": "NODE NETWORK INTERFACE",
            "text": "Connects physical6D links.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-k-handout",
            "locator": "p.1",
            "control": false
          },
          {
            "id": "tofu",
            "label": "Tofu mesh/torus",
            "subtitle": "X,Y,Z,a,b,c",
            "text": "Logical job tori embedded.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-k-handout",
            "locator": "p.1",
            "control": false
          },
          {
            "id": "ionode",
            "label": "I/O nodes",
            "subtitle": "PARALLEL FILE ACCESS",
            "text": "Compute/storage boundary.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-k-handout",
            "locator": "p.1",
            "control": false
          },
          {
            "id": "localfs",
            "label": "Local file system",
            "subtitle": "TEMPORARY JOB DATA",
            "text": "High-throughput work area.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-k-handout",
            "locator": "p.2",
            "control": false
          },
          {
            "id": "globalfs",
            "label": "Global file system",
            "subtitle": "PERSISTENT DATA",
            "text": "Automatic stage-in/out.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-k-handout",
            "locator": "p.2",
            "control": false
          },
          {
            "id": "front",
            "label": "Front ends /job management",
            "subtitle": "SUBMIT /STAGE /SCHEDULE",
            "text": "User and job services.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-k-handout",
            "locator": "pp.1–2",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "cores",
            "to": "l1",
            "type": "data",
            "source": "parallel-k-handout",
            "locator": "p.1",
            "label": ""
          },
          {
            "from": "l1",
            "to": "l2",
            "type": "data",
            "source": "parallel-k-handout",
            "locator": "p.1",
            "label": ""
          },
          {
            "from": "l2",
            "to": "mem",
            "type": "data",
            "source": "parallel-k-handout",
            "locator": "p.1",
            "label": ""
          },
          {
            "from": "mem",
            "to": "l2",
            "type": "data",
            "source": "parallel-k-handout",
            "locator": "p.1",
            "label": ""
          },
          {
            "from": "cores",
            "to": "icc",
            "type": "association",
            "source": "parallel-k-handout",
            "locator": "p.1",
            "label": ""
          },
          {
            "from": "icc",
            "to": "tofu",
            "type": "data",
            "source": "parallel-k-handout",
            "locator": "p.1",
            "label": ""
          },
          {
            "from": "tofu",
            "to": "icc",
            "type": "data",
            "source": "parallel-k-handout",
            "locator": "p.1",
            "label": ""
          },
          {
            "from": "tofu",
            "to": "ionode",
            "type": "data",
            "source": "parallel-k-handout",
            "locator": "p.1",
            "label": ""
          },
          {
            "from": "ionode",
            "to": "localfs",
            "type": "data",
            "source": "parallel-k-handout",
            "locator": "p.1",
            "label": ""
          },
          {
            "from": "globalfs",
            "to": "localfs",
            "type": "data",
            "source": "parallel-k-handout",
            "locator": "p.2",
            "label": "stage-in"
          },
          {
            "from": "localfs",
            "to": "globalfs",
            "type": "data",
            "source": "parallel-k-handout",
            "locator": "p.2",
            "label": "stage-out"
          },
          {
            "from": "front",
            "to": "globalfs",
            "type": "data",
            "source": "parallel-k-handout",
            "locator": "p.1",
            "label": ""
          },
          {
            "from": "front",
            "to": "tofu",
            "type": "association",
            "source": "parallel-k-handout",
            "locator": "p.1",
            "label": ""
          }
        ]
      },
      "originalCandidate": "K computer"
    },
    {
      "id": "queue-073",
      "name": "ILLIAC IV —1974 single quadrant",
      "organization": "Burroughs /NASA",
      "year": 1974,
      "yearLabel": "1974 manufacturer configuration",
      "kind": "Documented system configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "simd",
        "distributed",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-illiac4"
      ],
      "summary": "A scalar controller broadcasts operations to64 independently masked arithmetic elements.",
      "config": "One64-PE quadrant with B6700 control computer in the1974 brochure.",
      "gaps": [
        "Earlier four-quadrant proposals are outside scope."
      ],
      "insight": "How can lockstep elements follow data-dependent conditions?",
      "fields": {
        "state": {
          "value": "64/32/8-bit operands",
          "source": "parallel-illiac4",
          "locator": "Major system elements"
        },
        "compute": {
          "value": "64 PEs under one CU",
          "source": "parallel-illiac4",
          "locator": "Major system elements"
        },
        "memory": {
          "value": "2048 ×64-bit words/PE",
          "source": "parallel-illiac4",
          "locator": "Major system elements"
        },
        "control": {
          "value": "Broadcast instructions; per-PE mode and index",
          "source": "parallel-illiac4",
          "locator": "On-off control; Addressing"
        },
        "io": {
          "value": "I/O subsystem and disk subsystem",
          "source": "parallel-illiac4",
          "locator": "Major system elements"
        },
        "software": {
          "value": "B6700 compilation and executive control",
          "source": "parallel-illiac4",
          "locator": "Major system elements"
        },
        "workload": {
          "value": "Parallel array computation",
          "source": "parallel-illiac4",
          "locator": "Features of array operation"
        }
      },
      "diagram": {
        "title": "Broadcast control, local selection, chordal routing",
        "scope": "One PE expanded; neighbor groups show the documented±1 and±8 routes modulo64.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "host",
            "label": "B6700 control computer",
            "subtitle": "EXECUTIVE",
            "text": "Compiles programs and supervises the array computer.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-illiac4",
            "locator": "Major system elements",
            "control": true
          },
          {
            "id": "cu",
            "label": "Control Unit",
            "subtitle": "SCALAR /BROADCAST",
            "text": "Broadcasts instructions to the64 processing elements.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-illiac4",
            "locator": "Conventional instruction set",
            "control": true
          },
          {
            "id": "mode",
            "label": "PE0 mode/index",
            "subtitle": "LOCAL SELECTION",
            "text": "Selects local participation and supplies index state.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-illiac4",
            "locator": "On-off control; Addressing",
            "control": true
          },
          {
            "id": "pe",
            "label": "PE0 arithmetic/registers",
            "subtitle": "FOUR REGISTERS",
            "text": "Performs the active element’s arithmetic and register operations.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-illiac4",
            "locator": "Major system elements",
            "control": false
          },
          {
            "id": "pem",
            "label": "PE0 memory",
            "subtitle": "2048 ×64 BITS",
            "text": "Holds the processing element’s local array data.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-illiac4",
            "locator": "Major system elements",
            "control": false
          },
          {
            "id": "n1",
            "label": "PE±1 neighbors",
            "subtitle": "MODULO64 ROUTE",
            "text": "Routes values to adjacent elements modulo64.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-illiac4",
            "locator": "Routing",
            "control": false
          },
          {
            "id": "n8",
            "label": "PE±8 neighbors",
            "subtitle": "MODULO64 ROUTE",
            "text": "Routes values eight positions around the quadrant.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-illiac4",
            "locator": "Routing",
            "control": false
          },
          {
            "id": "others",
            "label": "Other processing units",
            "subtitle": "63 PE /MEMORY PAIRS",
            "text": "Execute the same broadcast operation on other local data.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-illiac4",
            "locator": "Major system elements",
            "control": false
          },
          {
            "id": "io",
            "label": "I/O subsystem",
            "subtitle": "SYSTEM DATA ROUTING",
            "text": "Transfers array data through the dedicated I/O subsystem.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-illiac4",
            "locator": "Major system elements",
            "control": false
          },
          {
            "id": "disk",
            "label": "Disk file subsystem",
            "subtitle": "INTERMEDIATE STORAGE",
            "text": "Provides the documented disk-file backing store.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-illiac4",
            "locator": "Major system elements",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "cu",
            "type": "control",
            "source": "parallel-illiac4",
            "locator": "Major system elements",
            "label": ""
          },
          {
            "from": "cu",
            "to": "pe",
            "type": "control",
            "source": "parallel-illiac4",
            "locator": "Broadcasting",
            "label": ""
          },
          {
            "from": "cu",
            "to": "mode",
            "type": "control",
            "source": "parallel-illiac4",
            "locator": "On-off control",
            "label": ""
          },
          {
            "from": "mode",
            "to": "pe",
            "type": "control",
            "source": "parallel-illiac4",
            "locator": "On-off control",
            "label": ""
          },
          {
            "from": "pem",
            "to": "pe",
            "type": "data",
            "source": "parallel-illiac4",
            "locator": "Major system elements",
            "label": ""
          },
          {
            "from": "pe",
            "to": "pem",
            "type": "data",
            "source": "parallel-illiac4",
            "locator": "Major system elements",
            "label": ""
          },
          {
            "from": "pe",
            "to": "n1",
            "type": "data",
            "source": "parallel-illiac4",
            "locator": "Routing",
            "label": ""
          },
          {
            "from": "pe",
            "to": "n8",
            "type": "data",
            "source": "parallel-illiac4",
            "locator": "Routing",
            "label": ""
          },
          {
            "from": "cu",
            "to": "others",
            "type": "control",
            "source": "parallel-illiac4",
            "locator": "Broadcasting",
            "label": ""
          },
          {
            "from": "io",
            "to": "pem",
            "type": "data",
            "source": "parallel-illiac4",
            "locator": "Major system elements",
            "label": ""
          },
          {
            "from": "host",
            "to": "io",
            "type": "control",
            "source": "parallel-illiac4",
            "locator": "Major system elements",
            "label": ""
          },
          {
            "from": "disk",
            "to": "io",
            "type": "data",
            "source": "parallel-illiac4",
            "locator": "Major system elements",
            "label": ""
          }
        ]
      },
      "originalCandidate": "ILLIAC IV"
    },
    {
      "id": "queue-074",
      "name": "Thinking Machines CM-1 —1985 prototype design",
      "organization": "Thinking Machines /MIT",
      "year": 1985,
      "yearLabel": "June1985 dissertation design",
      "kind": "Documented prototype design",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "simd",
        "distributed",
        "microcoded"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-cm1"
      ],
      "summary": "Bit-serial cells combine local NEWS communication with packet routing between processor chips.",
      "config": "The dissertation’s65536-cell CM-1 prototype, described during construction.",
      "gaps": [
        "Direct MIT scan was inaccessible; transcription-only evidence is identified."
      ],
      "insight": "Why provide both grid and arbitrary-message networks?",
      "fields": {
        "state": {
          "value": "One-bit datapaths; eight flag bits/cell",
          "source": "parallel-cm1",
          "locator": "§4.2"
        },
        "compute": {
          "value": "16 cells/router chip",
          "source": "parallel-cm1",
          "locator": "§4.1"
        },
        "memory": {
          "value": "4096 bits/cell",
          "source": "parallel-cm1",
          "locator": "p.69"
        },
        "control": {
          "value": "Host macrocommands become broadcast nanoinstructions",
          "source": "parallel-cm1",
          "locator": "§4.5"
        },
        "io": {
          "value": "Independent parallel I/O path",
          "source": "parallel-cm1",
          "locator": "§1.5"
        },
        "software": {
          "value": "Connection Machine Lisp",
          "source": "parallel-cm1",
          "locator": "Chapter2"
        },
        "workload": {
          "value": "Symbolic graphs and parallel data",
          "source": "parallel-cm1",
          "locator": "Chapters2/5"
        }
      },
      "diagram": {
        "title": "Macrocommands become bit operations and routed messages",
        "scope": "Text-derived logical paths; injector/heart/ejector separate packet roles.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "host",
            "label": "Conventional host",
            "subtitle": "MACROCOMMANDS",
            "text": "Sends macrocommands to the prototype’s SIMD controller.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm1",
            "locator": "§4.5",
            "control": true
          },
          {
            "id": "fifo",
            "label": "Input/output FIFOs",
            "subtitle": "ASYNCHRONOUS BUFFERING",
            "text": "Buffers the independent parallel input/output path.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm1",
            "locator": "§4.5",
            "control": false
          },
          {
            "id": "micro",
            "label": "Microcontroller",
            "subtitle": "NANOINSTRUCTIONS",
            "text": "Expands host commands into broadcast nanoinstructions.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm1",
            "locator": "§4.5",
            "control": true
          },
          {
            "id": "chipctrl",
            "label": "Chip control",
            "subtitle": "DECODE /BROADCAST",
            "text": "Distributes common control within one processor chip.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm1",
            "locator": "§4.1",
            "control": true
          },
          {
            "id": "cell",
            "label": "Sixteen bit-serial cells",
            "subtitle": "FLAGS /ALU",
            "text": "Executes bit-serial operations on sixteen local cells.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cm1",
            "locator": "§§4.1–4.2",
            "control": false
          },
          {
            "id": "mem",
            "label": "External cell memory",
            "subtitle": "4096 BITS/CELL",
            "text": "Provides each cell’s private4096-bit storage.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cm1",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "news",
            "label": "NEWS neighbor paths",
            "subtitle": "4×4 LOCAL GRID",
            "text": "Moves data along local geometric neighbor routes.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm1",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "inject",
            "label": "Router injector/ejector",
            "subtitle": "CELL MESSAGE BOUNDARY",
            "text": "Admits and delivers addressed packets to local cells.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cm1",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "heart",
            "label": "Router heart",
            "subtitle": "INTERCHIP FORWARDING",
            "text": "Forwards packets between chip-level cube connections.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cm1",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "cube",
            "label": "Other router chips",
            "subtitle": "BOOLEAN CUBE",
            "text": "Represents remote chip routers in the packet network.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-cm1",
            "locator": "§4.3",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "fifo",
            "type": "control",
            "source": "parallel-cm1",
            "locator": "§4.5",
            "label": ""
          },
          {
            "from": "fifo",
            "to": "micro",
            "type": "control",
            "source": "parallel-cm1",
            "locator": "§4.5",
            "label": ""
          },
          {
            "from": "micro",
            "to": "chipctrl",
            "type": "control",
            "source": "parallel-cm1",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "chipctrl",
            "to": "cell",
            "type": "control",
            "source": "parallel-cm1",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "cell",
            "to": "mem",
            "type": "data",
            "source": "parallel-cm1",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "mem",
            "to": "cell",
            "type": "data",
            "source": "parallel-cm1",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "cell",
            "to": "news",
            "type": "data",
            "source": "parallel-cm1",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "cell",
            "to": "inject",
            "type": "data",
            "source": "parallel-cm1",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "inject",
            "to": "heart",
            "type": "data",
            "source": "parallel-cm1",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "heart",
            "to": "cube",
            "type": "data",
            "source": "parallel-cm1",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "cube",
            "to": "heart",
            "type": "data",
            "source": "parallel-cm1",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "heart",
            "to": "mem",
            "type": "data",
            "source": "parallel-cm1",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "cell",
            "to": "micro",
            "type": "control",
            "source": "parallel-cm1",
            "locator": "§4.1",
            "label": "global/error return"
          }
        ]
      },
      "originalCandidate": "Thinking Machines CM-1"
    },
    {
      "id": "queue-075",
      "name": "Thinking Machines CM-2 —64K with floating option",
      "organization": "Thinking Machines",
      "year": 1987,
      "yearLabel": "April1987 technical summary",
      "kind": "Commercial reference configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "simd",
        "distributed",
        "heterogeneous",
        "microcoded"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-cm2"
      ],
      "summary": "Bit-serial processing and programmable neighbor exchange are augmented by shared floating-point accelerators.",
      "config": "65536 data processors with the documented floating-point option; precision option remains explicit.",
      "gaps": [
        "Single/double precision FP options differ.",
        "NEWS dimensions are programmable; the packet network’s12-cube is separate."
      ],
      "insight": "How does one floating unit serve32 bit-serial processors?",
      "fields": {
        "state": {
          "value": "Bit-addressable state; optional IEEE floating point",
          "source": "parallel-cm2",
          "locator": "§§4.1/4.3"
        },
        "compute": {
          "value": "64K data processors; one FP pair/32",
          "source": "parallel-cm2",
          "locator": "p.19"
        },
        "memory": {
          "value": "64K bits/processor;512MB total",
          "source": "parallel-cm2",
          "locator": "pp.4,19"
        },
        "control": {
          "value": "Front-end Paris instructions, sequencer broadcast",
          "source": "parallel-cm2",
          "locator": "pp.6–7"
        },
        "io": {
          "value": "Data-parallel channels and DataVault/framebuffer",
          "source": "parallel-cm2",
          "locator": "p.7"
        },
        "software": {
          "value": "Paris, C*, Fortran, *Lisp",
          "source": "parallel-cm2",
          "locator": "Chapters3/9"
        },
        "workload": {
          "value": "Data-parallel scientific and symbolic computation",
          "source": "parallel-cm2",
          "locator": "Chapter1"
        }
      },
      "diagram": {
        "title": "Partition control and two arithmetic paths",
        "scope": "One32-processor floating-point sharing group expanded; other groups are implicit.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "front",
            "label": "Front-end computer",
            "subtitle": "PARIS PROGRAM",
            "text": "Runs host code and issues Paris operations.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm2",
            "locator": "Chapter2",
            "control": true
          },
          {
            "id": "nexus",
            "label": "Nexus switch",
            "subtitle": "PARTITION ATTACHMENT",
            "text": "Connects front ends to Connection Machine sections.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm2",
            "locator": "p.7",
            "control": false
          },
          {
            "id": "seq",
            "label": "Section sequencer",
            "subtitle": "LOW-LEVEL BROADCAST",
            "text": "Broadcasts section instructions to local processors.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm2",
            "locator": "pp.6–7",
            "control": true
          },
          {
            "id": "bit",
            "label": "Bit-serial processors",
            "subtitle": "ALU /FLAGS",
            "text": "Executes bit-serial operations under local activity flags.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cm2",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "mem",
            "label": "Local processor memory",
            "subtitle": "64K BITS /PROCESSOR",
            "text": "Stores private data for each bit-serial processor.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cm2",
            "locator": "p.19",
            "control": false
          },
          {
            "id": "fpif",
            "label": "Floating memory interface",
            "subtitle": "32 PROCESSORS /PAIR",
            "text": "Connects a32-processor group’s memory to floating hardware.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cm2",
            "locator": "§4.3",
            "control": false
          },
          {
            "id": "fp",
            "label": "FP execution chip",
            "subtitle": "OPTIONAL IEEE UNIT",
            "text": "Executes the selected floating-point precision option.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm2",
            "locator": "§4.3",
            "control": false
          },
          {
            "id": "router",
            "label": "Packet router network",
            "subtitle": "4096-NODE12-CUBE",
            "text": "Carries addressed packets on the separate12-cube network.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-cm2",
            "locator": "§4.2",
            "control": false
          },
          {
            "id": "news",
            "label": "Programmable NEWS grid",
            "subtitle": "RECTANGULAR EXCHANGES",
            "text": "Provides a programmable geometric neighbor organization.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-cm2",
            "locator": "p.6",
            "control": false
          },
          {
            "id": "io",
            "label": "Parallel I/O devices",
            "subtitle": "DATAVAULT /DISPLAY",
            "text": "Moves parallel data to storage and display devices.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-cm2",
            "locator": "p.7",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "front",
            "to": "nexus",
            "type": "control",
            "source": "parallel-cm2",
            "locator": "p.7",
            "label": ""
          },
          {
            "from": "nexus",
            "to": "seq",
            "type": "control",
            "source": "parallel-cm2",
            "locator": "p.7",
            "label": ""
          },
          {
            "from": "seq",
            "to": "bit",
            "type": "control",
            "source": "parallel-cm2",
            "locator": "pp.6–7",
            "label": ""
          },
          {
            "from": "bit",
            "to": "mem",
            "type": "data",
            "source": "parallel-cm2",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "mem",
            "to": "bit",
            "type": "data",
            "source": "parallel-cm2",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "mem",
            "to": "fpif",
            "type": "data",
            "source": "parallel-cm2",
            "locator": "§4.3",
            "label": ""
          },
          {
            "from": "fpif",
            "to": "fp",
            "type": "data",
            "source": "parallel-cm2",
            "locator": "§4.3",
            "label": ""
          },
          {
            "from": "fp",
            "to": "fpif",
            "type": "data",
            "source": "parallel-cm2",
            "locator": "§4.3",
            "label": ""
          },
          {
            "from": "fpif",
            "to": "mem",
            "type": "data",
            "source": "parallel-cm2",
            "locator": "§4.3",
            "label": ""
          },
          {
            "from": "bit",
            "to": "router",
            "type": "data",
            "source": "parallel-cm2",
            "locator": "§4.2",
            "label": ""
          },
          {
            "from": "bit",
            "to": "news",
            "type": "data",
            "source": "parallel-cm2",
            "locator": "p.6",
            "label": ""
          },
          {
            "from": "seq",
            "to": "io",
            "type": "control",
            "source": "parallel-cm2",
            "locator": "p.7",
            "label": ""
          },
          {
            "from": "io",
            "to": "mem",
            "type": "data",
            "source": "parallel-cm2",
            "locator": "p.7",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Thinking Machines CM-2"
    },
    {
      "id": "queue-076",
      "name": "Thinking Machines CM-5 —initial network architecture",
      "organization": "Thinking Machines",
      "year": 1992,
      "yearLabel": "November1992 designer report",
      "kind": "Commercial reference architecture",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "distributed",
        "vector",
        "risc"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-cm5"
      ],
      "summary": "SPARC/vector nodes use separate networks for point-to-point traffic, collectives, and diagnosis.",
      "config": "Initial-release nodes in the1992 report;32–16384-node range is a product parameter, not one installation.",
      "gaps": [
        "Network topology is hidden from user addressing; physical wires are not a programming interface."
      ],
      "insight": "Why separate collective control from the fat-tree data network?",
      "fields": {
        "state": {
          "value": "64-bit vector floating/integer values",
          "source": "parallel-cm5",
          "locator": "§1"
        },
        "compute": {
          "value": "SPARC plus vector processing/node",
          "source": "parallel-cm5",
          "locator": "§1"
        },
        "memory": {
          "value": "32MB/node in this release",
          "source": "parallel-cm5",
          "locator": "§1"
        },
        "control": {
          "value": "Sun control processors and partition protection",
          "source": "parallel-cm5",
          "locator": "§§1–2"
        },
        "io": {
          "value": "Addressable I/O channels on data/control networks",
          "source": "parallel-cm5",
          "locator": "§§1/3"
        },
        "software": {
          "value": "User-accessible mapped FIFOs; data-parallel environments",
          "source": "parallel-cm5",
          "locator": "§§2/5"
        },
        "workload": {
          "value": "Data-parallel and message-passing applications",
          "source": "parallel-cm5",
          "locator": "§§1/5"
        }
      },
      "diagram": {
        "title": "One interface, three network responsibilities",
        "scope": "Physical grouping is conceptual; diagnostic paths denote back-door access, not application traffic.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "sparc",
            "label": "Node SPARC",
            "subtitle": "LOCAL EXECUTION",
            "text": "Executes scalar code and controls local vector work.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm5",
            "locator": "§1",
            "control": false
          },
          {
            "id": "vector",
            "label": "Node vector processing",
            "subtitle": "64-BIT ARITHMETIC",
            "text": "Runs node-local vector operations beside the SPARC.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm5",
            "locator": "§1",
            "control": false
          },
          {
            "id": "memory",
            "label": "Node memory",
            "subtitle": "32MB",
            "text": "Stores the node’s instructions and working data.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cm5",
            "locator": "§1",
            "control": false
          },
          {
            "id": "ni",
            "label": "Network interface",
            "subtitle": "MAPPED FIFOs /PROTECTION",
            "text": "Exposes mapped communication FIFOs to node software.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cm5",
            "locator": "§2",
            "control": false
          },
          {
            "id": "fat",
            "label": "4-ary fat-tree",
            "subtitle": "POINT-TO-POINT DATA",
            "text": "Routes point-to-point data through a fat-tree.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm5",
            "locator": "§3",
            "control": false
          },
          {
            "id": "control",
            "label": "Control network",
            "subtitle": "BROADCAST /SCAN /BARRIER",
            "text": "Performs collective communication and global coordination.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cm5",
            "locator": "§5",
            "control": true
          },
          {
            "id": "diag",
            "label": "Diagnostic network",
            "subtitle": "PRIVILEGED TEST ACCESS",
            "text": "Provides independent diagnostic access to system components.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-cm5",
            "locator": "§6",
            "control": true
          },
          {
            "id": "remote",
            "label": "Other processing nodes",
            "subtitle": "PARTITION ENDPOINTS",
            "text": "Represents other independent processing nodes.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cm5",
            "locator": "§1",
            "control": false
          },
          {
            "id": "cp",
            "label": "Control processors",
            "subtitle": "SUN WORKSTATIONS",
            "text": "Supervises partitions and launches distributed work.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-cm5",
            "locator": "§1",
            "control": true
          },
          {
            "id": "io",
            "label": "I/O interfaces",
            "subtitle": "DISK /GRAPHICS /NETWORK",
            "text": "Connects external channels to the communication networks.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-cm5",
            "locator": "§1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "sparc",
            "to": "vector",
            "type": "association",
            "source": "parallel-cm5",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "sparc",
            "to": "memory",
            "type": "data",
            "source": "parallel-cm5",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "sparc",
            "to": "ni",
            "type": "data",
            "source": "parallel-cm5",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "ni",
            "to": "fat",
            "type": "data",
            "source": "parallel-cm5",
            "locator": "§§2–3",
            "label": ""
          },
          {
            "from": "fat",
            "to": "ni",
            "type": "data",
            "source": "parallel-cm5",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "ni",
            "to": "control",
            "type": "control",
            "source": "parallel-cm5",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "control",
            "to": "ni",
            "type": "control",
            "source": "parallel-cm5",
            "locator": "§5",
            "label": ""
          },
          {
            "from": "fat",
            "to": "remote",
            "type": "data",
            "source": "parallel-cm5",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "control",
            "to": "remote",
            "type": "control",
            "source": "parallel-cm5",
            "locator": "§5",
            "label": ""
          },
          {
            "from": "cp",
            "to": "fat",
            "type": "data",
            "source": "parallel-cm5",
            "locator": "Fig.1",
            "label": ""
          },
          {
            "from": "cp",
            "to": "control",
            "type": "control",
            "source": "parallel-cm5",
            "locator": "Fig.1",
            "label": ""
          },
          {
            "from": "fat",
            "to": "io",
            "type": "data",
            "source": "parallel-cm5",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "diag",
            "to": "sparc",
            "type": "control",
            "source": "parallel-cm5",
            "locator": "§6",
            "label": ""
          },
          {
            "from": "diag",
            "to": "ni",
            "type": "control",
            "source": "parallel-cm5",
            "locator": "§6",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Thinking Machines CM-5"
    },
    {
      "id": "queue-077",
      "name": "MasPar MP-1 —16K/16KB reference",
      "organization": "MasPar Computer Corporation",
      "year": 1990,
      "yearLabel": "1990 designer paper configuration",
      "kind": "Commercial reference configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "simd",
        "distributed",
        "microcoded",
        "load-store"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-mp1"
      ],
      "summary": "A microcoded scalar controller drives nibble-oriented PEs with local memory and two communication networks.",
      "config": "16384 PEs with16KB/PE in the1990 paper; later64KB variants and MP-2 excluded.",
      "gaps": [
        "Ports are shared among16 PEs; a router is not dedicated to each PE."
      ],
      "insight": "Which communication stays with eight neighbors and which traverses the global router?",
      "fields": {
        "state": {
          "value": "40 programmer-visible32-bit registers/PE",
          "source": "parallel-mp1",
          "locator": "p.26"
        },
        "compute": {
          "value": "4-bit ALU with mantissa/exponent support",
          "source": "parallel-mp1",
          "locator": "pp.26–27"
        },
        "memory": {
          "value": "16KB ECC DRAM/PE",
          "source": "parallel-mp1",
          "locator": "p.26"
        },
        "control": {
          "value": "ACU broadcasts microcontrols; local enable flags",
          "source": "parallel-mp1",
          "locator": "pp.25/27"
        },
        "io": {
          "value": "Global router also supports I/O",
          "source": "parallel-mp1",
          "locator": "p.27"
        },
        "software": {
          "value": "Compiler-scheduled load/store overlap",
          "source": "parallel-mp1",
          "locator": "p.27"
        },
        "workload": {
          "value": "General data-parallel computation",
          "source": "parallel-mp1",
          "locator": "p.25"
        }
      },
      "diagram": {
        "title": "Nibble computation, overlapped memory, two networks",
        "scope": "One PE expanded; global router stages are explicit and the X-Net path is separate.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "acu",
            "label": "Array Control Unit",
            "subtitle": "SCALAR /MICROCODE",
            "text": "Issues common microcontrols to the SIMD array.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-mp1",
            "locator": "p.25",
            "control": true
          },
          {
            "id": "regs",
            "label": "PE register file",
            "subtitle": "40 USER +8 INTERNAL",
            "text": "Holds each PE’s programmer-visible scalar register values.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-mp1",
            "locator": "p.26",
            "control": false
          },
          {
            "id": "alu",
            "label": "ALU /mantissa /exponent",
            "subtitle": "NIBBLE /BIT PATHS",
            "text": "Performs nibble-oriented arithmetic with floating-point support.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-mp1",
            "locator": "Fig.3",
            "control": false
          },
          {
            "id": "flags",
            "label": "PE flags /enable",
            "subtitle": "LOCAL PREDICATION",
            "text": "Controls local conditional participation in broadcast instructions.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-mp1",
            "locator": "p.27",
            "control": true
          },
          {
            "id": "memctl",
            "label": "PE memory address/data",
            "subtitle": "QUEUED LOAD /STORE",
            "text": "Overlaps PE memory transfers with arithmetic activity.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-mp1",
            "locator": "Fig.3; p.27",
            "control": false
          },
          {
            "id": "dram",
            "label": "PE external memory",
            "subtitle": "16KB ECC DRAM",
            "text": "Provides16KB of local ECC-protected storage.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-mp1",
            "locator": "p.26",
            "control": false
          },
          {
            "id": "xnet",
            "label": "X-Net neighbor mesh",
            "subtitle": "EIGHT NEIGHBORS /TORUS",
            "text": "Moves data among nearby PEs independently of global routing.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-mp1",
            "locator": "p.27",
            "control": false
          },
          {
            "id": "s1",
            "label": "Router stageS1",
            "subtitle": "ORIGIN PORT",
            "text": "Accepts global-router traffic from shared PE ports.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-mp1",
            "locator": "p.27",
            "control": false
          },
          {
            "id": "s2",
            "label": "Router stageS2",
            "subtitle": "GLOBAL SWITCHING",
            "text": "Provides the middle global-router switching stage.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-mp1",
            "locator": "p.27",
            "control": false
          },
          {
            "id": "s3",
            "label": "Router stageS3",
            "subtitle": "TARGET PORT",
            "text": "Delivers globally routed values toward destination PEs.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-mp1",
            "locator": "p.27",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "acu",
            "to": "alu",
            "type": "control",
            "source": "parallel-mp1",
            "locator": "p.27",
            "label": ""
          },
          {
            "from": "acu",
            "to": "memctl",
            "type": "control",
            "source": "parallel-mp1",
            "locator": "p.27",
            "label": ""
          },
          {
            "from": "flags",
            "to": "alu",
            "type": "control",
            "source": "parallel-mp1",
            "locator": "p.27",
            "label": ""
          },
          {
            "from": "regs",
            "to": "alu",
            "type": "data",
            "source": "parallel-mp1",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "alu",
            "to": "regs",
            "type": "data",
            "source": "parallel-mp1",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "regs",
            "to": "memctl",
            "type": "data",
            "source": "parallel-mp1",
            "locator": "p.27",
            "label": ""
          },
          {
            "from": "memctl",
            "to": "dram",
            "type": "data",
            "source": "parallel-mp1",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "dram",
            "to": "memctl",
            "type": "data",
            "source": "parallel-mp1",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "alu",
            "to": "xnet",
            "type": "data",
            "source": "parallel-mp1",
            "locator": "p.27",
            "label": ""
          },
          {
            "from": "alu",
            "to": "s1",
            "type": "data",
            "source": "parallel-mp1",
            "locator": "pp.27–28",
            "label": ""
          },
          {
            "from": "s1",
            "to": "s2",
            "type": "data",
            "source": "parallel-mp1",
            "locator": "p.27",
            "label": ""
          },
          {
            "from": "s2",
            "to": "s3",
            "type": "data",
            "source": "parallel-mp1",
            "locator": "p.27",
            "label": ""
          },
          {
            "from": "s3",
            "to": "alu",
            "type": "data",
            "source": "parallel-mp1",
            "locator": "pp.27–28",
            "label": ""
          },
          {
            "from": "flags",
            "to": "acu",
            "type": "control",
            "source": "parallel-mp1",
            "locator": "p.27",
            "label": "OR reduction"
          }
        ]
      },
      "originalCandidate": "MasPar MP-1"
    },
    {
      "id": "queue-078",
      "name": "Goodyear MPP —1980 reference design",
      "organization": "Goodyear Aerospace /NASA Goddard",
      "year": 1980,
      "yearLabel": "1980 designer paper",
      "kind": "Documented pre-delivery system design",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "simd",
        "distributed",
        "bitstream",
        "fault-tolerant"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-mpp"
      ],
      "summary": "Bit-serial image processing overlaps scalar control, array control, and bit-plane I/O.",
      "config": "128×128 logical PEs,1024 bits/PE; spare columns preserve the logical array.",
      "gaps": [
        "Paper describes intended delivery; later operational memory expansions are excluded."
      ],
      "insight": "Why reorder pixel streams into bit planes before processing?",
      "fields": {
        "state": {
          "value": "Bit-serial variable-length operands",
          "source": "parallel-mpp",
          "locator": "pp.175–176"
        },
        "compute": {
          "value": "16384 logical PEs; full-adder/shift-register arithmetic",
          "source": "parallel-mpp",
          "locator": "pp.175–176"
        },
        "memory": {
          "value": "1024 RAM bits/PE",
          "source": "parallel-mpp",
          "locator": "p.177"
        },
        "control": {
          "value": "Separate main, PE and I/O controls",
          "source": "parallel-mpp",
          "locator": "pp.177–178"
        },
        "io": {
          "value": "Multidimensional-access reorder buffers",
          "source": "parallel-mpp",
          "locator": "p.178"
        },
        "software": {
          "value": "PDP-11 RSX-11M and ACU assemblers",
          "source": "parallel-mpp",
          "locator": "p.178"
        },
        "workload": {
          "value": "Satellite image processing",
          "source": "parallel-mpp",
          "locator": "p.174"
        }
      },
      "diagram": {
        "title": "Bit planes, independent controls, and global reduction",
        "scope": "One PE expanded. Spare-column and boundary controls are represented as control relationships.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "host",
            "label": "VAX host",
            "subtitle": "EXTERNAL APPLICATION",
            "text": "Provides the external host-computer environment.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-mpp",
            "locator": "p.179",
            "control": false
          },
          {
            "id": "pdmu",
            "label": "PDP-11 PDMU",
            "subtitle": "PROGRAM /DATA MANAGEMENT",
            "text": "Develops and manages ACU programs under RSX-11M.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-mpp",
            "locator": "p.178",
            "control": true
          },
          {
            "id": "main",
            "label": "ACU Main Control",
            "subtitle": "SCALAR APPLICATION",
            "text": "Runs scalar control alongside array operations.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-mpp",
            "locator": "p.178",
            "control": true
          },
          {
            "id": "pectl",
            "label": "ACU PE Control",
            "subtitle": "ARRAY MICROINSTRUCTIONS",
            "text": "Broadcasts processing-element control across the image array.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-mpp",
            "locator": "p.178",
            "control": true
          },
          {
            "id": "ioctl",
            "label": "ACU I/O Control",
            "subtitle": "OVERLAPPED TRANSFERS",
            "text": "Controls data transfers independently of PE computation.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-mpp",
            "locator": "p.178",
            "control": true
          },
          {
            "id": "reorder",
            "label": "Reorder I/O memory",
            "subtitle": "PIXELS ↔BIT PLANES",
            "text": "Rearranges image data for bit-plane array access.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-mpp",
            "locator": "p.178",
            "control": false
          },
          {
            "id": "s",
            "label": "PE S-register array",
            "subtitle": "I/O SHIFT PATH",
            "text": "Stages incoming and outgoing PE bit planes.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-mpp",
            "locator": "p.176",
            "control": false
          },
          {
            "id": "ram",
            "label": "PE RAM",
            "subtitle": "1024 BITS /PE",
            "text": "Stores1024 private bits per processing element.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-mpp",
            "locator": "p.177",
            "control": false
          },
          {
            "id": "pe",
            "label": "PE arithmetic /P routing",
            "subtitle": "FULL ADDER /SHIFT",
            "text": "Computes bit-serial values and routes neighbor data.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-mpp",
            "locator": "p.176",
            "control": false
          },
          {
            "id": "tree",
            "label": "Sum-or tree",
            "subtitle": "GLOBAL REDUCTION",
            "text": "Reduces array-wide sum/or information toward control.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-mpp",
            "locator": "p.177",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "pdmu",
            "type": "control",
            "source": "parallel-mpp",
            "locator": "p.179",
            "label": ""
          },
          {
            "from": "pdmu",
            "to": "main",
            "type": "control",
            "source": "parallel-mpp",
            "locator": "p.178",
            "label": ""
          },
          {
            "from": "main",
            "to": "pectl",
            "type": "control",
            "source": "parallel-mpp",
            "locator": "p.178",
            "label": "queued calls"
          },
          {
            "from": "main",
            "to": "ioctl",
            "type": "control",
            "source": "parallel-mpp",
            "locator": "p.178",
            "label": ""
          },
          {
            "from": "pectl",
            "to": "pe",
            "type": "control",
            "source": "parallel-mpp",
            "locator": "p.178",
            "label": ""
          },
          {
            "from": "reorder",
            "to": "s",
            "type": "data",
            "source": "parallel-mpp",
            "locator": "pp.178–179",
            "label": ""
          },
          {
            "from": "s",
            "to": "ram",
            "type": "data",
            "source": "parallel-mpp",
            "locator": "p.176",
            "label": ""
          },
          {
            "from": "ram",
            "to": "s",
            "type": "data",
            "source": "parallel-mpp",
            "locator": "p.176",
            "label": ""
          },
          {
            "from": "ioctl",
            "to": "s",
            "type": "control",
            "source": "parallel-mpp",
            "locator": "p.178",
            "label": ""
          },
          {
            "from": "ram",
            "to": "pe",
            "type": "data",
            "source": "parallel-mpp",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "pe",
            "to": "ram",
            "type": "data",
            "source": "parallel-mpp",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "pe",
            "to": "tree",
            "type": "data",
            "source": "parallel-mpp",
            "locator": "p.177",
            "label": ""
          },
          {
            "from": "tree",
            "to": "pectl",
            "type": "data",
            "source": "parallel-mpp",
            "locator": "p.177",
            "label": ""
          },
          {
            "from": "pdmu",
            "to": "reorder",
            "type": "data",
            "source": "parallel-mpp",
            "locator": "p.178",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Goodyear MPP"
    },
    {
      "id": "queue-079",
      "name": "Intel iPSC —d5 original system",
      "organization": "Intel Scientific Computers",
      "year": 1985,
      "yearLabel": "1985 introduction, participant account",
      "kind": "Commercial system configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "distributed",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-ipsc"
      ],
      "summary": "Independent286 nodes exchange messages along a five-dimensional cube.",
      "config": "Original32-node d5; memory-board and later vector/iPSC860 variants excluded.",
      "gaps": [
        "Evidence is a designer-participant retrospective.",
        "Neighbor labels are derived binary identities, not board positions."
      ],
      "insight": "Which destinations are one link from binary node00000?",
      "fields": {
        "state": {
          "value": "80286 integer and80287 floating state",
          "source": "parallel-ipsc",
          "locator": "Intel Personal Supercomputer"
        },
        "compute": {
          "value": "32 nodes",
          "source": "parallel-ipsc",
          "locator": "Intel Personal Supercomputer"
        },
        "memory": {
          "value": "512KB/node",
          "source": "parallel-ipsc",
          "locator": "Intel Personal Supercomputer"
        },
        "control": {
          "value": "Independent nodes with message-passing kernel",
          "source": "parallel-ipsc",
          "locator": "Intel Personal Supercomputer"
        },
        "io": {
          "value": "Cube Manager front end",
          "source": "parallel-ipsc",
          "locator": "Intel Personal Supercomputer"
        },
        "software": {
          "value": "Distributed-array parallel routines",
          "source": "parallel-ipsc",
          "locator": "Distributed Arrays"
        },
        "workload": {
          "value": "Scientific matrix computation",
          "source": "parallel-ipsc",
          "locator": "Distributed Arrays"
        }
      },
      "diagram": {
        "title": "Five cube links from one expanded node",
        "scope": "An induced star in the32-node5-cube; omitted neighbors still have their own five links.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "manager",
            "label": "Cube Manager",
            "subtitle": "FRONT END",
            "text": "Loads and supervises the independent cube nodes.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ipsc",
            "locator": "Intel Personal Supercomputer",
            "control": true
          },
          {
            "id": "cpu",
            "label": "Node00000:80286",
            "subtitle": "APPLICATION /KERNEL",
            "text": "Runs node-local286 code and message-passing work.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ipsc",
            "locator": "Intel Personal Supercomputer",
            "control": false
          },
          {
            "id": "fp",
            "label": "80287 coprocessor",
            "subtitle": "FLOATING POINT",
            "text": "Executes floating-point operations for the node CPU.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ipsc",
            "locator": "Intel Personal Supercomputer",
            "control": false
          },
          {
            "id": "ram",
            "label": "Local memory",
            "subtitle": "512KB",
            "text": "Provides the node’s private512KB working memory.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-ipsc",
            "locator": "Intel Personal Supercomputer",
            "control": false
          },
          {
            "id": "comm",
            "label": "Communication chip",
            "subtitle": "FIVE CUBE LINKS",
            "text": "Handles the node’s five dimension-neighbor connections.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-ipsc",
            "locator": "Intel Personal Supercomputer",
            "control": false
          },
          {
            "id": "b0",
            "label": "Node00001",
            "subtitle": "BIT0 DIFFERS",
            "text": "Differs from node00000 in the least-significant cube bit.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-ipsc",
            "locator": "Hypercube rule; d5",
            "control": false
          },
          {
            "id": "b1",
            "label": "Node00010",
            "subtitle": "BIT1 DIFFERS",
            "text": "Differs from node00000 in cube bit1.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-ipsc",
            "locator": "Hypercube rule; d5",
            "control": false
          },
          {
            "id": "b2",
            "label": "Node00100",
            "subtitle": "BIT2 DIFFERS",
            "text": "Differs from node00000 in cube bit2.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-ipsc",
            "locator": "Hypercube rule; d5",
            "control": false
          },
          {
            "id": "b3",
            "label": "Node01000",
            "subtitle": "BIT3 DIFFERS",
            "text": "Differs from node00000 in cube bit3.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-ipsc",
            "locator": "Hypercube rule; d5",
            "control": false
          },
          {
            "id": "b4",
            "label": "Node10000",
            "subtitle": "BIT4 DIFFERS",
            "text": "Differs from node00000 in cube bit4.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-ipsc",
            "locator": "Hypercube rule; d5",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "manager",
            "to": "cpu",
            "type": "association",
            "source": "parallel-ipsc",
            "locator": "Intel Personal Supercomputer",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "fp",
            "type": "association",
            "source": "parallel-ipsc",
            "locator": "Intel Personal Supercomputer",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "ram",
            "type": "data",
            "source": "parallel-ipsc",
            "locator": "Intel Personal Supercomputer",
            "label": ""
          },
          {
            "from": "ram",
            "to": "cpu",
            "type": "data",
            "source": "parallel-ipsc",
            "locator": "Intel Personal Supercomputer",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "comm",
            "type": "data",
            "source": "parallel-ipsc",
            "locator": "Intel Personal Supercomputer",
            "label": ""
          },
          {
            "from": "comm",
            "to": "b0",
            "type": "data",
            "source": "parallel-ipsc",
            "locator": "Hypercube rule; d5",
            "label": ""
          },
          {
            "from": "comm",
            "to": "b1",
            "type": "data",
            "source": "parallel-ipsc",
            "locator": "Hypercube rule; d5",
            "label": ""
          },
          {
            "from": "comm",
            "to": "b2",
            "type": "data",
            "source": "parallel-ipsc",
            "locator": "Hypercube rule; d5",
            "label": ""
          },
          {
            "from": "comm",
            "to": "b3",
            "type": "data",
            "source": "parallel-ipsc",
            "locator": "Hypercube rule; d5",
            "label": ""
          },
          {
            "from": "comm",
            "to": "b4",
            "type": "data",
            "source": "parallel-ipsc",
            "locator": "Hypercube rule; d5",
            "label": ""
          },
          {
            "from": "b0",
            "to": "comm",
            "type": "data",
            "source": "parallel-ipsc",
            "locator": "Hypercube rule; d5",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Intel iPSC"
    },
    {
      "id": "queue-080",
      "name": "Intel Paragon XP/S —basic dual-processor node",
      "organization": "Intel",
      "year": 1991,
      "yearLabel": "1991 manufacturer reference",
      "kind": "Commercial reference design",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "distributed",
        "heterogeneous",
        "risc"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-paragon"
      ],
      "summary": "A dedicated message processor keeps communication work separate from application execution on each mesh node.",
      "config": "Basic dual-i860XP node in the1991 overview; MP-node development and installation counts excluded.",
      "gaps": [
        "Optional instrumentation and I/O boards vary by node.",
        "Product peak/latency claims are not generalized into measured application performance."
      ],
      "insight": "Why add a full processor between an application and the mesh?",
      "fields": {
        "state": {
          "value": "i860XP scalar/floating-point state",
          "source": "parallel-paragon",
          "locator": "p.7"
        },
        "compute": {
          "value": "Application and message i860XP processors/node",
          "source": "parallel-paragon",
          "locator": "pp.8/11"
        },
        "memory": {
          "value": "Interleaved local ECC DRAM",
          "source": "parallel-paragon",
          "locator": "p.7"
        },
        "control": {
          "value": "Application, service and I/O partitions",
          "source": "parallel-paragon",
          "locator": "p.6"
        },
        "io": {
          "value": "NIC, two transfer engines, PMRC mesh routing",
          "source": "parallel-paragon",
          "locator": "pp.8–11"
        },
        "software": {
          "value": "Distributed UNIX services; C/Fortran/C++ tools",
          "source": "parallel-paragon",
          "locator": "pp.2–3; software sections"
        },
        "workload": {
          "value": "Scientific MIMD/SPMD applications",
          "source": "parallel-paragon",
          "locator": "pp.1–3"
        }
      },
      "diagram": {
        "title": "Communication offload inside a mesh node",
        "scope": "One basic node expanded, with dedicated system-service and I/O endpoints.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "app",
            "label": "Application i860XP",
            "subtitle": "USER COMPUTATION",
            "text": "Runs application computation on the local i860XP.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-paragon",
            "locator": "pp.7–8",
            "control": false
          },
          {
            "id": "msg",
            "label": "Message i860XP",
            "subtitle": "PROTOCOL /PACKETIZATION",
            "text": "Services communication while the application processor computes.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-paragon",
            "locator": "p.11",
            "control": false
          },
          {
            "id": "mem",
            "label": "Local ECC memory",
            "subtitle": "DUAL-BANK /64-BIT",
            "text": "Provides shared node-local ECC-protected data storage.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-paragon",
            "locator": "p.7",
            "control": false
          },
          {
            "id": "dma",
            "label": "Two transfer engines",
            "subtitle": "BLOCK TRANSFERS",
            "text": "Moves message payloads without application-processor copying.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-paragon",
            "locator": "p.11",
            "control": false
          },
          {
            "id": "nic",
            "label": "Network Interface Controller",
            "subtitle": "DUPLEX MESSAGE PORT",
            "text": "Connects local transfers to the node router.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-paragon",
            "locator": "p.11",
            "control": false
          },
          {
            "id": "pmrc",
            "label": "PMRC router",
            "subtitle": "HARDWARE ROUTING",
            "text": "Routes packets through neighboring mesh links.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-paragon",
            "locator": "pp.9–11",
            "control": false
          },
          {
            "id": "mesh",
            "label": "Two-dimensional mesh",
            "subtitle": "OTHER COMPUTE NODES",
            "text": "Connects application,service and I/O node partitions.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-paragon",
            "locator": "p.9",
            "control": false
          },
          {
            "id": "service",
            "label": "Service nodes",
            "subtitle": "OS SERVICES",
            "text": "Supplies distributed operating-system services to compute nodes.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-paragon",
            "locator": "pp.6/8",
            "control": true
          },
          {
            "id": "ionode",
            "label": "I/O nodes",
            "subtitle": "EXTERNAL INTERFACES",
            "text": "Hosts external I/O interfaces at selected mesh nodes.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-paragon",
            "locator": "pp.6/8",
            "control": false
          },
          {
            "id": "devices",
            "label": "Disk /HIPPI /networks",
            "subtitle": "CONFIGURED DEVICES",
            "text": "Provides storage and external communication endpoints.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-paragon",
            "locator": "pp.5–6",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "app",
            "to": "mem",
            "type": "data",
            "source": "parallel-paragon",
            "locator": "pp.7–8",
            "label": ""
          },
          {
            "from": "msg",
            "to": "mem",
            "type": "data",
            "source": "parallel-paragon",
            "locator": "p.8",
            "label": ""
          },
          {
            "from": "msg",
            "to": "nic",
            "type": "control",
            "source": "parallel-paragon",
            "locator": "p.11",
            "label": ""
          },
          {
            "from": "mem",
            "to": "dma",
            "type": "data",
            "source": "parallel-paragon",
            "locator": "p.11",
            "label": ""
          },
          {
            "from": "dma",
            "to": "nic",
            "type": "data",
            "source": "parallel-paragon",
            "locator": "p.11",
            "label": ""
          },
          {
            "from": "nic",
            "to": "dma",
            "type": "data",
            "source": "parallel-paragon",
            "locator": "p.11",
            "label": ""
          },
          {
            "from": "nic",
            "to": "pmrc",
            "type": "data",
            "source": "parallel-paragon",
            "locator": "p.11",
            "label": ""
          },
          {
            "from": "pmrc",
            "to": "mesh",
            "type": "data",
            "source": "parallel-paragon",
            "locator": "p.9",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "pmrc",
            "type": "data",
            "source": "parallel-paragon",
            "locator": "p.9",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "service",
            "type": "data",
            "source": "parallel-paragon",
            "locator": "p.6",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "ionode",
            "type": "data",
            "source": "parallel-paragon",
            "locator": "p.6",
            "label": ""
          },
          {
            "from": "ionode",
            "to": "devices",
            "type": "data",
            "source": "parallel-paragon",
            "locator": "pp.5–6",
            "label": ""
          },
          {
            "from": "app",
            "to": "msg",
            "type": "association",
            "source": "parallel-paragon",
            "locator": "pp.8/11",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Intel Paragon"
    },
    {
      "id": "queue-081",
      "name": "ASCI Red —Pentium Pro reference installation",
      "organization": "Intel /Sandia National Laboratories",
      "year": 1998,
      "yearLabel": "Q1,1998 configuration report",
      "kind": "Built supercomputer installation",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "distributed",
        "smp",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-asci-red"
      ],
      "summary": "Commodity dual-processor nodes form a partitioned mesh with specialized service and I/O roles.",
      "config": "Table2’s4536 compute nodes and200MHz Pentium Pro generation; later upgrades excluded.",
      "gaps": [
        "Node, CPU, and earlier benchmark counts are distinct."
      ],
      "insight": "How do a Kestrel board’s two nodes attach to the mesh?",
      "fields": {
        "state": {
          "value": "IA-32 and x87 state",
          "source": "parallel-asci-red",
          "locator": "p.5"
        },
        "compute": {
          "value": "Two Pentium Pro processors/node",
          "source": "parallel-asci-red",
          "locator": "pp.5–7"
        },
        "memory": {
          "value": "Private caches; local interleaved ECC DRAM",
          "source": "parallel-asci-red",
          "locator": "pp.5–7"
        },
        "control": {
          "value": "Cougar compute kernel; distributed UNIX services",
          "source": "parallel-asci-red",
          "locator": "p.2"
        },
        "io": {
          "value": "Eagle I/O nodes and two disk subsystems",
          "source": "parallel-asci-red",
          "locator": "pp.5–6"
        },
        "software": {
          "value": "Integrated compute/service environment",
          "source": "parallel-asci-red",
          "locator": "Software overview"
        },
        "workload": {
          "value": "Large scientific simulations",
          "source": "parallel-asci-red",
          "locator": "Introduction"
        }
      },
      "diagram": {
        "title": "Dual-node Kestrel boards and system partitions",
        "scope": "One Kestrel board expanded; mesh and specialized endpoints aggregated.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "p0",
            "label": "Compute-node0 CPUs",
            "subtitle": "DUAL PENTIUM PRO",
            "text": "Runs compute work on node0’s two processors.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-asci-red",
            "locator": "p.5",
            "control": false
          },
          {
            "id": "m0",
            "label": "Node0 memory",
            "subtitle": "INTERLEAVED ECC",
            "text": "Provides node0’s local interleaved ECC memory.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-asci-red",
            "locator": "p.7",
            "control": false
          },
          {
            "id": "n0",
            "label": "Node0 NIC",
            "subtitle": "KESTREL ATTACHMENT",
            "text": "Connects node0 to its mesh-router interface.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-asci-red",
            "locator": "Fig.3",
            "control": false
          },
          {
            "id": "p1",
            "label": "Compute-node1 CPUs/memory",
            "subtitle": "SECOND NODE /BOARD",
            "text": "Groups the second compute node’s processors and memory.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-asci-red",
            "locator": "p.6",
            "control": false
          },
          {
            "id": "n1",
            "label": "Node1 NIC",
            "subtitle": "CHAINED TO NODE0 NIC",
            "text": "Connects node1 independently to the same board router.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-asci-red",
            "locator": "Fig.3",
            "control": false
          },
          {
            "id": "mrc",
            "label": "Mesh Router Chip",
            "subtitle": "ICF BACKPLANE",
            "text": "Routes traffic from two nodes onto the mesh.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-asci-red",
            "locator": "Fig.3",
            "control": false
          },
          {
            "id": "mesh",
            "label": "38×32×2 mesh",
            "subtitle": "SYSTEM COMMUNICATION",
            "text": "Connects the partitioned compute and service resources.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-asci-red",
            "locator": "Table2",
            "control": false
          },
          {
            "id": "service",
            "label": "Service/system nodes",
            "subtitle": "UNIX /BOOT SERVICES",
            "text": "Runs distributed UNIX and system-management services.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-asci-red",
            "locator": "pp.2/6",
            "control": false
          },
          {
            "id": "eagle",
            "label": "Eagle I/O nodes",
            "subtitle": "PCI INTERFACES",
            "text": "Transfers data between the mesh and storage subsystem.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-asci-red",
            "locator": "p.6",
            "control": false
          },
          {
            "id": "disk",
            "label": "Two disk subsystems",
            "subtitle": "SEPARATE END BLOCKS",
            "text": "Provides two independently organized disk subsystems.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-asci-red",
            "locator": "p.5",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "p0",
            "to": "m0",
            "type": "data",
            "source": "parallel-asci-red",
            "locator": "p.7",
            "label": ""
          },
          {
            "from": "m0",
            "to": "p0",
            "type": "data",
            "source": "parallel-asci-red",
            "locator": "p.7",
            "label": ""
          },
          {
            "from": "p0",
            "to": "n0",
            "type": "data",
            "source": "parallel-asci-red",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "p1",
            "to": "n1",
            "type": "data",
            "source": "parallel-asci-red",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "n1",
            "to": "n0",
            "type": "data",
            "source": "parallel-asci-red",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "n0",
            "to": "n1",
            "type": "data",
            "source": "parallel-asci-red",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "n0",
            "to": "mrc",
            "type": "data",
            "source": "parallel-asci-red",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "mrc",
            "to": "mesh",
            "type": "data",
            "source": "parallel-asci-red",
            "locator": "ICF section",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "mrc",
            "type": "data",
            "source": "parallel-asci-red",
            "locator": "ICF section",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "service",
            "type": "data",
            "source": "parallel-asci-red",
            "locator": "Hardware/software overview",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "eagle",
            "type": "data",
            "source": "parallel-asci-red",
            "locator": "Hardware overview",
            "label": ""
          },
          {
            "from": "eagle",
            "to": "disk",
            "type": "data",
            "source": "parallel-asci-red",
            "locator": "Fig.1",
            "label": ""
          }
        ]
      },
      "originalCandidate": "ASCI Red"
    },
    {
      "id": "queue-082",
      "name": "IBM Blue Gene/L —2005 reference system",
      "organization": "IBM",
      "year": 2005,
      "yearLabel": "2005 designer system paper",
      "kind": "Commercial reference architecture",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "distributed",
        "simd",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-bgl"
      ],
      "summary": "Integrated dual-core nodes split point-to-point, collective, barrier, I/O and management communication.",
      "config": "65536-node/512MB-per-node design point in the2005 article; modes remain selectable.",
      "gaps": [
        "No hardware-shared memory between nodes.",
        "Five network roles must not be collapsed into one generic interconnect."
      ],
      "insight": "When is a second core computation and when is it communication support?",
      "fields": {
        "state": {
          "value": "PPC440 integer and double-hummer FP state",
          "source": "parallel-bgl",
          "locator": "ASIC section"
        },
        "compute": {
          "value": "Two PPC440 cores with attached FPUs/node",
          "source": "parallel-bgl",
          "locator": "Fig.5"
        },
        "memory": {
          "value": "4MB eDRAM L3;512MB external memory/node",
          "source": "parallel-bgl",
          "locator": "Memory system overview"
        },
        "control": {
          "value": "Virtual-node or communication-coprocessor mode",
          "source": "parallel-bgl",
          "locator": "System architecture"
        },
        "io": {
          "value": "Collective path to I/O nodes; Gigabit Ethernet externally",
          "source": "parallel-bgl",
          "locator": "Networks/ASIC sections"
        },
        "software": {
          "value": "Small compute kernel; external service hosts",
          "source": "parallel-bgl",
          "locator": "System architecture"
        },
        "workload": {
          "value": "Highly parallel scientific applications",
          "source": "parallel-bgl",
          "locator": "Application-driven design"
        }
      },
      "diagram": {
        "title": "Dual-core chip and specialized system fabrics",
        "scope": "One compute ASIC expanded; only I/O nodes use external Gigabit Ethernet.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "c0",
            "label": "PPC440 core0 +FPU",
            "subtitle": "COMPUTATION",
            "text": "Executes application work with an attached double-hummer FPU.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-bgl",
            "locator": "Fig.5",
            "control": false
          },
          {
            "id": "c1",
            "label": "PPC440 core1 +FPU",
            "subtitle": "COMPUTE OR COMMUNICATION",
            "text": "Runs application or communication work according to node mode.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-bgl",
            "locator": "System architecture",
            "control": false
          },
          {
            "id": "l3",
            "label": "Shared eDRAM L3",
            "subtitle": "4MB",
            "text": "Provides shared on-chip embedded-DRAM cache storage.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-bgl",
            "locator": "Fig.5",
            "control": false
          },
          {
            "id": "ddr",
            "label": "External DDR memory",
            "subtitle": "512MB /NODE",
            "text": "Holds node-local memory beyond the integrated cache.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-bgl",
            "locator": "Memory system overview",
            "control": false
          },
          {
            "id": "torus",
            "label": "3D torus network",
            "subtitle": "POINT-TO-POINT",
            "text": "Carries point-to-point traffic between compute nodes.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-bgl",
            "locator": "Torus network",
            "control": false
          },
          {
            "id": "tree",
            "label": "Collective network",
            "subtitle": "REDUCE /BROADCAST",
            "text": "Performs collectives and compute-to-I/O-node communication.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-bgl",
            "locator": "Collective network",
            "control": false
          },
          {
            "id": "barrier",
            "label": "Global interrupt network",
            "subtitle": "BARRIER /EVENTS",
            "text": "Distributes barrier and interrupt coordination signals.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-bgl",
            "locator": "Global interrupt network",
            "control": true
          },
          {
            "id": "ion",
            "label": "I/O nodes",
            "subtitle": "SERVICE OFFLOAD",
            "text": "Bridges compute resources to external host communication.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-bgl",
            "locator": "System architecture",
            "control": false
          },
          {
            "id": "ether",
            "label": "Gigabit Ethernet /hosts",
            "subtitle": "FILESYSTEM ACCESS",
            "text": "Connects I/O nodes to external service hosts.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-bgl",
            "locator": "Control system networks",
            "control": false
          },
          {
            "id": "mgmt",
            "label": "JTAG /Fast Ethernet",
            "subtitle": "BOOT /DEBUG",
            "text": "Provides separate management and diagnostic access.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-bgl",
            "locator": "Control system networks",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "c0",
            "to": "l3",
            "type": "data",
            "source": "parallel-bgl",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "c1",
            "to": "l3",
            "type": "data",
            "source": "parallel-bgl",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "l3",
            "to": "ddr",
            "type": "data",
            "source": "parallel-bgl",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "ddr",
            "to": "l3",
            "type": "data",
            "source": "parallel-bgl",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "c0",
            "to": "torus",
            "type": "data",
            "source": "parallel-bgl",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "c1",
            "to": "torus",
            "type": "data",
            "source": "parallel-bgl",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "c0",
            "to": "tree",
            "type": "data",
            "source": "parallel-bgl",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "c1",
            "to": "tree",
            "type": "data",
            "source": "parallel-bgl",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "barrier",
            "to": "c0",
            "type": "control",
            "source": "parallel-bgl",
            "locator": "Global interrupt network",
            "label": ""
          },
          {
            "from": "tree",
            "to": "ion",
            "type": "data",
            "source": "parallel-bgl",
            "locator": "Collective network",
            "label": ""
          },
          {
            "from": "ion",
            "to": "ether",
            "type": "data",
            "source": "parallel-bgl",
            "locator": "ASIC section",
            "label": ""
          },
          {
            "from": "mgmt",
            "to": "c0",
            "type": "control",
            "source": "parallel-bgl",
            "locator": "Control system networks",
            "label": ""
          },
          {
            "from": "mgmt",
            "to": "ion",
            "type": "control",
            "source": "parallel-bgl",
            "locator": "Control system networks",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IBM Blue Gene/L"
    },
    {
      "id": "queue-083",
      "name": "IBM Blue Gene/Q —standard16GB compute card",
      "organization": "IBM",
      "year": 2012,
      "yearLabel": "2012 hardware Redbook configuration",
      "kind": "Commercial system building block",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "distributed",
        "smp",
        "simd"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-bgq-hardware",
        "parallel-bgq-development"
      ],
      "summary": "A many-core coherent node joins a5D torus; lightweight compute kernels ship services to Linux I/O nodes.",
      "config": "Standard16GB compute card and2012 system organization; installation/rack count unspecified.",
      "gaps": [
        "On-node shared memory does not extend coherently across the torus."
      ],
      "insight": "Where does coherence stop and function shipping start?",
      "fields": {
        "state": {
          "value": "A2 thread and SIMD state",
          "source": "parallel-bgq-development",
          "locator": "§1.3"
        },
        "compute": {
          "value": "16 application cores; four threads/core",
          "source": "parallel-bgq-development",
          "locator": "§§1.3/2.3"
        },
        "memory": {
          "value": "16GB DDR3;32MB shared L2 and L1P",
          "source": "parallel-bgq-development",
          "locator": "§4.1"
        },
        "control": {
          "value": "CNK compute kernel; Linux I/O nodes",
          "source": "parallel-bgq-development",
          "locator": "§§1.3/2.1"
        },
        "io": {
          "value": "5D torus, I/O nodes and PCIe",
          "source": "parallel-bgq-hardware",
          "locator": "Chapter1"
        },
        "software": {
          "value": "MPI, OpenMP, XL/GNU compilers",
          "source": "parallel-bgq-development",
          "locator": "§1.3"
        },
        "workload": {
          "value": "Parallel scientific applications",
          "source": "parallel-bgq-development",
          "locator": "Chapter1"
        }
      },
      "diagram": {
        "title": "Coherent node hierarchy and off-node services",
        "scope": "A2 cores grouped; L1P is a prefetch/write-combining interface, not the shared L2.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cores",
            "label": "16 application A2 cores",
            "subtitle": "4 THREADS /CORE",
            "text": "Executes application threads on the sixteen active A2 cores.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-bgq-development",
            "locator": "§§1.3/2.3",
            "control": false
          },
          {
            "id": "l1p",
            "label": "Private L1 /L1P",
            "subtitle": "PREFETCH /WRITE COMBINE",
            "text": "Buffers core accesses and supports prefetch/write combining.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-bgq-development",
            "locator": "§4.1.1",
            "control": false
          },
          {
            "id": "switch",
            "label": "On-chip switch",
            "subtitle": "NODE INTERCONNECT",
            "text": "Connects cores,cache banks and network interfaces.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-bgq-development",
            "locator": "§4.1.1",
            "control": false
          },
          {
            "id": "l2",
            "label": "Shared L2",
            "subtitle": "32MB /ATOMIC SUPPORT",
            "text": "Maintains shared coherent storage within one compute node.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-bgq-development",
            "locator": "§§4.1/4.9",
            "control": false
          },
          {
            "id": "mem",
            "label": "External DDR3",
            "subtitle": "16GB /NODE",
            "text": "Provides16GB of external compute-card memory.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-bgq-hardware",
            "locator": "§1.3",
            "control": false
          },
          {
            "id": "cnk",
            "label": "Compute Node Kernel",
            "subtitle": "THREAD /JOB CONTROL",
            "text": "Runs lightweight compute processes and forwards system services.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-bgq-development",
            "locator": "§2.1",
            "control": true
          },
          {
            "id": "torus",
            "label": "5D torus",
            "subtitle": "COMPUTE-NODE LINKS",
            "text": "Carries communication between independent compute nodes.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-bgq-hardware",
            "locator": "Chapter1",
            "control": false
          },
          {
            "id": "io",
            "label": "I/O node:Linux /CIOS",
            "subtitle": "SHIPPED SYSTEM CALLS",
            "text": "Runs Linux/CIOS services for compute-node clients.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-bgq-development",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "external",
            "label": "PCIe /external I/O",
            "subtitle": "FILES /NETWORKS",
            "text": "Connects I/O nodes to storage and other devices.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-bgq-hardware",
            "locator": "Chapter1",
            "control": false
          },
          {
            "id": "rack",
            "label": "Node board /midplane",
            "subtitle": "32 CARDS /BOARD",
            "text": "Groups compute cards into larger system packaging.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-bgq-hardware",
            "locator": "§§1.4–1.5",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cores",
            "to": "l1p",
            "type": "data",
            "source": "parallel-bgq-development",
            "locator": "§4.1.1",
            "label": ""
          },
          {
            "from": "l1p",
            "to": "switch",
            "type": "data",
            "source": "parallel-bgq-development",
            "locator": "§4.1.1",
            "label": ""
          },
          {
            "from": "switch",
            "to": "l2",
            "type": "data",
            "source": "parallel-bgq-development",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "l2",
            "to": "mem",
            "type": "data",
            "source": "parallel-bgq-development",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "mem",
            "to": "l2",
            "type": "data",
            "source": "parallel-bgq-development",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "cnk",
            "to": "cores",
            "type": "control",
            "source": "parallel-bgq-development",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "switch",
            "to": "torus",
            "type": "association",
            "source": "parallel-bgq-development",
            "locator": "§4.1.1",
            "label": ""
          },
          {
            "from": "cnk",
            "to": "torus",
            "type": "control",
            "source": "parallel-bgq-development",
            "locator": "Fig.2-1",
            "label": ""
          },
          {
            "from": "torus",
            "to": "io",
            "type": "data",
            "source": "parallel-bgq-development",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "io",
            "to": "external",
            "type": "data",
            "source": "parallel-bgq-hardware",
            "locator": "Chapter1",
            "label": ""
          },
          {
            "from": "cores",
            "to": "rack",
            "type": "association",
            "source": "parallel-bgq-hardware",
            "locator": "§§1.3–1.5",
            "label": ""
          },
          {
            "from": "rack",
            "to": "torus",
            "type": "association",
            "source": "parallel-bgq-hardware",
            "locator": "§1.4",
            "label": ""
          }
        ]
      },
      "originalCandidate": "IBM Blue Gene/Q"
    },
    {
      "id": "queue-084",
      "name": "SGI Origin2000 —dual-R10000 node organization",
      "organization": "Silicon Graphics",
      "year": 1997,
      "yearLabel": "1997 designer paper",
      "kind": "Commercial reference architecture",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "numa",
        "distributed",
        "risc"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-origin"
      ],
      "summary": "Hub-connected processor nodes maintain global coherence through distributed directories and point-to-point messages.",
      "config": "Dual-R10000 node architecture in the1997 paper; no maximal installation asserted.",
      "gaps": [
        "The shared processor bus is not a snoopy SMP cluster."
      ],
      "insight": "How does a directory request find a dirty owner without global broadcast?",
      "fields": {
        "state": {
          "value": "MIPS registers and private cache state",
          "source": "parallel-origin",
          "locator": "§3"
        },
        "compute": {
          "value": "One/two R10000 processors/node",
          "source": "parallel-origin",
          "locator": "§2"
        },
        "memory": {
          "value": "Node DRAM plus directory memory",
          "source": "parallel-origin",
          "locator": "§2"
        },
        "control": {
          "value": "Directory coherence and page-migration support",
          "source": "parallel-origin",
          "locator": "§§2/3.6"
        },
        "io": {
          "value": "Globally addressable XIO; DMA to all memory",
          "source": "parallel-origin",
          "locator": "§2"
        },
        "software": {
          "value": "OS-managed page placement and migration",
          "source": "parallel-origin",
          "locator": "§3.6"
        },
        "workload": {
          "value": "Shared-memory scientific/throughput workloads",
          "source": "parallel-origin",
          "locator": "§1"
        }
      },
      "diagram": {
        "title": "Directory home, owner intervention, global I/O",
        "scope": "Node0 expanded; remote home/owner are logical roles and may reside in other nodes.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "p0",
            "label": "R10000 CPU0/cache",
            "subtitle": "PRIVATE CACHE",
            "text": "Executes code through private R10000 cache state.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-origin",
            "locator": "§2",
            "control": false
          },
          {
            "id": "p1",
            "label": "R10000 CPU1/cache",
            "subtitle": "PRIVATE CACHE",
            "text": "Provides the second processor/cache attachment to the Hub.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-origin",
            "locator": "§2",
            "control": false
          },
          {
            "id": "hub",
            "label": "Hub ASIC",
            "subtitle": "FOUR-WAY CROSSBAR",
            "text": "Coordinates memory,processor and network coherence requests.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-origin",
            "locator": "§2",
            "control": false
          },
          {
            "id": "mem",
            "label": "Node DRAM/directory",
            "subtitle": "HOME DATA /SHARERS",
            "text": "Stores home data together with directory information.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-origin",
            "locator": "§2",
            "control": false
          },
          {
            "id": "router",
            "label": "SPIDER router",
            "subtitle": "CRAYLINK",
            "text": "Forwards point-to-point traffic between Hub-connected nodes.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-origin",
            "locator": "§3.1",
            "control": false
          },
          {
            "id": "network",
            "label": "Fat-hypercube network",
            "subtitle": "POINT-TO-POINT",
            "text": "Connects distributed homes and cached data owners.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-origin",
            "locator": "§3.1",
            "control": false
          },
          {
            "id": "home",
            "label": "Remote home directory",
            "subtitle": "LOOKUP /FORWARD",
            "text": "Tracks coherence state for a remotely homed line.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-origin",
            "locator": "Read-request flow",
            "control": false
          },
          {
            "id": "owner",
            "label": "Remote owner cache",
            "subtitle": "DIRTY DATA RESPONSE",
            "text": "Supplies a line held by a remote cache owner.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-origin",
            "locator": "Read-request flow",
            "control": false
          },
          {
            "id": "xio",
            "label": "XIO interface/devices",
            "subtitle": "GLOBAL PIO /DMA",
            "text": "Provides globally addressable I/O and DMA access.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-origin",
            "locator": "§2",
            "control": false
          },
          {
            "id": "migrate",
            "label": "Page-migration support",
            "subtitle": "COUNTERS /BLOCK COPY",
            "text": "Supports operating-system-directed page placement changes.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-origin",
            "locator": "§3.6",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "p0",
            "to": "hub",
            "type": "data",
            "source": "parallel-origin",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "p1",
            "to": "hub",
            "type": "data",
            "source": "parallel-origin",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "hub",
            "to": "mem",
            "type": "data",
            "source": "parallel-origin",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "mem",
            "to": "hub",
            "type": "data",
            "source": "parallel-origin",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "hub",
            "to": "router",
            "type": "data",
            "source": "parallel-origin",
            "locator": "§3.1",
            "label": ""
          },
          {
            "from": "router",
            "to": "network",
            "type": "data",
            "source": "parallel-origin",
            "locator": "§3.1",
            "label": ""
          },
          {
            "from": "network",
            "to": "home",
            "type": "data",
            "source": "parallel-origin",
            "locator": "Read-request flow",
            "label": ""
          },
          {
            "from": "home",
            "to": "owner",
            "type": "control",
            "source": "parallel-origin",
            "locator": "Read-request flow",
            "label": "intervention"
          },
          {
            "from": "owner",
            "to": "network",
            "type": "data",
            "source": "parallel-origin",
            "locator": "Read-request flow",
            "label": ""
          },
          {
            "from": "network",
            "to": "router",
            "type": "data",
            "source": "parallel-origin",
            "locator": "Read-request flow",
            "label": ""
          },
          {
            "from": "hub",
            "to": "xio",
            "type": "data",
            "source": "parallel-origin",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "migrate",
            "to": "mem",
            "type": "control",
            "source": "parallel-origin",
            "locator": "§3.6",
            "label": ""
          }
        ]
      },
      "originalCandidate": "SGI Origin 2000"
    },
    {
      "id": "queue-085",
      "name": "Sequent Symmetry2000/200 — 1991 organization",
      "organization": "Sequent Computer Systems",
      "year": 1991,
      "yearLabel": "1991 manufacturer maintenance manual",
      "kind": "Commercial shared-memory reference configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "smp",
        "cisc"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-sequent-s2000"
      ],
      "summary": "A shared pipelined system bus carries data while SLIC separately distributes interrupts and configuration messages.",
      "config": "S2000/200 with80486 processor board,SSM/SSM-I/O and VME peripherals.",
      "gaps": [
        "No exact installed CPU/memory count beyond the illustrated board is asserted.",
        "A named coherence protocol is not reconstructed from the training diagram."
      ],
      "insight": "Why carry interrupts on a separate serial bus?",
      "fields": {
        "state": {
          "value": "32-bit80486 processing;64-bit system data path",
          "source": "parallel-sequent-s2000",
          "locator": "pp.2.12,2.27"
        },
        "compute": {
          "value": "Two CPUs/processor board;512KB cache/CPU",
          "source": "parallel-sequent-s2000",
          "locator": "p.2.12"
        },
        "memory": {
          "value": "MEMC RAM with optional MEMX expansion",
          "source": "parallel-sequent-s2000",
          "locator": "p.2.14"
        },
        "control": {
          "value": "Serial SLIC interrupt/configuration bus",
          "source": "parallel-sequent-s2000",
          "locator": "p.2.29"
        },
        "io": {
          "value": "SSM bridges VME and SCSI",
          "source": "parallel-sequent-s2000",
          "locator": "pp.2.8–2.9,2.30–2.31"
        },
        "software": {
          "value": "DYNIX3.1 or DYNIX/ptx UNIX environment",
          "source": "parallel-sequent-s2000",
          "locator": "p.1.9"
        },
        "workload": {
          "value": "Concurrent multiprocess user processes",
          "source": "parallel-sequent-s2000",
          "locator": "pp.1.5–1.6"
        }
      },
      "diagram": {
        "title": "Shared data bus, separate interrupts, and service processor",
        "scope": "S2000/200 only; SSM2/MULTIBUS components belong to other models.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cpu",
            "label": "80486 processor board",
            "subtitle": "TWO CPU POSITIONS",
            "text": "Executes concurrent UNIX processes.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-sequent-s2000",
            "locator": "p.2.12",
            "control": false
          },
          {
            "id": "cache",
            "label": "Processor caches /CIC",
            "subtitle": "512KB /CPU",
            "text": "Buffers processor data through cache control.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-sequent-s2000",
            "locator": "pp.2.12–2.13",
            "control": false
          },
          {
            "id": "bus",
            "label": "Sequent System Bus",
            "subtitle": "PIPELINED64-BIT DATA",
            "text": "Connects processors,memory and I/O.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-sequent-s2000",
            "locator": "p.2.27",
            "control": false
          },
          {
            "id": "mem",
            "label": "MEMC +optional MEMX",
            "subtitle": "ECC SHARED RAM",
            "text": "Provides shared system memory.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-sequent-s2000",
            "locator": "pp.2.14–2.15",
            "control": false
          },
          {
            "id": "slic",
            "label": "SLIC serial bus",
            "subtitle": "INTERRUPTS /CONFIGURATION",
            "text": "Carries low-level board messages.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-sequent-s2000",
            "locator": "p.2.29",
            "control": true
          },
          {
            "id": "ssm",
            "label": "SSM80386SX /RAM",
            "subtitle": "BOOT /DIAGNOSTICS",
            "text": "Initializes system and provides services.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-sequent-s2000",
            "locator": "pp.2.8–2.9",
            "control": false
          },
          {
            "id": "vme",
            "label": "SSM VME mapping",
            "subtitle": "EXTERNAL I/O BUS",
            "text": "Maps VME access onto system bus.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-sequent-s2000",
            "locator": "pp.2.9,2.31",
            "control": false
          },
          {
            "id": "vdev",
            "label": "VME controllers",
            "subtitle": "ETHERNET /TERMINALS",
            "text": "Serve communication peripherals.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-sequent-s2000",
            "locator": "p.2.4",
            "control": false
          },
          {
            "id": "scsi",
            "label": "SSM SCSI /local I/O",
            "subtitle": "DISK /TAPE /CONSOLE",
            "text": "Connects mass storage and console.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-sequent-s2000",
            "locator": "pp.2.4,2.9",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu",
            "to": "cache",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.13",
            "label": ""
          },
          {
            "from": "cache",
            "to": "cpu",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.13",
            "label": ""
          },
          {
            "from": "cache",
            "to": "bus",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.13",
            "label": ""
          },
          {
            "from": "bus",
            "to": "cache",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.13",
            "label": ""
          },
          {
            "from": "bus",
            "to": "mem",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.4",
            "label": ""
          },
          {
            "from": "mem",
            "to": "bus",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.4",
            "label": ""
          },
          {
            "from": "ssm",
            "to": "bus",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.9",
            "label": ""
          },
          {
            "from": "bus",
            "to": "ssm",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.9",
            "label": ""
          },
          {
            "from": "ssm",
            "to": "slic",
            "type": "control",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.29",
            "label": ""
          },
          {
            "from": "slic",
            "to": "cpu",
            "type": "control",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.13",
            "label": ""
          },
          {
            "from": "slic",
            "to": "mem",
            "type": "control",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.15",
            "label": ""
          },
          {
            "from": "ssm",
            "to": "vme",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.9",
            "label": ""
          },
          {
            "from": "vme",
            "to": "vdev",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.4",
            "label": ""
          },
          {
            "from": "vdev",
            "to": "vme",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.4",
            "label": ""
          },
          {
            "from": "ssm",
            "to": "scsi",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.9",
            "label": ""
          },
          {
            "from": "scsi",
            "to": "ssm",
            "type": "data",
            "source": "parallel-sequent-s2000",
            "locator": "p.2.9",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Sequent Symmetry"
    },
    {
      "id": "queue-086",
      "name": "Kendall Square KSR1 —32-cell experimental ring",
      "organization": "Kendall Square Research /ORNL study",
      "year": 1993,
      "yearLabel": "February1993 experiment configuration",
      "kind": "Measured commercial installation configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "distributed",
        "numa"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-ksr1"
      ],
      "summary": "Cache-only shared storage migrates data among cells; poststore can proactively distribute updated subpages.",
      "config": "The report’s one-ring32-cell system running KSR OS R1.0.5.",
      "gaps": [
        "COMA is distinct from fixed-home NUMA; taxonomy tag describes nonuniform access only.",
        "Higher-ring paths are outside the studied configuration."
      ],
      "insight": "How does shared data move when there is no fixed home DRAM?",
      "fields": {
        "state": {
          "value": "64-bit registers;128-byte shared subpages",
          "source": "parallel-ksr1",
          "locator": "§§2.1–2.2"
        },
        "compute": {
          "value": "32 custom processing cells",
          "source": "parallel-ksr1",
          "locator": "§2.3"
        },
        "memory": {
          "value": "256KB I +256KB D subcaches;32MB local cache/cell",
          "source": "parallel-ksr1",
          "locator": "§2.1"
        },
        "control": {
          "value": "ALLCACHE directory state and optional poststore",
          "source": "parallel-ksr1",
          "locator": "§§1/2.2"
        },
        "io": {
          "value": "XIU supports DMA and programmed I/O",
          "source": "parallel-ksr1",
          "locator": "§2.1"
        },
        "software": {
          "value": "OSF-1/Mach-derived OS and extended pthreads",
          "source": "parallel-ksr1",
          "locator": "§2.3"
        },
        "workload": {
          "value": "Shared-memory reader/writer experiments",
          "source": "parallel-ksr1",
          "locator": "§3"
        }
      },
      "diagram": {
        "title": "Cache-only storage and ring-mediated movement",
        "scope": "One of32 cells expanded. A local cache is the cell’s memory-level storage, not a conventional DRAM home.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "ceu",
            "label": "Co-execution Unit",
            "subtitle": "FETCH /ADDRESS /CONTROL",
            "text": "Coordinates instructions among the cell’s execution resources.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "control": true
          },
          {
            "id": "ipu",
            "label": "Integer Processing Unit",
            "subtitle": "INTEGER /LOGIC",
            "text": "Performs integer operations within one processing cell.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "fpu",
            "label": "Floating Point Unit",
            "subtitle": "FLOATING ARITHMETIC",
            "text": "Performs the cell’s floating-point computation.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "sub",
            "label": "Instruction/data subcaches",
            "subtitle": "256KB EACH",
            "text": "Caches instructions and data close to execution.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "ccu",
            "label": "Cache Control Units",
            "subtitle": "SUBCACHE INTERFACE",
            "text": "Controls access to the larger local cache.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "lc",
            "label": "Local cache/directory",
            "subtitle": "32MB /SUBPAGE STATE",
            "text": "Stores migratory shared subpages and their directory state.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-ksr1",
            "locator": "§§2.1–2.2",
            "control": false
          },
          {
            "id": "ciu",
            "label": "Cell Interconnect Units",
            "subtitle": "RING INTERFACE",
            "text": "Connects the cell’s coherence traffic to Ring:0.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "ring",
            "label": "Ring:0",
            "subtitle": "32 PROCESSING CELLS",
            "text": "Carries searches and subpage transfers among32 cells.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ksr1",
            "locator": "§2.3",
            "control": false
          },
          {
            "id": "other",
            "label": "Other local caches",
            "subtitle": "MIGRATING VALID COPIES",
            "text": "Holds shared subpages currently residing in other cells.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-ksr1",
            "locator": "§§1/2.2",
            "control": false
          },
          {
            "id": "xiu",
            "label": "External I/O Unit",
            "subtitle": "DMA /PROGRAMMED I/O",
            "text": "Provides programmed I/O and DMA connections.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "ceu",
            "to": "ipu",
            "type": "control",
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "ceu",
            "to": "fpu",
            "type": "control",
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "ceu",
            "to": "sub",
            "type": "data",
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "ipu",
            "to": "sub",
            "type": "association",
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "fpu",
            "to": "sub",
            "type": "association",
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "sub",
            "to": "ccu",
            "type": "data",
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "ccu",
            "to": "lc",
            "type": "data",
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "lc",
            "to": "ccu",
            "type": "data",
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "lc",
            "to": "ciu",
            "type": "association",
            "source": "parallel-ksr1",
            "locator": "§§2.1–2.2",
            "label": ""
          },
          {
            "from": "ciu",
            "to": "ring",
            "type": "data",
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "ring",
            "to": "other",
            "type": "data",
            "source": "parallel-ksr1",
            "locator": "§1",
            "label": "fetch /poststore"
          },
          {
            "from": "other",
            "to": "ring",
            "type": "data",
            "source": "parallel-ksr1",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "xiu",
            "to": "ceu",
            "type": "association",
            "source": "parallel-ksr1",
            "locator": "§2.1",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Kendall Square KSR1"
    },
    {
      "id": "queue-087",
      "name": "Stanford DASH —four-cluster prototype",
      "organization": "Stanford University",
      "year": 1992,
      "yearLabel": "March1992 reported prototype",
      "kind": "Built research prototype configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "numa",
        "smp",
        "distributed",
        "risc"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-dash"
      ],
      "summary": "Local snoopy clusters combine with inter-cluster directory coherence and separate request/reply networks.",
      "config": "Four-cluster16-processor prototype used by the article’s running OS; larger64-processor target not implied.",
      "gaps": [
        "Local snooping and global directory control are different coherence levels."
      ],
      "insight": "Which misses stay on a local bus and which enter the directory protocol?",
      "fields": {
        "state": {
          "value": "R3000/R3010 architectural state",
          "source": "parallel-dash",
          "locator": "Prototype cluster"
        },
        "compute": {
          "value": "Four R3000/R3010 pairs per cluster",
          "source": "parallel-dash",
          "locator": "Prototype cluster"
        },
        "memory": {
          "value": "Private caches and distributed shared memory",
          "source": "parallel-dash",
          "locator": "Fig.4"
        },
        "control": {
          "value": "Local MESI; global directory coherence",
          "source": "parallel-dash",
          "locator": "Prototype/coherence sections"
        },
        "io": {
          "value": "I/O resources partitioned across clusters",
          "source": "parallel-dash",
          "locator": "Software support"
        },
        "software": {
          "value": "Modified IRIX; shared-memory programming tools",
          "source": "parallel-dash",
          "locator": "Software support"
        },
        "workload": {
          "value": "Parallel shared-memory applications",
          "source": "parallel-dash",
          "locator": "Performance section"
        }
      },
      "diagram": {
        "title": "Snooping cluster meets distributed directories",
        "scope": "One cluster expanded; remote home/owner roles use request and reply meshes.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cpu",
            "label": "Four R3000/R3010 pairs",
            "subtitle": "PRIVATE L1 CACHES",
            "text": "Executes four processor/FPU streams inside a cluster.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-dash",
            "locator": "Prototype cluster",
            "control": false
          },
          {
            "id": "l2",
            "label": "Four L2 caches",
            "subtitle": "256KB /MESI SNOOP",
            "text": "Caches each processor’s data on the local snooping bus.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-dash",
            "locator": "Prototype cluster",
            "control": false
          },
          {
            "id": "bus",
            "label": "Local MPbus",
            "subtitle": "CLUSTER TRANSACTIONS",
            "text": "Maintains local coherence and connects cluster memory.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-dash",
            "locator": "Prototype cluster",
            "control": false
          },
          {
            "id": "memory",
            "label": "Cluster memory",
            "subtitle": "SHARED ADDRESS SPACE",
            "text": "Holds this cluster’s part of shared memory.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-dash",
            "locator": "Fig.4",
            "control": false
          },
          {
            "id": "dc",
            "label": "Directory Controller",
            "subtitle": "HOME /SHARER STATE",
            "text": "Tracks global sharers for locally homed memory blocks.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-dash",
            "locator": "Fig.5",
            "control": true
          },
          {
            "id": "rc",
            "label": "Reply Controller /RAC",
            "subtitle": "OUTSTANDING REQUESTS",
            "text": "Tracks remote accesses and consumes network replies.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-dash",
            "locator": "Fig.5",
            "control": false
          },
          {
            "id": "pcpu",
            "label": "Pseudo-CPU interface",
            "subtitle": "LOCAL BUS INJECTION",
            "text": "Presents remote requests as local-bus transactions.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-dash",
            "locator": "Fig.5",
            "control": false
          },
          {
            "id": "req",
            "label": "Request mesh",
            "subtitle": "REMOTE REQUESTS",
            "text": "Carries inter-cluster coherence and memory requests.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-dash",
            "locator": "Fig.4",
            "control": false
          },
          {
            "id": "reply",
            "label": "Reply mesh",
            "subtitle": "REMOTE RESPONSES",
            "text": "Returns data and coherence responses separately.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-dash",
            "locator": "Fig.4",
            "control": false
          },
          {
            "id": "remote",
            "label": "Other clusters",
            "subtitle": "DIRECTORY /CACHES",
            "text": "Represents the prototype’s other directory-coherent clusters.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-dash",
            "locator": "Fig.4",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu",
            "to": "l2",
            "type": "data",
            "source": "parallel-dash",
            "locator": "Prototype cluster",
            "label": ""
          },
          {
            "from": "l2",
            "to": "bus",
            "type": "data",
            "source": "parallel-dash",
            "locator": "Prototype cluster",
            "label": ""
          },
          {
            "from": "bus",
            "to": "memory",
            "type": "data",
            "source": "parallel-dash",
            "locator": "Fig.4",
            "label": ""
          },
          {
            "from": "dc",
            "to": "bus",
            "type": "control",
            "source": "parallel-dash",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "bus",
            "to": "rc",
            "type": "data",
            "source": "parallel-dash",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "rc",
            "to": "req",
            "type": "data",
            "source": "parallel-dash",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "req",
            "to": "remote",
            "type": "data",
            "source": "parallel-dash",
            "locator": "Fig.4",
            "label": ""
          },
          {
            "from": "remote",
            "to": "reply",
            "type": "data",
            "source": "parallel-dash",
            "locator": "Fig.4",
            "label": ""
          },
          {
            "from": "reply",
            "to": "rc",
            "type": "data",
            "source": "parallel-dash",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "req",
            "to": "pcpu",
            "type": "control",
            "source": "parallel-dash",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "pcpu",
            "to": "bus",
            "type": "control",
            "source": "parallel-dash",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "dc",
            "to": "reply",
            "type": "data",
            "source": "parallel-dash",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "memory",
            "to": "bus",
            "type": "data",
            "source": "parallel-dash",
            "locator": "Fig.4",
            "label": ""
          }
        ]
      },
      "originalCandidate": "DASH"
    },
    {
      "id": "queue-088",
      "name": "MIT Alewife —32-node first-silicon prototype",
      "organization": "MIT",
      "year": 1995,
      "yearLabel": "ISCA1995 measured configuration",
      "kind": "Built research prototype configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "numa",
        "distributed",
        "risc",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-alewife"
      ],
      "summary": "Shared-memory requests and explicit messages use the same network; software extends limited hardware directory resources.",
      "config": "The32-node first-silicon machine measured in the1995 paper.",
      "gaps": [
        "The measured first silicon runs floating work at20MHz;33MHz was a planned correction."
      ],
      "insight": "When does coherence proceed in hardware and when does software intervene?",
      "fields": {
        "state": {
          "value": "Sparcle SPARC state and hardware contexts",
          "source": "parallel-alewife",
          "locator": "§2.1"
        },
        "compute": {
          "value": "Sparcle plus off-the-shelf FPU/node",
          "source": "parallel-alewife",
          "locator": "§2"
        },
        "memory": {
          "value": "64KB cache;4MB shared data plus directory/private memory",
          "source": "parallel-alewife",
          "locator": "§2"
        },
        "control": {
          "value": "CMMU and LimitLESS software traps",
          "source": "parallel-alewife",
          "locator": "§§1/2"
        },
        "io": {
          "value": "SCSI at mesh edge; host workstation services",
          "source": "parallel-alewife",
          "locator": "§2"
        },
        "software": {
          "value": "Compiler/runtime, synchronization and message handlers",
          "source": "parallel-alewife",
          "locator": "§1"
        },
        "workload": {
          "value": "Fine-grained shared-memory applications",
          "source": "parallel-alewife",
          "locator": "§1"
        }
      },
      "diagram": {
        "title": "Hardware common case, software coherence extension",
        "scope": "CMMU functional roles separated; all off-node communication uses the mesh.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "sparcle",
            "label": "Sparcle processor",
            "subtitle": "MULTIPLE CONTEXTS",
            "text": "Runs SPARC code with latency-tolerating hardware contexts.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-alewife",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "fpu",
            "label": "SPARC-compatible FPU",
            "subtitle": "FLOATING POINT",
            "text": "Executes floating-point instructions alongside Sparcle.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-alewife",
            "locator": "§2",
            "control": false
          },
          {
            "id": "cache",
            "label": "Direct-mapped cache",
            "subtitle": "64KB",
            "text": "Holds64KB of directly mapped processor data.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-alewife",
            "locator": "§2",
            "control": false
          },
          {
            "id": "cohere",
            "label": "CMMU coherence/DRAM",
            "subtitle": "HARDWARE DIRECTORY",
            "text": "Manages local DRAM and shared-memory coherence.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-alewife",
            "locator": "Fig.3",
            "control": false
          },
          {
            "id": "ram",
            "label": "Shared data/directory",
            "subtitle": "4MB DATA /2MB DIR",
            "text": "Stores shared data and associated directory state.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-alewife",
            "locator": "§2",
            "control": false
          },
          {
            "id": "packet",
            "label": "CMMU queues /DMA",
            "subtitle": "EXPLICIT MESSAGES",
            "text": "Buffers packets and performs explicit-message DMA.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-alewife",
            "locator": "Fig.3; §3",
            "control": false
          },
          {
            "id": "handler",
            "label": "LimitLESS handlers",
            "subtitle": "SOFTWARE EXTENSION",
            "text": "Extends limited hardware directory entries through software.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-alewife",
            "locator": "§1",
            "control": true
          },
          {
            "id": "router",
            "label": "Elko mesh router",
            "subtitle": "WORMHOLE ROUTING",
            "text": "Routes shared-memory and message traffic across the mesh.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-alewife",
            "locator": "§2",
            "control": false
          },
          {
            "id": "mesh",
            "label": "Other mesh nodes",
            "subtitle": "SHARED MEMORY /MESSAGES",
            "text": "Connects the other nodes in the32-node prototype.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-alewife",
            "locator": "§2",
            "control": false
          },
          {
            "id": "io",
            "label": "Mesh-edge SCSI /host",
            "subtitle": "FILES /CLIENT ACCESS",
            "text": "Attaches SCSI and host services at mesh edges.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-alewife",
            "locator": "§2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "sparcle",
            "to": "fpu",
            "type": "association",
            "source": "parallel-alewife",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "sparcle",
            "to": "cache",
            "type": "data",
            "source": "parallel-alewife",
            "locator": "Fig.1",
            "label": ""
          },
          {
            "from": "cache",
            "to": "cohere",
            "type": "data",
            "source": "parallel-alewife",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "cohere",
            "to": "ram",
            "type": "data",
            "source": "parallel-alewife",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "cohere",
            "to": "router",
            "type": "data",
            "source": "parallel-alewife",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "sparcle",
            "to": "packet",
            "type": "data",
            "source": "parallel-alewife",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "packet",
            "to": "router",
            "type": "data",
            "source": "parallel-alewife",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "router",
            "to": "mesh",
            "type": "data",
            "source": "parallel-alewife",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "router",
            "type": "data",
            "source": "parallel-alewife",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "cohere",
            "to": "handler",
            "type": "control",
            "source": "parallel-alewife",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "handler",
            "to": "packet",
            "type": "data",
            "source": "parallel-alewife",
            "locator": "§1",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "io",
            "type": "data",
            "source": "parallel-alewife",
            "locator": "§2",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Alewife"
    },
    {
      "id": "queue-089",
      "name": "Beowulf —original16-node DX4 workstation",
      "organization": "NASA CESDIS /collaborators",
      "year": 1995,
      "yearLabel": "1995 prototype architecture report",
      "kind": "Built research cluster configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "distributed"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-beowulf"
      ],
      "summary": "Commodity PCs share two Ethernet channels while retaining local computation, memory, and disks.",
      "config": "Original16-node100MHz DX4 system; later Pentium/Fast Ethernet generation excluded.",
      "gaps": [
        "Beowulf is also a cluster class; this record covers the original prototype only."
      ],
      "insight": "Why stripe packets across two networks instead of adding shared memory?",
      "fields": {
        "state": {
          "value": "486DX4 local architectural state",
          "source": "parallel-beowulf",
          "locator": "Beowulf Architecture"
        },
        "compute": {
          "value": "16 DX4 processors",
          "source": "parallel-beowulf",
          "locator": "Beowulf Architecture"
        },
        "memory": {
          "value": "16MB DRAM/node;256KB secondary cache",
          "source": "parallel-beowulf",
          "locator": "Beowulf Architecture"
        },
        "control": {
          "value": "Linux kernel distributes packets over both channels",
          "source": "parallel-beowulf",
          "locator": "Introduction"
        },
        "io": {
          "value": "Local disk/controller per node; external LAN ports",
          "source": "parallel-beowulf",
          "locator": "Beowulf Architecture"
        },
        "software": {
          "value": "Linux and PVM; MPI port planned",
          "source": "parallel-beowulf",
          "locator": "Software; conclusions"
        },
        "workload": {
          "value": "CFD and gravitational N-body simulation",
          "source": "parallel-beowulf",
          "locator": "Applications"
        }
      },
      "diagram": {
        "title": "Local storage and two channel-bonded Ethernet fabrics",
        "scope": "Two example nodes expanded; remaining14 nodes use the same two communication channels.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cpu0",
            "label": "Node0 DX4/cache",
            "subtitle": "LOCAL COMPUTATION",
            "text": "Runs node0’s local computation on a DX4.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "control": false
          },
          {
            "id": "mem0",
            "label": "Node0 DRAM/disk",
            "subtitle": "16MB /LOCAL CONTROLLER",
            "text": "Provides private RAM and disk storage for node0.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "control": false
          },
          {
            "id": "linux0",
            "label": "Node0 Linux networking",
            "subtitle": "PACKET DISTRIBUTION",
            "text": "Distributes messages over the two Ethernet channels.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-beowulf",
            "locator": "Introduction",
            "control": true
          },
          {
            "id": "hub",
            "label": "Ethernet channelA",
            "subtitle": "TWISTED-PAIR HUB",
            "text": "Carries one independent shared Ethernet communication channel.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "control": false
          },
          {
            "id": "thin",
            "label": "Ethernet channelB",
            "subtitle": "MULTIDROP THIN-NET",
            "text": "Provides the second Ethernet channel for parallel traffic.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "control": false
          },
          {
            "id": "cpu1",
            "label": "Node1 DX4/cache",
            "subtitle": "LOCAL COMPUTATION",
            "text": "Runs node1 independently of the other PCs.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "control": false
          },
          {
            "id": "mem1",
            "label": "Node1 DRAM/disk",
            "subtitle": "LOCAL STORAGE",
            "text": "Provides node1’s private working storage.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "control": false
          },
          {
            "id": "linux1",
            "label": "Node1 Linux networking",
            "subtitle": "PACKET DISTRIBUTION",
            "text": "Runs Linux/PVM communication for node1.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-beowulf",
            "locator": "Introduction",
            "control": true
          },
          {
            "id": "rest",
            "label": "Nodes2–15",
            "subtitle": "SAME DUAL CHANNELS",
            "text": "Represents fourteen similarly configured PCs.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "control": false
          },
          {
            "id": "access",
            "label": "External LAN/display",
            "subtitle": "SELECTED NODES",
            "text": "Provides external access and system display connections.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu0",
            "to": "mem0",
            "type": "data",
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "label": ""
          },
          {
            "from": "cpu0",
            "to": "linux0",
            "type": "association",
            "source": "parallel-beowulf",
            "locator": "Introduction",
            "label": ""
          },
          {
            "from": "linux0",
            "to": "hub",
            "type": "data",
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "label": ""
          },
          {
            "from": "linux0",
            "to": "thin",
            "type": "data",
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "label": ""
          },
          {
            "from": "hub",
            "to": "linux1",
            "type": "data",
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "label": ""
          },
          {
            "from": "thin",
            "to": "linux1",
            "type": "data",
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "label": ""
          },
          {
            "from": "linux1",
            "to": "cpu1",
            "type": "association",
            "source": "parallel-beowulf",
            "locator": "Introduction",
            "label": ""
          },
          {
            "from": "cpu1",
            "to": "mem1",
            "type": "data",
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "label": ""
          },
          {
            "from": "hub",
            "to": "rest",
            "type": "data",
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "label": ""
          },
          {
            "from": "thin",
            "to": "rest",
            "type": "data",
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "label": ""
          },
          {
            "from": "rest",
            "to": "hub",
            "type": "data",
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "label": ""
          },
          {
            "from": "access",
            "to": "cpu0",
            "type": "association",
            "source": "parallel-beowulf",
            "locator": "Beowulf Architecture",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Beowulf cluster"
    },
    {
      "id": "queue-090",
      "name": "Summit —standard AC922 compute node",
      "organization": "ORNL /IBM /NVIDIA",
      "year": 2024,
      "yearLabel": "Guide archived after November2024 retirement",
      "kind": "Built supercomputer configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "heterogeneous",
        "distributed",
        "mimd",
        "simt",
        "numa"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-summit"
      ],
      "summary": "Two POWER9 domains each attach three NVLink-connected GPUs, while InfiniBand links nodes.",
      "config": "Standard512GB DDR4/96GB HBM2 node in the archived guide; high-memory nodes excluded.",
      "gaps": [
        "The archive reflects later software/storage revisions."
      ],
      "insight": "Which data movement remains within a three-GPU domain?",
      "fields": {
        "state": {
          "value": "POWER9 CPU and V100 GPU state",
          "source": "parallel-summit",
          "locator": "Summit Nodes; GPUs"
        },
        "compute": {
          "value": "Two22-core POWER9 CPUs and six V100s/node",
          "source": "parallel-summit",
          "locator": "Summit Nodes"
        },
        "memory": {
          "value": "512GB DDR4;16GB HBM2/GPU",
          "source": "parallel-summit",
          "locator": "Summit Nodes"
        },
        "control": {
          "value": "Login/launch/compute roles; jsrun",
          "source": "parallel-summit",
          "locator": "Node Types"
        },
        "io": {
          "value": "Dual-rail EDR fat-tree and node NVMe",
          "source": "parallel-summit",
          "locator": "Interconnect; Data and Storage"
        },
        "software": {
          "value": "RHEL8.2 and GPU/MPI programming tools",
          "source": "parallel-summit",
          "locator": "OS; Shell and Programming"
        },
        "workload": {
          "value": "Scientific simulation and deep learning",
          "source": "parallel-summit",
          "locator": "System Overview"
        }
      },
      "diagram": {
        "title": "Two CPU/GPU locality domains and shared network access",
        "scope": "Each three-GPU triangle is grouped; no all-to-all NVLink connection across CPU domains is implied.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cpu0",
            "label": "POWER9 CPU0",
            "subtitle": "22 CORES",
            "text": "Hosts one POWER9 domain and three attached GPUs.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "control": false
          },
          {
            "id": "cpu1",
            "label": "POWER9 CPU1",
            "subtitle": "22 CORES",
            "text": "Hosts the second CPU/GPU affinity domain.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "control": false
          },
          {
            "id": "dram0",
            "label": "CPU0 DDR4",
            "subtitle": "256GB",
            "text": "Supplies CPU0’s share of node DDR4 memory.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "control": false
          },
          {
            "id": "dram1",
            "label": "CPU1 DDR4",
            "subtitle": "256GB",
            "text": "Supplies CPU1’s share of node DDR4 memory.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "control": false
          },
          {
            "id": "g0",
            "label": "V100 GPUs0–2",
            "subtitle": "NVLINK TRIANGLE",
            "text": "Groups the three GPUs in CPU0’s NVLink triangle.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "control": false
          },
          {
            "id": "g1",
            "label": "V100 GPUs3–5",
            "subtitle": "NVLINK TRIANGLE",
            "text": "Groups the three GPUs in CPU1’s NVLink triangle.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "control": false
          },
          {
            "id": "h0",
            "label": "GPU-domain0 HBM2",
            "subtitle": "3 ×16GB",
            "text": "Provides private HBM2 for the first three GPUs.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "control": false
          },
          {
            "id": "h1",
            "label": "GPU-domain1 HBM2",
            "subtitle": "3 ×16GB",
            "text": "Provides private HBM2 for the second three GPUs.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "control": false
          },
          {
            "id": "nic",
            "label": "Dual-rail EDR NIC",
            "subtitle": "PCIe TO BOTH CPUs",
            "text": "Connects CPU domains to the dual-rail EDR fabric.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "control": false
          },
          {
            "id": "net",
            "label": "InfiniBand fat tree",
            "subtitle": "OTHER COMPUTE NODES",
            "text": "Carries inter-node traffic through the system fat-tree.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-summit",
            "locator": "System Interconnect",
            "control": false
          },
          {
            "id": "nvme",
            "label": "Node NVMe",
            "subtitle": "1.6TB BURST BUFFER",
            "text": "Provides node-local fast storage.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu0",
            "to": "cpu1",
            "type": "data",
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "label": "X-Bus"
          },
          {
            "from": "cpu0",
            "to": "dram0",
            "type": "data",
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "label": ""
          },
          {
            "from": "cpu1",
            "to": "dram1",
            "type": "data",
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "label": ""
          },
          {
            "from": "cpu0",
            "to": "g0",
            "type": "data",
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "label": "NVLink"
          },
          {
            "from": "cpu1",
            "to": "g1",
            "type": "data",
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "label": "NVLink"
          },
          {
            "from": "g0",
            "to": "h0",
            "type": "data",
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "label": ""
          },
          {
            "from": "g1",
            "to": "h1",
            "type": "data",
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "label": ""
          },
          {
            "from": "cpu0",
            "to": "nic",
            "type": "data",
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "label": "PCIe"
          },
          {
            "from": "cpu1",
            "to": "nic",
            "type": "data",
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "label": "PCIe"
          },
          {
            "from": "nic",
            "to": "net",
            "type": "data",
            "source": "parallel-summit",
            "locator": "System Interconnect",
            "label": ""
          },
          {
            "from": "net",
            "to": "nic",
            "type": "data",
            "source": "parallel-summit",
            "locator": "System Interconnect",
            "label": ""
          },
          {
            "from": "cpu1",
            "to": "nvme",
            "type": "data",
            "source": "parallel-summit",
            "locator": "Node architecture figure",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Summit"
    },
    {
      "id": "queue-091",
      "name": "Frontier —MI250X compute-node organization",
      "organization": "ORNL /HPE /AMD",
      "year": null,
      "yearLabel": "Operator-guide snapshot,November2026",
      "kind": "Built supercomputer configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "heterogeneous",
        "distributed",
        "mimd",
        "simt",
        "numa"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-frontier"
      ],
      "summary": "Four dual-die GPU packages appear as eight GPUs, with explicit CPU affinity and direct network paths.",
      "config": "The guide’s64-core EPYC/four-MI250X node; launch and software revisions are not conflated.",
      "gaps": [
        "Package count and software-visible GPU count differ."
      ],
      "insight": "Why does a four-accelerator node expose eight GPU devices?",
      "fields": {
        "state": {
          "value": "EPYC and CDNA2 GCD state",
          "source": "parallel-frontier",
          "locator": "Compute Nodes"
        },
        "compute": {
          "value": "One64-core CPU; four MI250X/eight GCDs",
          "source": "parallel-frontier",
          "locator": "Compute Nodes"
        },
        "memory": {
          "value": "512GB DDR4;64GB HBM2E/GCD",
          "source": "parallel-frontier",
          "locator": "Compute Nodes"
        },
        "control": {
          "value": "Slurm placement across CPU NUMA/GPU affinity",
          "source": "parallel-frontier",
          "locator": "Compute Nodes"
        },
        "io": {
          "value": "Four Slingshot NICs; local NVMe",
          "source": "parallel-frontier",
          "locator": "Interconnect; File Systems"
        },
        "software": {
          "value": "Cray OS; ROCm/HIP/MPI environment",
          "source": "parallel-frontier",
          "locator": "OS; programming sections"
        },
        "workload": {
          "value": "Accelerated scientific computation",
          "source": "parallel-frontier",
          "locator": "System Overview"
        }
      },
      "diagram": {
        "title": "One MI250X expanded within the eight-GCD node",
        "scope": "GCD0/1 are one package; remaining interpackage Infinity Fabric paths are aggregated.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cpu",
            "label": "Optimized EPYC CPU",
            "subtitle": "64 CORES /4 NUMA",
            "text": "Runs host work and controls accelerator placement.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-frontier",
            "locator": "Compute Nodes",
            "control": false
          },
          {
            "id": "dram",
            "label": "CPU DDR4",
            "subtitle": "512GB",
            "text": "Provides the CPU’s local DDR4 memory.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-frontier",
            "locator": "Compute Nodes",
            "control": false
          },
          {
            "id": "g0",
            "label": "MI250X:GCD0",
            "subtitle": "GPU DEVICE0",
            "text": "Acts as one software-visible GPU in an MI250X.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "control": false
          },
          {
            "id": "g1",
            "label": "MI250X:GCD1",
            "subtitle": "GPU DEVICE1",
            "text": "Acts as the package’s second software-visible GPU.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "control": false
          },
          {
            "id": "h0",
            "label": "GCD0 HBM2E",
            "subtitle": "64GB",
            "text": "Provides64GB of HBM2E local to GCD0.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "control": false
          },
          {
            "id": "h1",
            "label": "GCD1 HBM2E",
            "subtitle": "64GB",
            "text": "Provides64GB of HBM2E local to GCD1.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "control": false
          },
          {
            "id": "other",
            "label": "Other three MI250Xs",
            "subtitle": "SIX MORE GCDs",
            "text": "Adds six GCDs across three further packages.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-frontier",
            "locator": "Compute Nodes",
            "control": false
          },
          {
            "id": "fabric",
            "label": "Interpackage IF paths",
            "subtitle": "SELECTED GCD PEERS",
            "text": "Connects accelerator packages through Infinity Fabric paths.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "control": false
          },
          {
            "id": "nic",
            "label": "Four Slingshot NICs",
            "subtitle": "ONE DIRECT PATH /PAIR",
            "text": "Supplies four direct node-to-Slingshot network interfaces.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "control": false
          },
          {
            "id": "net",
            "label": "Slingshot system fabric",
            "subtitle": "INTER-NODE MESSAGES",
            "text": "Connects compute nodes through the system fabric.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-frontier",
            "locator": "System Interconnect",
            "control": false
          },
          {
            "id": "nvme",
            "label": "Local NVMe pair",
            "subtitle": "NODE STORAGE",
            "text": "Provides node-local temporary storage.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-frontier",
            "locator": "File Systems",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu",
            "to": "dram",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "Compute Nodes",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "g0",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "label": "CPU–GPU IF"
          },
          {
            "from": "cpu",
            "to": "g1",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "label": "CPU–GPU IF"
          },
          {
            "from": "g0",
            "to": "g1",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "label": "in-package IF"
          },
          {
            "from": "g1",
            "to": "g0",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "label": ""
          },
          {
            "from": "g0",
            "to": "h0",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "label": ""
          },
          {
            "from": "g1",
            "to": "h1",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "label": ""
          },
          {
            "from": "g0",
            "to": "fabric",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "label": ""
          },
          {
            "from": "fabric",
            "to": "other",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "label": ""
          },
          {
            "from": "g1",
            "to": "nic",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "label": "PCIe"
          },
          {
            "from": "other",
            "to": "nic",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "label": ""
          },
          {
            "from": "nic",
            "to": "net",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "System Interconnect",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "nvme",
            "type": "data",
            "source": "parallel-frontier",
            "locator": "Node diagram",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Frontier"
    },
    {
      "id": "queue-092",
      "name": "Aurora —Xeon Max/Max1550 compute node",
      "organization": "Argonne /HPE /Intel",
      "year": 2025,
      "yearLabel": "February2025 operator hardware revision",
      "kind": "Built supercomputer configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "heterogeneous",
        "distributed",
        "mimd",
        "simd",
        "numa"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-aurora-system",
        "parallel-aurora-pe"
      ],
      "summary": "HBM-equipped CPUs and six XeLink-connected GPUs feed a Slingshot Dragonfly fabric.",
      "config": "Dual9470C/six1550 node in the February2025 machine overview.",
      "gaps": [
        "Physical and active Xe-unit counts are not reconciled in the operator’s summary table."
      ],
      "insight": "Which memory is CPU-attached and which belongs to GPU tiles?",
      "fields": {
        "state": {
          "value": "Xeon CPU and Xe vector/matrix state",
          "source": "parallel-aurora-system",
          "locator": "Machine overview"
        },
        "compute": {
          "value": "Two52-core CPUs; six Max1550 GPUs",
          "source": "parallel-aurora-system",
          "locator": "Compute Node table"
        },
        "memory": {
          "value": "CPU:2×64GiB HBM +2×512GiB DDR5; GPU:768GiB HBM",
          "source": "parallel-aurora-system",
          "locator": "Compute Node table"
        },
        "control": {
          "value": "Host execution and GPU offload",
          "source": "parallel-aurora-system",
          "locator": "Machine overview"
        },
        "io": {
          "value": "Eight Slingshot11 NICs; Dragonfly",
          "source": "parallel-aurora-system",
          "locator": "Machine overview"
        },
        "software": {
          "value": "oneAPI SDK, MPICH and Spack PE",
          "source": "parallel-aurora-pe",
          "locator": "Overview"
        },
        "workload": {
          "value": "Scientific simulation and accelerated applications",
          "source": "parallel-aurora-system",
          "locator": "Machine overview"
        }
      },
      "diagram": {
        "title": "CPU HBM domains, GPU all-to-all, direct network I/O",
        "scope": "Three GPUs per group are aggregated; XeLink represents the documented six-GPU all-to-all network.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cpu0",
            "label": "Xeon Max CPU0",
            "subtitle": "52 CORES",
            "text": "Runs one host CPU/socket affinity domain.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-system",
            "locator": "Compute Node table",
            "control": false
          },
          {
            "id": "cpu1",
            "label": "Xeon Max CPU1",
            "subtitle": "52 CORES",
            "text": "Runs the second host CPU/socket affinity domain.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-system",
            "locator": "Compute Node table",
            "control": false
          },
          {
            "id": "cm0",
            "label": "CPU0 HBM /DDR5",
            "subtitle": "64GiB /512GiB",
            "text": "Combines CPU0’s HBM capacity with attached DDR5.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-system",
            "locator": "Compute Node table",
            "control": false
          },
          {
            "id": "cm1",
            "label": "CPU1 HBM /DDR5",
            "subtitle": "64GiB /512GiB",
            "text": "Combines CPU1’s HBM capacity with attached DDR5.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-system",
            "locator": "Compute Node table",
            "control": false
          },
          {
            "id": "g0",
            "label": "Max1550 GPUs0–2",
            "subtitle": "VECTOR /MATRIX ENGINES",
            "text": "Groups three of the node’s six Max1550 GPUs.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "control": false
          },
          {
            "id": "g1",
            "label": "Max1550 GPUs3–5",
            "subtitle": "VECTOR /MATRIX ENGINES",
            "text": "Groups the other three Max1550 GPUs.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "control": false
          },
          {
            "id": "hbm",
            "label": "GPU HBM2E",
            "subtitle": "768GiB /NODE",
            "text": "Supplies GPU-local HBM2E across the six accelerators.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-system",
            "locator": "Compute Node table",
            "control": false
          },
          {
            "id": "xe",
            "label": "XeLink fabric",
            "subtitle": "SIX-GPU ALL-TO-ALL",
            "text": "Connects all six GPUs through the XeLink fabric.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "control": false
          },
          {
            "id": "nic",
            "label": "Eight Slingshot NICs",
            "subtitle": "DIRECT GPU PCIe",
            "text": "Provides eight Slingshot network interfaces per node.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "control": false
          },
          {
            "id": "net",
            "label": "Dragonfly system fabric",
            "subtitle": "10624 COMPUTE NODES",
            "text": "Carries inter-node communication in a Dragonfly topology.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cpu0",
            "to": "cm0",
            "type": "data",
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "label": ""
          },
          {
            "from": "cpu1",
            "to": "cm1",
            "type": "data",
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "label": ""
          },
          {
            "from": "cpu0",
            "to": "g0",
            "type": "association",
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "label": ""
          },
          {
            "from": "cpu1",
            "to": "g1",
            "type": "association",
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "label": ""
          },
          {
            "from": "g0",
            "to": "xe",
            "type": "data",
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "label": ""
          },
          {
            "from": "xe",
            "to": "g1",
            "type": "data",
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "label": ""
          },
          {
            "from": "g1",
            "to": "xe",
            "type": "data",
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "label": ""
          },
          {
            "from": "xe",
            "to": "g0",
            "type": "data",
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "label": ""
          },
          {
            "from": "g0",
            "to": "hbm",
            "type": "data",
            "source": "parallel-aurora-system",
            "locator": "Compute Node table",
            "label": ""
          },
          {
            "from": "g1",
            "to": "hbm",
            "type": "data",
            "source": "parallel-aurora-system",
            "locator": "Compute Node table",
            "label": ""
          },
          {
            "from": "g0",
            "to": "nic",
            "type": "data",
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "label": "PCIe messaging"
          },
          {
            "from": "g1",
            "to": "nic",
            "type": "data",
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "label": "PCIe messaging"
          },
          {
            "from": "nic",
            "to": "net",
            "type": "data",
            "source": "parallel-aurora-system",
            "locator": "Machine overview",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Aurora"
    },
    {
      "id": "queue-093",
      "name": "El Capitan —four-MI300A node",
      "organization": "LLNL /HPE /AMD",
      "year": 2024,
      "yearLabel": "2024 commissioning; operator node specification",
      "kind": "Built supercomputer configuration",
      "status": "dossier",
      "track": "super",
      "trackName": "Vector & large parallel machines",
      "discoveryParadigms": [
        "digital",
        "parallel"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "heterogeneous",
        "distributed",
        "mimd",
        "simt",
        "numa"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-elcap-hardware",
        "parallel-elcap-installation"
      ],
      "summary": "CPU and GPU chiplets share each APU’s HBM3, with four NUMA sockets linked in a fully connected node.",
      "config": "FourMI300A/512GiB compute node; queue counts and software revision are separate operational facts.",
      "gaps": [
        "Unified addressability does not erase cross-socket GPU coherence rules."
      ],
      "insight": "What copying disappears inside an APU, and where does coherence change?",
      "fields": {
        "state": {
          "value": "CPU and CDNA3 GPU state",
          "source": "parallel-elcap-hardware",
          "locator": "APU description"
        },
        "compute": {
          "value": "96 CPU cores and four MI300A GPUs/node",
          "source": "parallel-elcap-installation",
          "locator": "Platform table"
        },
        "memory": {
          "value": "128GB unified HBM3/APU;512GB/node",
          "source": "parallel-elcap-hardware",
          "locator": "APU/node description"
        },
        "control": {
          "value": "Hardware coherence within socket; software GPU coherence across sockets",
          "source": "parallel-elcap-hardware",
          "locator": "APU description"
        },
        "io": {
          "value": "Four Slingshot interfaces; near-node storage",
          "source": "parallel-elcap-hardware",
          "locator": "Node diagram; System Interconnect"
        },
        "software": {
          "value": "TOSS4, Cray compilers and Flux",
          "source": "parallel-elcap-installation",
          "locator": "System description"
        },
        "workload": {
          "value": "Large-scale scientific simulation",
          "source": "parallel-elcap-installation",
          "locator": "Platform overview"
        }
      },
      "diagram": {
        "title": "Shared-memory APU and four-socket NUMA system",
        "scope": "APU0 expanded; three peers aggregated. Direct CPU/GPU load-store access targets the same HBM.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "ccd",
            "label": "APU0 CPU chiplets",
            "subtitle": "THREE CCDs",
            "text": "Runs CPU code against the APU’s shared HBM.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-elcap-hardware",
            "locator": "APU description",
            "control": false
          },
          {
            "id": "xcd",
            "label": "APU0 GPU chiplets",
            "subtitle": "SIX XCDs",
            "text": "Runs GPU kernels against the same APU memory.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-elcap-hardware",
            "locator": "APU description",
            "control": false
          },
          {
            "id": "if",
            "label": "APU0 Infinity Fabric",
            "subtitle": "HETEROGENEOUS PACKAGE",
            "text": "Connects CPU,GPU and I/O chiplets inside the APU.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-elcap-hardware",
            "locator": "APU description",
            "control": false
          },
          {
            "id": "cache",
            "label": "Infinity Cache /IODs",
            "subtitle": "MEMORY-SIDE CACHE",
            "text": "Provides on-package cache and memory-controller resources.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-elcap-hardware",
            "locator": "Memory description",
            "control": false
          },
          {
            "id": "hbm",
            "label": "APU0 HBM3",
            "subtitle": "128GB SHARED",
            "text": "Supplies128GB of CPU/GPU unified memory per APU.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-elcap-hardware",
            "locator": "APU/node description",
            "control": false
          },
          {
            "id": "peers",
            "label": "APUs1–3",
            "subtitle": "THREE MORE NUMA SOCKETS",
            "text": "Adds three fully connected NUMA APU sockets.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-elcap-hardware",
            "locator": "Node description",
            "control": false
          },
          {
            "id": "gpucoh",
            "label": "Cross-socket GPU rules",
            "subtitle": "SOFTWARE COHERENCE",
            "text": "Identifies software-managed coherence across GPU sockets.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-elcap-hardware",
            "locator": "APU description",
            "control": true
          },
          {
            "id": "nic",
            "label": "Four Slingshot NICs",
            "subtitle": "PCIe ATTACHMENT",
            "text": "Provides one Slingshot interface per APU.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-elcap-hardware",
            "locator": "Node diagram",
            "control": false
          },
          {
            "id": "net",
            "label": "Dragonfly interconnect",
            "subtitle": "SYSTEM COMMUNICATION",
            "text": "Carries inter-node traffic through Dragonfly routing.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-elcap-hardware",
            "locator": "System Interconnect",
            "control": false
          },
          {
            "id": "storage",
            "label": "Near-node local storage",
            "subtitle": "NODE STORAGE PATH",
            "text": "Provides the documented near-node local storage tier.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-elcap-hardware",
            "locator": "Node diagram",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "ccd",
            "to": "if",
            "type": "data",
            "source": "parallel-elcap-hardware",
            "locator": "APU description",
            "label": ""
          },
          {
            "from": "xcd",
            "to": "if",
            "type": "data",
            "source": "parallel-elcap-hardware",
            "locator": "APU description",
            "label": ""
          },
          {
            "from": "if",
            "to": "cache",
            "type": "data",
            "source": "parallel-elcap-hardware",
            "locator": "Memory description",
            "label": ""
          },
          {
            "from": "cache",
            "to": "hbm",
            "type": "data",
            "source": "parallel-elcap-hardware",
            "locator": "Memory description",
            "label": ""
          },
          {
            "from": "hbm",
            "to": "cache",
            "type": "data",
            "source": "parallel-elcap-hardware",
            "locator": "Memory description",
            "label": ""
          },
          {
            "from": "if",
            "to": "peers",
            "type": "data",
            "source": "parallel-elcap-hardware",
            "locator": "Node description",
            "label": "inter-APU IF"
          },
          {
            "from": "peers",
            "to": "if",
            "type": "data",
            "source": "parallel-elcap-hardware",
            "locator": "Node description",
            "label": ""
          },
          {
            "from": "gpucoh",
            "to": "xcd",
            "type": "association",
            "source": "parallel-elcap-hardware",
            "locator": "APU description",
            "label": ""
          },
          {
            "from": "gpucoh",
            "to": "peers",
            "type": "association",
            "source": "parallel-elcap-hardware",
            "locator": "APU description",
            "label": ""
          },
          {
            "from": "if",
            "to": "nic",
            "type": "data",
            "source": "parallel-elcap-hardware",
            "locator": "Node diagram",
            "label": ""
          },
          {
            "from": "nic",
            "to": "net",
            "type": "data",
            "source": "parallel-elcap-hardware",
            "locator": "System Interconnect",
            "label": ""
          },
          {
            "from": "if",
            "to": "storage",
            "type": "data",
            "source": "parallel-elcap-hardware",
            "locator": "Node diagram",
            "label": ""
          }
        ]
      },
      "originalCandidate": "El Capitan"
    },
    {
      "id": "queue-094",
      "name": "MIT TTDA — 1990 architectural model",
      "organization": "MIT Laboratory for Computer Science",
      "year": 1990,
      "yearLabel": "March1990 designer paper",
      "kind": "Architectural model",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "architectures": [
        "dataflow-arch",
        "distributed",
        "mimd",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "parallel-ttda"
      ],
      "summary": "Tagged operands rendezvous before instruction fetch; separate I-structure units defer reads until a value exists.",
      "config": "The1990 paper’s n-cube TTDA model; physical packaging and processor count are unspecified.",
      "gaps": [
        "This record describes an architecture rather than claiming a fabricated TTDA installation.",
        "The hash matcher implementation and n-cube size are intentionally unspecified."
      ],
      "insight": "What state identifies one dynamic invocation of a dataflow instruction?",
      "fields": {
        "state": {
          "value": "Tokens contain a value and invocation/instruction tag",
          "source": "parallel-ttda",
          "locator": "§III-B; §IV-B"
        },
        "compute": {
          "value": "PE pipeline: match, fetch, ALU/tag computation, token formation",
          "source": "parallel-ttda",
          "locator": "§IV-B, Fig.18"
        },
        "memory": {
          "value": "Program/constants plus globally addressed I-structure storage",
          "source": "parallel-ttda",
          "locator": "§§III-C,IV-A–C"
        },
        "control": {
          "value": "Operand availability fires instructions; control tokens initialize PE state",
          "source": "parallel-ttda",
          "locator": "§IV-B.2–3"
        },
        "io": {
          "value": "External channels belong to the control section",
          "source": "parallel-ttda",
          "locator": "§IV-B.3"
        },
        "software": {
          "value": "Id programs compile to basic dataflow code blocks",
          "source": "parallel-ttda",
          "locator": "§IV introduction"
        },
        "workload": {
          "value": "Parallel loops, recursion, and asynchronous structure access",
          "source": "parallel-ttda",
          "locator": "§III; §IV-C"
        }
      },
      "diagram": {
        "title": "Matching, invocation state, and asynchronous I-structures",
        "scope": "One expanded PE plus network/storage roles; conceptual paths from Figs.17–18.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "net",
            "label": "n-cube packet network",
            "subtitle": "DIRECTED TOKENS",
            "text": "Routes tokens directly to destination PEs or I-structures.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-ttda",
            "locator": "Fig.17; §IV-C",
            "control": false
          },
          {
            "id": "wm",
            "label": "Wait-match unit",
            "subtitle": "TAG RENDEZVOUS",
            "text": "Retains an operand until its matching tag arrives.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-ttda",
            "locator": "Fig.18; §IV-B.2",
            "control": false
          },
          {
            "id": "fetch",
            "label": "Instruction fetch",
            "subtitle": "CBR /DBR CONTEXT",
            "text": "Uses invocation context to fetch code and constants.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-ttda",
            "locator": "Fig.18; §IV-B.2",
            "control": false
          },
          {
            "id": "program",
            "label": "Program memory",
            "subtitle": "OP /LITERAL /DESTINATIONS",
            "text": "Stores opcodes,literals and successor instruction offsets.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ttda",
            "locator": "Fig.18; §IV-B.1",
            "control": false
          },
          {
            "id": "constant",
            "label": "Constant memory",
            "subtitle": "INVOCATION CONSTANTS",
            "text": "Stores constants addressed through invocation database registers.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ttda",
            "locator": "Fig.18; §IV-B.2",
            "control": false
          },
          {
            "id": "alu",
            "label": "ALU",
            "subtitle": "OPERAND COMPUTATION",
            "text": "Computes the enabled instruction’s result value.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-ttda",
            "locator": "Fig.18; §IV-B.2",
            "control": false
          },
          {
            "id": "tag",
            "label": "Compute-tag unit",
            "subtitle": "SUCCESSOR TAGS",
            "text": "Combines context with successor offsets for result tags.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-ttda",
            "locator": "Fig.18; §IV-B.2",
            "control": false
          },
          {
            "id": "form",
            "label": "Form tokens",
            "subtitle": "RESULT +DESTINATION",
            "text": "Pairs computed values with their successor tags.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-ttda",
            "locator": "Fig.18; §IV-B.2",
            "control": false
          },
          {
            "id": "is",
            "label": "I-structure units",
            "subtitle": "PRESENT /DEFERRED READ",
            "text": "Defers reads until write-once locations become present.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-ttda",
            "locator": "§III-C; Fig.17",
            "control": false
          },
          {
            "id": "control",
            "label": "Control +external I/O",
            "subtitle": "SPECIAL STATE TOKENS",
            "text": "Accepts special tokens that initialize PE state.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-ttda",
            "locator": "§IV-B.3",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "net",
            "to": "wm",
            "type": "data",
            "source": "parallel-ttda",
            "locator": "Fig.18",
            "label": ""
          },
          {
            "from": "wm",
            "to": "fetch",
            "type": "data",
            "source": "parallel-ttda",
            "locator": "§IV-B.2",
            "label": "matched operands"
          },
          {
            "from": "program",
            "to": "fetch",
            "type": "data",
            "source": "parallel-ttda",
            "locator": "Fig.18",
            "label": ""
          },
          {
            "from": "constant",
            "to": "fetch",
            "type": "data",
            "source": "parallel-ttda",
            "locator": "§IV-B.2",
            "label": ""
          },
          {
            "from": "fetch",
            "to": "alu",
            "type": "data",
            "source": "parallel-ttda",
            "locator": "Fig.18",
            "label": ""
          },
          {
            "from": "fetch",
            "to": "tag",
            "type": "control",
            "source": "parallel-ttda",
            "locator": "§IV-B.2",
            "label": "context /offsets"
          },
          {
            "from": "alu",
            "to": "form",
            "type": "data",
            "source": "parallel-ttda",
            "locator": "Fig.18",
            "label": ""
          },
          {
            "from": "tag",
            "to": "form",
            "type": "control",
            "source": "parallel-ttda",
            "locator": "Fig.18",
            "label": ""
          },
          {
            "from": "form",
            "to": "wm",
            "type": "data",
            "source": "parallel-ttda",
            "locator": "§IV-B.2",
            "label": "local recirculation"
          },
          {
            "from": "form",
            "to": "net",
            "type": "data",
            "source": "parallel-ttda",
            "locator": "§IV-B.2",
            "label": "remote destinations"
          },
          {
            "from": "net",
            "to": "is",
            "type": "data",
            "source": "parallel-ttda",
            "locator": "§III-C; Fig.17",
            "label": "reads /writes"
          },
          {
            "from": "is",
            "to": "net",
            "type": "data",
            "source": "parallel-ttda",
            "locator": "§III-C",
            "label": "read-result tokens"
          },
          {
            "from": "control",
            "to": "fetch",
            "type": "control",
            "source": "parallel-ttda",
            "locator": "§IV-B.3",
            "label": "initialize code/context"
          }
        ]
      },
      "originalCandidate": "MIT Tagged-Token Dataflow Machine"
    },
    {
      "id": "queue-095",
      "name": "Manchester dataflow prototype — 1985 ring",
      "organization": "University of Manchester",
      "year": 1985,
      "yearLabel": "January1985 paper configuration",
      "kind": "Built research prototype",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "architectures": [
        "dataflow-arch",
        "pipelined",
        "microcoded"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "parallel-manchester-dataflow"
      ],
      "summary": "Asynchronous ring modules match tagged operands and dispatch ready instructions to parallel microcoded units.",
      "config": "1985 documented ring with software-emulated overflow; future overflow hardware is excluded.",
      "gaps": [
        "Direct source mirror currently returns404; indexed article body was inspected.",
        "Overflow hardware pictured as a future design was not yet operational."
      ],
      "insight": "Where does a token wait for its partner?",
      "fields": {
        "state": {
          "value": "96-bit tokens; tag/destination identify partners",
          "source": "parallel-manchester-dataflow",
          "locator": "pp.41,46, Fig.7"
        },
        "compute": {
          "value": "Homogeneous microcoded function units",
          "source": "parallel-manchester-dataflow",
          "locator": "p.42, Fig.8"
        },
        "memory": {
          "value": "32Ktoken FIFO and parallel hashed matching store",
          "source": "parallel-manchester-dataflow",
          "locator": "p.41"
        },
        "control": {
          "value": "Availability matching and first-free-unit distribution",
          "source": "parallel-manchester-dataflow",
          "locator": "pp.41–42"
        },
        "io": {
          "value": "Host connects through a2×2 I/O switch",
          "source": "parallel-manchester-dataflow",
          "locator": "p.41"
        },
        "software": {
          "value": "TASS/MACRO, MAD and SISAL",
          "source": "parallel-manchester-dataflow",
          "locator": "p.44"
        },
        "workload": {
          "value": "Numerical and logic benchmark graphs",
          "source": "parallel-manchester-dataflow",
          "locator": "TableII"
        }
      },
      "diagram": {
        "title": "Tagged matching around an asynchronous execution ring",
        "scope": "Built ring roles; overflow represents the contemporary software service.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "host",
            "label": "Host",
            "subtitle": "LOAD /RESULTS",
            "text": "Loads programs/inputs and receives result tokens.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-manchester-dataflow",
            "locator": "p.41",
            "control": false
          },
          {
            "id": "switch",
            "label": "I/O switch",
            "subtitle": "2×2 ROUTING",
            "text": "Routes host/ring tokens using marker-bit decoding.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-manchester-dataflow",
            "locator": "p.41",
            "control": false
          },
          {
            "id": "queue",
            "label": "Token queue",
            "subtitle": "32KTOKEN FIFO",
            "text": "Smooths uneven token production and consumption rates.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-manchester-dataflow",
            "locator": "p.41, Fig.7",
            "control": false
          },
          {
            "id": "match",
            "label": "Matching unit",
            "subtitle": "TAG +DESTINATION",
            "text": "Pairs operands sharing tag and instruction destination.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-manchester-dataflow",
            "locator": "p.41",
            "control": false
          },
          {
            "id": "hash",
            "label": "Parallel hash banks",
            "subtitle": "UNMATCHED TOKENS",
            "text": "Stores waiting operands at parallel hashed locations.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-manchester-dataflow",
            "locator": "p.41, Fig.7",
            "control": false
          },
          {
            "id": "overflow",
            "label": "Overflow service",
            "subtitle": "SOFTWARE EMULATION",
            "text": "Emulates handling of full hash buckets in software.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-manchester-dataflow",
            "locator": "p.42",
            "control": false
          },
          {
            "id": "instr",
            "label": "Instruction store",
            "subtitle": "SEGMENT BASE /BOUND",
            "text": "Uses segment base/bounds to fetch instruction packages.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-manchester-dataflow",
            "locator": "p.42, Fig.8",
            "control": false
          },
          {
            "id": "pre",
            "label": "Preprocessor",
            "subtitle": "GLOBAL OPERATIONS",
            "text": "Handles the few nondistributable global operations.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-manchester-dataflow",
            "locator": "p.42",
            "control": false
          },
          {
            "id": "fu",
            "label": "Function-unit array",
            "subtitle": "MICROCODED EXECUTION",
            "text": "Executes enabled instructions on available microcoded processors.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-manchester-dataflow",
            "locator": "p.42, Fig.8",
            "control": false
          },
          {
            "id": "bus",
            "label": "Arbitration bus",
            "subtitle": "OUTPUT TOKENS",
            "text": "Arbitrates competing result-token outputs back to the ring.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-manchester-dataflow",
            "locator": "p.42",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "switch",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "p.41",
            "label": ""
          },
          {
            "from": "switch",
            "to": "host",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "p.41",
            "label": ""
          },
          {
            "from": "switch",
            "to": "queue",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "queue",
            "to": "match",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "match",
            "to": "hash",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "p.41",
            "label": ""
          },
          {
            "from": "hash",
            "to": "match",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "p.41",
            "label": ""
          },
          {
            "from": "match",
            "to": "overflow",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "p.42",
            "label": ""
          },
          {
            "from": "overflow",
            "to": "match",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "pp.41–42",
            "label": ""
          },
          {
            "from": "match",
            "to": "instr",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "Fig.5",
            "label": "paired /unary"
          },
          {
            "from": "instr",
            "to": "pre",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "Fig.8",
            "label": ""
          },
          {
            "from": "pre",
            "to": "fu",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "p.42",
            "label": "first available"
          },
          {
            "from": "fu",
            "to": "bus",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "p.42",
            "label": ""
          },
          {
            "from": "bus",
            "to": "switch",
            "type": "data",
            "source": "parallel-manchester-dataflow",
            "locator": "Fig.5",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Manchester Dataflow Machine"
    },
    {
      "id": "queue-096",
      "name": "Monsoon — single-processor MIT prototype",
      "organization": "MIT / Motorola collaboration",
      "year": 1988,
      "yearLabel": "Operational since October1988, reported1990",
      "kind": "Built research prototype",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "dataflow"
      ],
      "architectures": [
        "dataflow-arch",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "parallel-monsoon"
      ],
      "summary": "Explicit activation frames replace associative token matching with indexed presence-bit transitions.",
      "config": "The operational single-PE prototype in §4, hosted by a TI Explorer through NuBus; multiprocessor plans are excluded.",
      "gaps": [
        "This prototype had no interprocessor network connection or separate I-structure module.",
        "Heap and activation frames shared the limited frame-store."
      ],
      "insight": "How can a frame address replace an associative search?",
      "fields": {
        "state": {
          "value": "144-bit tokens: typed72-bit tag and value",
          "source": "parallel-monsoon",
          "locator": "§3.1"
        },
        "compute": {
          "value": "Eight-stage token pipeline with ALU and tag generation",
          "source": "parallel-monsoon",
          "locator": "§3.2"
        },
        "memory": {
          "value": "128Kword frame-store and128Kword instruction memory",
          "source": "parallel-monsoon",
          "locator": "§4"
        },
        "control": {
          "value": "Three presence bits per frame slot determine firing",
          "source": "parallel-monsoon",
          "locator": "§3.2"
        },
        "io": {
          "value": "TI Explorer host through a NuBus adapter",
          "source": "parallel-monsoon",
          "locator": "§4"
        },
        "software": {
          "value": "Id runtime; Common Lisp compiler/loader on host",
          "source": "parallel-monsoon",
          "locator": "§4"
        },
        "workload": {
          "value": "Compiled Id programs with parallel calls and loops",
          "source": "parallel-monsoon",
          "locator": "§§2,4"
        }
      },
      "diagram": {
        "title": "Indexed token synchronization and direct recirculation",
        "scope": "Actual single-PE resources; diagram expands the pipeline rather than importing the planned multiprocessor.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "queues",
            "label": "System /user queues",
            "subtitle": "WAITING READY TOKENS",
            "text": "Hold ready local tokens that cannot immediately recirculate.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-monsoon",
            "locator": "Fig.2; §3.2",
            "control": false
          },
          {
            "id": "fetch",
            "label": "Instruction fetch",
            "subtitle": "TOKEN IP",
            "text": "Uses the token’s IP to read an instruction.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-monsoon",
            "locator": "Fig.2",
            "control": false
          },
          {
            "id": "imem",
            "label": "Instruction memory",
            "subtitle": "128K ×32 BITS",
            "text": "Stores the prototype’s local32-bit instruction words.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-monsoon",
            "locator": "§4",
            "control": false
          },
          {
            "id": "ea",
            "label": "Effective address",
            "subtitle": "FP +OFFSET",
            "text": "Adds the instruction offset to its activation frame.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-monsoon",
            "locator": "§3.2",
            "control": false
          },
          {
            "id": "presence",
            "label": "Presence transition",
            "subtitle": "3 BITS /SLOT",
            "text": "Tests/updates slot state and suppresses unmatched continuation.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-monsoon",
            "locator": "§3.2",
            "control": true
          },
          {
            "id": "frame",
            "label": "Frame-store operation",
            "subtitle": "128K ×72 BITS",
            "text": "Reads,writes or exchanges the indexed72-bit operand.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-monsoon",
            "locator": "§§3.2,4",
            "control": false
          },
          {
            "id": "alu",
            "label": "ALU /pointer /type units",
            "subtitle": "OPERANDS /RESULT",
            "text": "Performs arithmetic,pointer,type or machine-control operations.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-monsoon",
            "locator": "§3.2",
            "control": false
          },
          {
            "id": "tags",
            "label": "Next-tag generators",
            "subtitle": "SUCCESSOR IP /FP",
            "text": "Calculates the successor instruction and frame tags.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-monsoon",
            "locator": "Fig.2; §3.2",
            "control": false
          },
          {
            "id": "form",
            "label": "Form-token mux",
            "subtitle": "RESULT +TAG",
            "text": "Joins results/tags and selects local recirculation.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-monsoon",
            "locator": "Fig.2; §3.2",
            "control": false
          },
          {
            "id": "host",
            "label": "TI Explorer /NuBus",
            "subtitle": "COMPILER /LOADER",
            "text": "Runs the Common Lisp compiler and loader.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-monsoon",
            "locator": "§4",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "queues",
            "to": "fetch",
            "type": "data",
            "source": "parallel-monsoon",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "imem",
            "to": "fetch",
            "type": "data",
            "source": "parallel-monsoon",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "fetch",
            "to": "ea",
            "type": "data",
            "source": "parallel-monsoon",
            "locator": "§3.2",
            "label": ""
          },
          {
            "from": "ea",
            "to": "presence",
            "type": "control",
            "source": "parallel-monsoon",
            "locator": "§3.2",
            "label": ""
          },
          {
            "from": "presence",
            "to": "frame",
            "type": "control",
            "source": "parallel-monsoon",
            "locator": "§3.2",
            "label": "read /write /exchange"
          },
          {
            "from": "presence",
            "to": "form",
            "type": "control",
            "source": "parallel-monsoon",
            "locator": "§3.2",
            "label": "suppress if unmatched"
          },
          {
            "from": "ea",
            "to": "frame",
            "type": "control",
            "source": "parallel-monsoon",
            "locator": "§3.2",
            "label": ""
          },
          {
            "from": "frame",
            "to": "alu",
            "type": "data",
            "source": "parallel-monsoon",
            "locator": "§3.2",
            "label": ""
          },
          {
            "from": "frame",
            "to": "tags",
            "type": "control",
            "source": "parallel-monsoon",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "alu",
            "to": "form",
            "type": "data",
            "source": "parallel-monsoon",
            "locator": "§3.2",
            "label": ""
          },
          {
            "from": "tags",
            "to": "form",
            "type": "control",
            "source": "parallel-monsoon",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "form",
            "to": "fetch",
            "type": "data",
            "source": "parallel-monsoon",
            "locator": "§3.2",
            "label": "direct recirculation"
          },
          {
            "from": "form",
            "to": "queues",
            "type": "data",
            "source": "parallel-monsoon",
            "locator": "§3.2",
            "label": "second local token"
          },
          {
            "from": "host",
            "to": "imem",
            "type": "association",
            "source": "parallel-monsoon",
            "locator": "§4",
            "label": "load code"
          },
          {
            "from": "host",
            "to": "frame",
            "type": "association",
            "source": "parallel-monsoon",
            "locator": "§4",
            "label": "load data"
          }
        ]
      },
      "originalCandidate": "Monsoon"
    },
    {
      "id": "queue-097",
      "name": "TRIPS — two-core prototype organization",
      "organization": "University of Texas at Austin",
      "year": 2006,
      "yearLabel": "MICRO2006 prototype paper",
      "kind": "Documented research prototype architecture",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "architectures": [
        "dataflow-arch",
        "distributed",
        "mimd",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "dataflow-model",
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-trips"
      ],
      "summary": "EDGE blocks dispatch across execution tiles; operand routing triggers local execution while distributed protocols commit whole blocks.",
      "config": "Two16-wide cores and1MB configurable NUCA in the2006 prototype paper.",
      "gaps": [
        "Paper-year identifies the documented design, not an installation or acceptance date.",
        "The graph aggregates seven core micronetworks by operand, dispatch, and control roles."
      ],
      "insight": "Which operations remain global when instruction execution becomes distributed?",
      "fields": {
        "state": {
          "value": "64-bit operands; up to eight128-instruction blocks/core",
          "source": "parallel-trips",
          "locator": "§3"
        },
        "compute": {
          "value": "16 execution tiles/core, each integer and FP units",
          "source": "parallel-trips",
          "locator": "§3.4"
        },
        "memory": {
          "value": "Four L1 data banks/core;16 secondary64KB banks",
          "source": "parallel-trips",
          "locator": "§§3.5–3.6"
        },
        "control": {
          "value": "Global tile predicts blocks; distributed completion/commit",
          "source": "parallel-trips",
          "locator": "§§3.1,4"
        },
        "io": {
          "value": "On-chip network carries DRAM, I/O and DMA traffic",
          "source": "parallel-trips",
          "locator": "§§3,5"
        },
        "software": {
          "value": "EDGE ISA encodes explicit intra-block destinations",
          "source": "parallel-trips",
          "locator": "§2"
        },
        "workload": {
          "value": "Instruction-level and thread-level parallel execution",
          "source": "parallel-trips",
          "locator": "§§1–2"
        }
      },
      "diagram": {
        "title": "Block dispatch and operand flow across a tiled core",
        "scope": "Core0 expanded; core1 and secondary memory aggregated. Network nodes show distinct protocol roles.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "gt",
            "label": "Global control tile",
            "subtitle": "PREDICT /COMMIT /FLUSH",
            "text": "Predicts blocks and coordinates fetch,flush and commit.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-trips",
            "locator": "§3.1",
            "control": true
          },
          {
            "id": "it",
            "label": "Five instruction tiles",
            "subtitle": "FETCH BLOCK CONTENTS",
            "text": "Sends fetched block instructions to execution/register tiles.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-trips",
            "locator": "§3.2",
            "control": false
          },
          {
            "id": "gdn",
            "label": "Dispatch network",
            "subtitle": "BLOCK INSTRUCTIONS",
            "text": "Pipelines instructions to their compiler-assigned tiles.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-trips",
            "locator": "Fig.3",
            "control": false
          },
          {
            "id": "et",
            "label": "16 execution tiles",
            "subtitle": "DATA-DRIVEN ISSUE",
            "text": "Fires resident instructions when operand slots become ready.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-trips",
            "locator": "§3.4",
            "control": false
          },
          {
            "id": "opn",
            "label": "5×5 operand mesh",
            "subtitle": "64-BIT OPERANDS",
            "text": "Routes operands directly among data,register and execution tiles.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-trips",
            "locator": "§3",
            "control": false
          },
          {
            "id": "rt",
            "label": "Four register tiles",
            "subtitle": "INTER-BLOCK STATE",
            "text": "Holds architectural registers and inter-block forwarding queues.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-trips",
            "locator": "§3.3",
            "control": false
          },
          {
            "id": "dt",
            "label": "Four data tiles",
            "subtitle": "L1D +REPLICATED LSQ",
            "text": "Combines L1 data banking with replicated disambiguation state.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-trips",
            "locator": "§3.5",
            "control": false
          },
          {
            "id": "ocn",
            "label": "4×10 on-chip network",
            "subtitle": "CACHE LINES /I/O",
            "text": "Transports cache-line,DRAM,DMA and I/O traffic.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-trips",
            "locator": "§3",
            "control": false
          },
          {
            "id": "mt",
            "label": "16 memory tiles",
            "subtitle": "1MB CACHE /SCRATCHPAD",
            "text": "Provides configurable L2 banks or scratchpad memory.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-trips",
            "locator": "§3.6",
            "control": false
          },
          {
            "id": "other",
            "label": "Core1 /DRAM /I/O",
            "subtitle": "OTHER OCN CLIENTS",
            "text": "Represents remaining processor and external OCN clients.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-trips",
            "locator": "Fig.2; §§3,5",
            "control": false
          },
          {
            "id": "control",
            "label": "Control micronetworks",
            "subtitle": "STATUS /COMMIT /REFILL",
            "text": "Carries distributed completion,commit,flush and refill protocols.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-trips",
            "locator": "Fig.3",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "gt",
            "to": "it",
            "type": "control",
            "source": "parallel-trips",
            "locator": "§4.1",
            "label": "fetch command"
          },
          {
            "from": "it",
            "to": "gdn",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "gdn",
            "to": "et",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "gdn",
            "to": "rt",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§4.1",
            "label": ""
          },
          {
            "from": "rt",
            "to": "opn",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§3.3",
            "label": ""
          },
          {
            "from": "opn",
            "to": "rt",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§3.3",
            "label": ""
          },
          {
            "from": "et",
            "to": "opn",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§3.4",
            "label": ""
          },
          {
            "from": "opn",
            "to": "et",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§3.4",
            "label": ""
          },
          {
            "from": "dt",
            "to": "opn",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§3.5",
            "label": ""
          },
          {
            "from": "opn",
            "to": "dt",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§3.5",
            "label": ""
          },
          {
            "from": "dt",
            "to": "ocn",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§3.6",
            "label": ""
          },
          {
            "from": "it",
            "to": "ocn",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§3.6",
            "label": "refill"
          },
          {
            "from": "ocn",
            "to": "mt",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§3.6",
            "label": ""
          },
          {
            "from": "mt",
            "to": "ocn",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§3.6",
            "label": ""
          },
          {
            "from": "ocn",
            "to": "other",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "other",
            "to": "ocn",
            "type": "data",
            "source": "parallel-trips",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "gt",
            "to": "control",
            "type": "control",
            "source": "parallel-trips",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "control",
            "to": "et",
            "type": "control",
            "source": "parallel-trips",
            "locator": "§4",
            "label": "commit /flush"
          },
          {
            "from": "control",
            "to": "gt",
            "type": "control",
            "source": "parallel-trips",
            "locator": "Fig.3",
            "label": "completion"
          }
        ]
      },
      "originalCandidate": "TRIPS"
    },
    {
      "id": "queue-098",
      "name": "WaveScalar — 2003 WaveCache proposal",
      "organization": "University of Washington",
      "year": 2003,
      "yearLabel": "MICRO2003 proposed/simulated architecture",
      "kind": "Simulated architecture proposal",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "architectures": [
        "dataflow-arch",
        "distributed"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "parallel-wavescalar"
      ],
      "summary": "Instructions remain in distributed processing elements; wave tags and ordered memory requests preserve imperative load/store behavior.",
      "config": "Original2003 WaveCache proposal: roughly2K PEs in16-PE clusters, eight instruction slots/PE.",
      "gaps": [
        "No fabricated WaveCache is claimed by the2003 paper.",
        "Store-buffer assignment has two proposed alternatives; the graph shows the shared ordering principle only."
      ],
      "insight": "How can dataflow execution preserve the order of memory side effects?",
      "fields": {
        "state": {
          "value": "Operands carry wave numbers identifying dynamic executions",
          "source": "parallel-wavescalar",
          "locator": "§3.2"
        },
        "compute": {
          "value": "PE functional units execute locally resident instructions",
          "source": "parallel-wavescalar",
          "locator": "§4"
        },
        "memory": {
          "value": "Operand queues; L1/store buffer per four clusters; unified L2/DRAM",
          "source": "parallel-wavescalar",
          "locator": "§4"
        },
        "control": {
          "value": "Full/empty matching and compiler-generated wave management",
          "source": "parallel-wavescalar",
          "locator": "§§3.2,4"
        },
        "io": {
          "value": "Conventional DRAM path; external device system unspecified",
          "source": "parallel-wavescalar",
          "locator": "§4"
        },
        "software": {
          "value": "Binary translation and explicit wave/memory annotations",
          "source": "parallel-wavescalar",
          "locator": "§§3.2,5–6"
        },
        "workload": {
          "value": "Simulated general-purpose benchmark programs",
          "source": "parallel-wavescalar",
          "locator": "§6"
        }
      },
      "diagram": {
        "title": "Resident instructions and wave-ordered memory",
        "scope": "Proposed PE/cluster paths; compiler annotations are control metadata, not a centralized runtime controller.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "slots",
            "label": "PE instruction slots",
            "subtitle": "EIGHT RESIDENT INSTRUCTIONS",
            "text": "Keeps several instructions resident at one processing element.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-wavescalar",
            "locator": "§4",
            "control": false
          },
          {
            "id": "input",
            "label": "Operand input queues",
            "subtitle": "INDEXED BY WAVE",
            "text": "Retains operands indexed by dynamic wave identity.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-wavescalar",
            "locator": "§4",
            "control": false
          },
          {
            "id": "match",
            "label": "Full /empty bits",
            "subtitle": "OPERAND MATCHING",
            "text": "Marks operand presence without content-addressable matching.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-wavescalar",
            "locator": "§4",
            "control": true
          },
          {
            "id": "alu",
            "label": "PE functional unit",
            "subtitle": "READY INSTRUCTION",
            "text": "Executes a resident instruction once inputs are ready.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-wavescalar",
            "locator": "Fig.3; §4",
            "control": false
          },
          {
            "id": "out",
            "label": "Output queues /buses",
            "subtitle": "INTRA-CLUSTER VALUES",
            "text": "Delivers results to consumers over local cluster buses.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-wavescalar",
            "locator": "§4",
            "control": false
          },
          {
            "id": "net",
            "label": "Inter-cluster network",
            "subtitle": "DYNAMIC ROUTING",
            "text": "Dynamically routes values between PE clusters.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-wavescalar",
            "locator": "§4",
            "control": false
          },
          {
            "id": "order",
            "label": "Wave memory annotations",
            "subtitle": "PRED /THIS /SUCCESSOR",
            "text": "Encodes sequence and predecessor/successor memory relationships.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-wavescalar",
            "locator": "§3.2",
            "control": true
          },
          {
            "id": "store",
            "label": "Wave-ordered store buffer",
            "subtitle": "ONE PER FOUR CLUSTERS",
            "text": "Orders a wave’s loads/stores before memory effects.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-wavescalar",
            "locator": "§4",
            "control": false
          },
          {
            "id": "l1",
            "label": "L1 data cache",
            "subtitle": "FOUR-CLUSTER GROUP",
            "text": "Caches data for each four-cluster PE group.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-wavescalar",
            "locator": "§4",
            "control": false
          },
          {
            "id": "lower",
            "label": "Unified L2 /DRAM",
            "subtitle": "CONVENTIONAL MEMORY",
            "text": "Supplies conventional backing memory beyond the WaveCache.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-wavescalar",
            "locator": "§4",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "slots",
            "to": "alu",
            "type": "control",
            "source": "parallel-wavescalar",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "input",
            "to": "match",
            "type": "data",
            "source": "parallel-wavescalar",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "match",
            "to": "alu",
            "type": "control",
            "source": "parallel-wavescalar",
            "locator": "§4",
            "label": "ready"
          },
          {
            "from": "input",
            "to": "alu",
            "type": "data",
            "source": "parallel-wavescalar",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "alu",
            "to": "out",
            "type": "data",
            "source": "parallel-wavescalar",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "out",
            "to": "input",
            "type": "data",
            "source": "parallel-wavescalar",
            "locator": "§4",
            "label": "local consumers"
          },
          {
            "from": "out",
            "to": "net",
            "type": "data",
            "source": "parallel-wavescalar",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "net",
            "to": "input",
            "type": "data",
            "source": "parallel-wavescalar",
            "locator": "§4",
            "label": "remote consumers"
          },
          {
            "from": "order",
            "to": "store",
            "type": "control",
            "source": "parallel-wavescalar",
            "locator": "§3.2",
            "label": "request ordering links"
          },
          {
            "from": "alu",
            "to": "store",
            "type": "data",
            "source": "parallel-wavescalar",
            "locator": "§§3.2,4",
            "label": "memory requests"
          },
          {
            "from": "store",
            "to": "l1",
            "type": "data",
            "source": "parallel-wavescalar",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "l1",
            "to": "input",
            "type": "data",
            "source": "parallel-wavescalar",
            "locator": "§§3.2,4",
            "label": "load values"
          },
          {
            "from": "l1",
            "to": "lower",
            "type": "data",
            "source": "parallel-wavescalar",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "lower",
            "to": "l1",
            "type": "data",
            "source": "parallel-wavescalar",
            "locator": "§4",
            "label": ""
          }
        ]
      },
      "originalCandidate": "WaveScalar"
    },
    {
      "id": "queue-099",
      "name": "INMOS B401-3 — T800 TRAM node",
      "organization": "INMOS",
      "year": 1991,
      "yearLabel": "1991 databook /December1990 module revision",
      "kind": "Commercial parallel-system building block",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "mimd",
        "distributed",
        "stack"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-t800",
        "parallel-b401"
      ],
      "summary": "A complete T800 node combines local memory and hardware process scheduling with four independent serial communication links.",
      "config": "B401-3 module: T800-20,4KB internal RAM and32KB external SRAM; unspecified motherboard wiring is excluded.",
      "gaps": [
        "This resolves a broad systems family to one documented node, not a particular multi-node installation.",
        "Preliminary1987 chip organization is combined only with documented B401-3 module integration; no undocumented network topology."
      ],
      "insight": "Why put scheduling and communication inside each distributed node?",
      "fields": {
        "state": {
          "value": "32-bit processor with64-bit floating-point unit",
          "source": "parallel-t800",
          "locator": "feature page"
        },
        "compute": {
          "value": "Integer processor and integral IEEE floating-point hardware",
          "source": "parallel-t800",
          "locator": "feature page; printedp.2"
        },
        "memory": {
          "value": "4KB on-chip plus32KB module SRAM",
          "source": "parallel-b401",
          "locator": "§17.1.4"
        },
        "control": {
          "value": "Hardware concurrent-process scheduler and timers",
          "source": "parallel-t800",
          "locator": "feature page"
        },
        "io": {
          "value": "Four serial links plus reset/analyse/error service pins",
          "source": "parallel-b401",
          "locator": "Table17.1; §17.1.3"
        },
        "software": {
          "value": "occam toolchain and transputer runtime libraries",
          "source": "parallel-b401",
          "locator": "software tools chapters"
        },
        "workload": {
          "value": "Systolic/signal processing and feature extraction",
          "source": "parallel-b401",
          "locator": "p.149"
        }
      },
      "diagram": {
        "title": "A self-contained distributed node with four serial links",
        "scope": "Chip internal bus expanded within the B401-3 module; link endpoints intentionally unspecified.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cpu",
            "label": "32-bit processor",
            "subtitle": "HARDWARE PROCESS SCHEDULING",
            "text": "Executes integer code with hardware process scheduling.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-t800",
            "locator": "feature page; printedp.2",
            "control": false
          },
          {
            "id": "fpu",
            "label": "64-bit FPU",
            "subtitle": "IEEE754",
            "text": "Provides integral IEEE floating-point arithmetic.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-t800",
            "locator": "feature page; printedp.2",
            "control": false
          },
          {
            "id": "bus",
            "label": "Internal32-bit bus",
            "subtitle": "LOCAL TRANSFERS",
            "text": "Connects processor,memory and link-interface resources.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-t800",
            "locator": "printedp.2",
            "control": false
          },
          {
            "id": "ram",
            "label": "4KB on-chip RAM",
            "subtitle": "LOCAL STATE",
            "text": "Holds fast local code and process data.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-t800",
            "locator": "printedp.2",
            "control": false
          },
          {
            "id": "emi",
            "label": "External memory interface",
            "subtitle": "CONFIGURABLE BUS",
            "text": "Connects the transputer to module-local external SRAM.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-t800",
            "locator": "printedp.2",
            "control": false
          },
          {
            "id": "sram",
            "label": "32KB module SRAM",
            "subtitle": "B401-3 EXTERNAL STORE",
            "text": "Extends the B401-3 node’s private storage.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-b401",
            "locator": "§17.1.4",
            "control": false
          },
          {
            "id": "l0",
            "label": "Link0 interface",
            "subtitle": "SERIAL IN /OUT",
            "text": "Provides serial communication independent of links1–3.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-t800",
            "locator": "printedp.2",
            "control": false
          },
          {
            "id": "l1",
            "label": "Link1 interface",
            "subtitle": "SERIAL IN /OUT",
            "text": "Provides serial communication independent of the other links.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-t800",
            "locator": "printedp.2",
            "control": false
          },
          {
            "id": "l2",
            "label": "Link2 interface",
            "subtitle": "SERIAL IN /OUT",
            "text": "Provides serial communication independent of the other links.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-t800",
            "locator": "printedp.2",
            "control": false
          },
          {
            "id": "l3",
            "label": "Link3 interface",
            "subtitle": "SERIAL IN /OUT",
            "text": "Provides serial communication independent of the other links.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-t800",
            "locator": "printedp.2",
            "control": false
          },
          {
            "id": "svc",
            "label": "Timers /system services",
            "subtitle": "RESET /ANALYSE /ERROR",
            "text": "Supplies timing,reset,analysis and error service functions.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-t800",
            "locator": "printedp.2",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "cpu",
            "to": "bus",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "bus",
            "to": "cpu",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "fpu",
            "to": "bus",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "bus",
            "to": "fpu",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "ram",
            "to": "bus",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "bus",
            "to": "ram",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "bus",
            "to": "emi",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "emi",
            "to": "sram",
            "type": "data",
            "source": "parallel-b401",
            "locator": "§17.1.4",
            "label": ""
          },
          {
            "from": "sram",
            "to": "emi",
            "type": "data",
            "source": "parallel-b401",
            "locator": "§17.1.4",
            "label": ""
          },
          {
            "from": "emi",
            "to": "bus",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "bus",
            "to": "l0",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "l0",
            "to": "bus",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "bus",
            "to": "l1",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "l1",
            "to": "bus",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "bus",
            "to": "l2",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "l2",
            "to": "bus",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "bus",
            "to": "l3",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "l3",
            "to": "bus",
            "type": "data",
            "source": "parallel-t800",
            "locator": "printedp.2",
            "label": ""
          },
          {
            "from": "svc",
            "to": "cpu",
            "type": "association",
            "source": "parallel-t800",
            "locator": "feature page",
            "label": "scheduler timing /services"
          }
        ]
      },
      "originalCandidate": "INMOS Transputer T800 systems"
    },
    {
      "id": "queue-100",
      "name": "iWarp — 1990 cell architecture",
      "organization": "Intel / Carnegie Mellon University",
      "year": 1990,
      "yearLabel": "1990 paper following December1989 first silicon",
      "kind": "Prototype processor/system building block",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "architectures": [
        "distributed",
        "mimd",
        "vliw",
        "systolic"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "process",
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "parallel-iwarp"
      ],
      "summary": "Independent computation, communication and memory agents support direct systolic operands and memory-buffered messages.",
      "config": "The1990 iWarp cell and pathway mechanisms; the paper’s planned8×8 torus is not claimed as delivered.",
      "gaps": [
        "The delivery date of the planned64-cell systems is not established here.",
        "Channel multiplexing is shown by role; no particular application’s reserved pathway is asserted."
      ],
      "insight": "When should a message enter memory, and when should it become an arithmetic operand?",
      "fields": {
        "state": {
          "value": "Integer and single/double floating-point data",
          "source": "parallel-iwarp",
          "locator": "§1"
        },
        "compute": {
          "value": "Long instruction words coordinate multiple functional units",
          "source": "parallel-iwarp",
          "locator": "§§1,7.1"
        },
        "memory": {
          "value": "Per-cell local memory; memory agent spools message queues",
          "source": "parallel-iwarp",
          "locator": "§7.2"
        },
        "control": {
          "value": "Logical pathways, event CAM and status registers",
          "source": "parallel-iwarp",
          "locator": "§§6,7.3"
        },
        "io": {
          "value": "Four input and four output physical buses",
          "source": "parallel-iwarp",
          "locator": "§§1,4"
        },
        "software": {
          "value": "C/Fortran compilers and parallel programming environments",
          "source": "parallel-iwarp",
          "locator": "§1"
        },
        "workload": {
          "value": "Systolic streams and distributed-memory message passing",
          "source": "parallel-iwarp",
          "locator": "§§1–2"
        }
      },
      "diagram": {
        "title": "Two communication paths: systolic gates and memory spooling",
        "scope": "One cell expanded; neighbor communication passes through logical channels and multiplexed physical buses.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "exec",
            "label": "Computation agent",
            "subtitle": "LONG-INSTRUCTION-WORD",
            "text": "Executes long instruction words across computational units.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-iwarp",
            "locator": "§1",
            "control": false
          },
          {
            "id": "gates",
            "label": "Systolic gates",
            "subtitle": "2 INPUT /2 OUTPUT",
            "text": "Makes stream receive/send appear as register operands.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-iwarp",
            "locator": "§7.1",
            "control": false
          },
          {
            "id": "queues",
            "label": "Logical channel queues",
            "subtitle": "WORD-STREAM BUFFERS",
            "text": "Buffers words belonging to separately allocated logical channels.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-iwarp",
            "locator": "§5",
            "control": false
          },
          {
            "id": "cross",
            "label": "Logical crossbar",
            "subtitle": "PATHWAYS /FORWARDING",
            "text": "Connects logical channels into reserved forwarding pathways.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-iwarp",
            "locator": "§§6–7",
            "control": false
          },
          {
            "id": "ports",
            "label": "Physical bus ports",
            "subtitle": "FOUR INPUT /FOUR OUTPUT",
            "text": "Multiplexes logical channels over physical neighbor buses.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-iwarp",
            "locator": "§4",
            "control": false
          },
          {
            "id": "neighbor",
            "label": "Neighboring cells",
            "subtitle": "APPLICATION TOPOLOGY",
            "text": "Represents cells connected by the selected array topology.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-iwarp",
            "locator": "Fig.1",
            "control": false
          },
          {
            "id": "spool",
            "label": "Memory agent",
            "subtitle": "EIGHT SPOOLING GATES",
            "text": "Transfers queued message words to/from local memory.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-iwarp",
            "locator": "§7.2",
            "control": false
          },
          {
            "id": "mem",
            "label": "Local memory",
            "subtitle": "BUFFERED MESSAGES /CODE",
            "text": "Stores code,data and longer buffered message streams.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-iwarp",
            "locator": "§§1,7.2",
            "control": false
          },
          {
            "id": "cam",
            "label": "Match CAM /status",
            "subtitle": "EVENT NOTIFICATION",
            "text": "Matches communication events and notifies computation control.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-iwarp",
            "locator": "§7.3",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "exec",
            "to": "gates",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§7.1",
            "label": ""
          },
          {
            "from": "gates",
            "to": "exec",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§7.1",
            "label": ""
          },
          {
            "from": "gates",
            "to": "queues",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§7.1",
            "label": ""
          },
          {
            "from": "queues",
            "to": "gates",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§7.1",
            "label": ""
          },
          {
            "from": "queues",
            "to": "cross",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§§5–6",
            "label": ""
          },
          {
            "from": "cross",
            "to": "queues",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§§5–6",
            "label": ""
          },
          {
            "from": "cross",
            "to": "ports",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§§4–6",
            "label": ""
          },
          {
            "from": "ports",
            "to": "cross",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§§4–6",
            "label": ""
          },
          {
            "from": "ports",
            "to": "neighbor",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "neighbor",
            "to": "ports",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§4",
            "label": ""
          },
          {
            "from": "queues",
            "to": "spool",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§7.2",
            "label": ""
          },
          {
            "from": "spool",
            "to": "queues",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§7.2",
            "label": ""
          },
          {
            "from": "spool",
            "to": "mem",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§7.2",
            "label": ""
          },
          {
            "from": "mem",
            "to": "spool",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§7.2",
            "label": ""
          },
          {
            "from": "mem",
            "to": "exec",
            "type": "data",
            "source": "parallel-iwarp",
            "locator": "§7.2",
            "label": ""
          },
          {
            "from": "exec",
            "to": "cam",
            "type": "control",
            "source": "parallel-iwarp",
            "locator": "§7.3",
            "label": ""
          },
          {
            "from": "cam",
            "to": "exec",
            "type": "control",
            "source": "parallel-iwarp",
            "locator": "§7.3",
            "label": "status events"
          },
          {
            "from": "cam",
            "to": "cross",
            "type": "control",
            "source": "parallel-iwarp",
            "locator": "§6.1.4",
            "label": "pathway begin match"
          }
        ]
      },
      "originalCandidate": "iWarp"
    },
    {
      "id": "queue-101",
      "name": "Raw — sixteen-tile prototype motherboard",
      "organization": "MIT / ISI-East",
      "year": 2004,
      "yearLabel": "2004 paper; chips received October2002",
      "kind": "Built research prototype",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "stored-program",
        "mimd",
        "distributed",
        "reconfigurable",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-raw"
      ],
      "summary": "Compiler-programmed static networks expose wire delay; separate dynamic meshes serve memory and general messages.",
      "config": "Single16-tile Raw chip with SDRAM, I/O and interface FPGAs in the2004 prototype motherboard.",
      "gaps": [
        "The four networks are distinct: two static, one trusted memory, one general dynamic.",
        "The2004 evaluation mixes prototype observations with validated simulation; no benchmark speedup is generalized here."
      ],
      "insight": "What becomes programmable when network paths are part of the ISA?",
      "fields": {
        "state": {
          "value": "32-bit MIPS-style pipelines and single-precision FPUs",
          "source": "parallel-raw",
          "locator": "§2,Tiled Architecture"
        },
        "compute": {
          "value": "16 tiles with8-stage single-issue processors",
          "source": "parallel-raw",
          "locator": "§2"
        },
        "memory": {
          "value": "32KB data and32KB compute instruction cache/tile",
          "source": "parallel-raw",
          "locator": "§2"
        },
        "control": {
          "value": "64KB static-router instruction cache/tile; compiler routes",
          "source": "parallel-raw",
          "locator": "§2,On-chip Networks"
        },
        "io": {
          "value": "Fourteen physical32-bit full-duplex edge ports",
          "source": "parallel-raw",
          "locator": "§2,Direct I/O Interfaces"
        },
        "software": {
          "value": "ILP and stream compilers; exposed routing ISA",
          "source": "parallel-raw",
          "locator": "§§1–2"
        },
        "workload": {
          "value": "Sequential ILP, streams, server and bit-level computation",
          "source": "parallel-raw",
          "locator": "§4"
        }
      },
      "diagram": {
        "title": "An expanded Raw tile and programmable chip edges",
        "scope": "One of16 tiles; links summarize registered nearest-neighbor meshes rather than a central switch.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "cpu",
            "label": "Compute pipeline +FPU",
            "subtitle": "MIPS-STYLE /IN ORDER",
            "text": "Runs local instructions and consumes register-mapped network operands.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-raw",
            "locator": "§2",
            "control": false
          },
          {
            "id": "ic",
            "label": "Compute instruction cache",
            "subtitle": "32KB /TILE",
            "text": "Holds software-managed instructions for the compute pipeline.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-raw",
            "locator": "§2",
            "control": false
          },
          {
            "id": "dc",
            "label": "Data cache",
            "subtitle": "32KB /TILE",
            "text": "Caches local data accessed through ordinary loads/stores.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-raw",
            "locator": "§2",
            "control": false
          },
          {
            "id": "static",
            "label": "Static router crossbars",
            "subtitle": "TWO STATIC MESHES",
            "text": "Executes compiler-scheduled routes for two operand networks.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-raw",
            "locator": "§2",
            "control": false
          },
          {
            "id": "smem",
            "label": "Router instruction cache",
            "subtitle": "64KB /TILE",
            "text": "Stores the tile’s static routing instruction program.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-raw",
            "locator": "§2",
            "control": false
          },
          {
            "id": "memnet",
            "label": "Dynamic memory router",
            "subtitle": "TRUSTED CACHE /DMA",
            "text": "Carries trusted cache,DMA and I/O transactions.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-raw",
            "locator": "§2",
            "control": false
          },
          {
            "id": "general",
            "label": "General dynamic router",
            "subtitle": "UNTRUSTED MESSAGES",
            "text": "Carries general messages with deadlock-recovery support.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-raw",
            "locator": "§2",
            "control": false
          },
          {
            "id": "neighbor",
            "label": "Neighboring tiles",
            "subtitle": "4×4 MESH FABRICS",
            "text": "Represents registered links to adjacent Raw tiles.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-raw",
            "locator": "Fig.1; §2",
            "control": false
          },
          {
            "id": "edge",
            "label": "Chip-edge ports",
            "subtitle": "14 PHYSICAL PORTS",
            "text": "Maps perimeter network channels onto external pins.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-raw",
            "locator": "§2,Direct I/O",
            "control": false
          },
          {
            "id": "external",
            "label": "SDRAM /I/O /FPGAs",
            "subtitle": "PROTOTYPE MOTHERBOARD",
            "text": "Connects prototype SDRAM,peripherals and interface logic.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-raw",
            "locator": "§§1,3",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "ic",
            "to": "cpu",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "dc",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "dc",
            "to": "cpu",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "static",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": "register /bypass interface"
          },
          {
            "from": "static",
            "to": "cpu",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "smem",
            "to": "static",
            "type": "control",
            "source": "parallel-raw",
            "locator": "§2",
            "label": "routing instructions"
          },
          {
            "from": "dc",
            "to": "memnet",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "memnet",
            "to": "dc",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "general",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "general",
            "to": "cpu",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "static",
            "to": "neighbor",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "memnet",
            "to": "neighbor",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "general",
            "to": "neighbor",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "neighbor",
            "to": "static",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "neighbor",
            "to": "memnet",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "neighbor",
            "to": "general",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "static",
            "to": "edge",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2,Direct I/O",
            "label": ""
          },
          {
            "from": "memnet",
            "to": "edge",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2,Direct I/O",
            "label": ""
          },
          {
            "from": "general",
            "to": "edge",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2,Direct I/O",
            "label": ""
          },
          {
            "from": "edge",
            "to": "external",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§§1–3",
            "label": ""
          },
          {
            "from": "external",
            "to": "edge",
            "type": "data",
            "source": "parallel-raw",
            "locator": "§2,Direct I/O",
            "label": ""
          }
        ]
      },
      "originalCandidate": "RAW machine"
    },
    {
      "id": "queue-102",
      "name": "MIT Eyeriss —2016 test chip",
      "organization": "MIT / NVIDIA",
      "year": 2016,
      "yearLabel": "ISSCC2016 chip disclosure",
      "kind": "Research accelerator test chip",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "architectures": [
        "dataflow-arch",
        "reconfigurable",
        "heterogeneous",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural",
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "parallel-eyeriss"
      ],
      "summary": "A row-stationary PE array reuses images, weights, and partial sums through local storage and configurable multicast.",
      "config": "The original168-PE Eyeriss chip; Eyerissv2 is distinct.",
      "gaps": [
        "The graph illustrates data roles rather than an exact mapping for every CNN shape.",
        "Chip power and frame rates are workload/measurement-specific and are not generalized here."
      ],
      "insight": "Which reuse is local and which requires the global buffer?",
      "fields": {
        "state": {
          "value": "Images, filter weights, partial sums",
          "source": "parallel-eyeriss",
          "locator": "p.262, dataflow"
        },
        "compute": {
          "value": "168 PEs; three-stage inner-product engines",
          "source": "parallel-eyeriss",
          "locator": "Figs.14.5.2/14.5.5"
        },
        "memory": {
          "value": "108KB shared SRAM plus PE scratchpads",
          "source": "parallel-eyeriss",
          "locator": "p.262"
        },
        "control": {
          "value": "Layer mapping, multicast IDs, ready/clock gating",
          "source": "parallel-eyeriss",
          "locator": "p.262, NoC"
        },
        "io": {
          "value": "DRAM traffic with run-length compression",
          "source": "parallel-eyeriss",
          "locator": "p.262"
        },
        "software": {
          "value": "Configured CNN layer mappings",
          "source": "parallel-eyeriss",
          "locator": "p.262"
        },
        "workload": {
          "value": "CNN convolution layers",
          "source": "parallel-eyeriss",
          "locator": "p.262"
        }
      },
      "diagram": {
        "title": "Row-stationary reuse and separate multicast paths",
        "scope": "Logical data roles from the original chip. Local PE state is expanded; array placement is conceptual.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "dram",
            "label": "Off-chip DRAM",
            "subtitle": "INPUT / OUTPUT",
            "text": "External tensor storage.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-eyeriss",
            "locator": "Fig.14.5.2",
            "control": false
          },
          {
            "id": "codec",
            "label": "Compression / ReLU",
            "subtitle": "OUTPUT PROCESSING",
            "text": "Reduces external traffic.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-eyeriss",
            "locator": "p.262",
            "control": false
          },
          {
            "id": "glb",
            "label": "Shared SRAM buffer",
            "subtitle": "108KB /IMG,FILT,PSUM",
            "text": "Stores reusable values.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-eyeriss",
            "locator": "Fig.14.5.2",
            "control": false
          },
          {
            "id": "noc",
            "label": "Multicast networks",
            "subtitle": "SEPARATE DATA TYPES",
            "text": "Configurable target IDs.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-eyeriss",
            "locator": "Fig.14.5.4",
            "control": false
          },
          {
            "id": "scratch",
            "label": "PE scratchpads",
            "subtitle": "LOCAL TEMPORAL REUSE",
            "text": "Retains image/filter/psum.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-eyeriss",
            "locator": "Fig.14.5.5",
            "control": false
          },
          {
            "id": "mac",
            "label": "PE computation",
            "subtitle": "THREE-STAGE PIPELINE",
            "text": "Computes row inner products.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-eyeriss",
            "locator": "Fig.14.5.5",
            "control": false
          },
          {
            "id": "neighbor",
            "label": "Neighbor PE links",
            "subtitle": "PARTIAL-SUM MOVEMENT",
            "text": "Combines across filter rows.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-eyeriss",
            "locator": "Fig.14.5.3",
            "control": false
          },
          {
            "id": "mapping",
            "label": "Layer configuration",
            "subtitle": "FOLD / REPLICATE / IDS",
            "text": "Adapts the data mapping.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-eyeriss",
            "locator": "p.262",
            "control": true
          },
          {
            "id": "zero",
            "label": "Zero buffer / gating",
            "subtitle": "SKIP INACTIVE WORK",
            "text": "Suppresses unneeded activity.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-eyeriss",
            "locator": "p.262",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "dram",
            "to": "glb",
            "type": "data",
            "source": "parallel-eyeriss",
            "locator": "Fig.14.5.2",
            "label": ""
          },
          {
            "from": "glb",
            "to": "noc",
            "type": "data",
            "source": "parallel-eyeriss",
            "locator": "Fig.14.5.4",
            "label": ""
          },
          {
            "from": "noc",
            "to": "scratch",
            "type": "data",
            "source": "parallel-eyeriss",
            "locator": "Fig.14.5.4",
            "label": ""
          },
          {
            "from": "scratch",
            "to": "mac",
            "type": "data",
            "source": "parallel-eyeriss",
            "locator": "Fig.14.5.5",
            "label": ""
          },
          {
            "from": "mac",
            "to": "scratch",
            "type": "data",
            "source": "parallel-eyeriss",
            "locator": "Fig.14.5.5",
            "label": ""
          },
          {
            "from": "mac",
            "to": "neighbor",
            "type": "data",
            "source": "parallel-eyeriss",
            "locator": "Fig.14.5.3",
            "label": ""
          },
          {
            "from": "neighbor",
            "to": "glb",
            "type": "data",
            "source": "parallel-eyeriss",
            "locator": "p.262",
            "label": ""
          },
          {
            "from": "glb",
            "to": "codec",
            "type": "data",
            "source": "parallel-eyeriss",
            "locator": "p.262",
            "label": ""
          },
          {
            "from": "codec",
            "to": "dram",
            "type": "data",
            "source": "parallel-eyeriss",
            "locator": "p.262",
            "label": ""
          },
          {
            "from": "mapping",
            "to": "noc",
            "type": "control",
            "source": "parallel-eyeriss",
            "locator": "p.262",
            "label": ""
          },
          {
            "from": "mapping",
            "to": "mac",
            "type": "control",
            "source": "parallel-eyeriss",
            "locator": "p.262",
            "label": ""
          },
          {
            "from": "zero",
            "to": "mac",
            "type": "control",
            "source": "parallel-eyeriss",
            "locator": "p.262",
            "label": ""
          }
        ]
      },
      "originalCandidate": "MIT Eyeriss"
    },
    {
      "id": "queue-103",
      "name": "Google TPU v1 — inference coprocessor",
      "organization": "Google",
      "year": 2017,
      "yearLabel": "2017 architecture disclosure",
      "kind": "Deployed accelerator configuration",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "architectures": [
        "systolic",
        "heterogeneous",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural",
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "parallel-tpu1"
      ],
      "summary": "A host-commanded inference accelerator keeps dense matrix work close to software-managed buffers.",
      "config": "The first-generation TPU disclosed at ISCA2017; not a training TPU or later pod.",
      "gaps": [
        "The array has no general sparse execution support in this generation.",
        "The graph aggregates matrix cells; it does not display individual MAC timing."
      ],
      "insight": "Where does each weight, activation, and partial sum travel?",
      "fields": {
        "state": {
          "value": "8-bit integer MACs;32-bit accumulators",
          "source": "parallel-tpu1",
          "locator": "§2"
        },
        "compute": {
          "value": "256×256 systolic matrix unit",
          "source": "parallel-tpu1",
          "locator": "§2, Figures1/4"
        },
        "memory": {
          "value": "24MiB Unified Buffer;4MiB accumulators;8GiB weight DRAM",
          "source": "parallel-tpu1",
          "locator": "§2"
        },
        "control": {
          "value": "Host-issued instructions over PCIe",
          "source": "parallel-tpu1",
          "locator": "§2"
        },
        "io": {
          "value": "PCIeGen3×16 and programmable DMA",
          "source": "parallel-tpu1",
          "locator": "§2"
        },
        "software": {
          "value": "TensorFlow API, user-space and kernel drivers",
          "source": "parallel-tpu1",
          "locator": "§2, software stack"
        },
        "workload": {
          "value": "Quantized NN inference",
          "source": "parallel-tpu1",
          "locator": "§§1–2"
        }
      },
      "diagram": {
        "title": "Weights and activations meet in a systolic datapath",
        "scope": "Selected paths from Figure1; instructions and DMA are distinct from arithmetic.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "host",
            "label": "Host CPU / memory",
            "subtitle": "APPLICATION + DRIVER",
            "text": "Sends TPU commands.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-tpu1",
            "locator": "§2",
            "control": true
          },
          {
            "id": "pcie",
            "label": "PCIe interface",
            "subtitle": "GEN3×16",
            "text": "Host attachment.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-tpu1",
            "locator": "§2",
            "control": false
          },
          {
            "id": "inst",
            "label": "Instruction buffer",
            "subtitle": "HOST-ISSUED COMMANDS",
            "text": "Controls accelerator execution.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-tpu1",
            "locator": "§2",
            "control": true
          },
          {
            "id": "dma",
            "label": "DMA controller",
            "subtitle": "HOST TRANSFERS",
            "text": "Moves activation data.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-tpu1",
            "locator": "§2",
            "control": false
          },
          {
            "id": "ub",
            "label": "Unified Buffer",
            "subtitle": "24MiB SRAM",
            "text": "Activations and intermediates.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-tpu1",
            "locator": "§2",
            "control": false
          },
          {
            "id": "matrix",
            "label": "Matrix Multiply Unit",
            "subtitle": "256×256 MACs",
            "text": "Systolic dense computation.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-tpu1",
            "locator": "§2, Fig.1",
            "control": false
          },
          {
            "id": "dram",
            "label": "Weight Memory",
            "subtitle": "8GiB DRAM",
            "text": "External model weights.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-tpu1",
            "locator": "§2",
            "control": false
          },
          {
            "id": "fifo",
            "label": "Weight FIFO",
            "subtitle": "TILE STAGING",
            "text": "Feeds matrix weights.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-tpu1",
            "locator": "§2",
            "control": false
          },
          {
            "id": "acc",
            "label": "Accumulators",
            "subtitle": "4MiB /32-BIT",
            "text": "Collects partial sums.",
            "x": 940,
            "y": 200,
            "w": 184,
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            "locator": "§2",
            "control": false
          },
          {
            "id": "activate",
            "label": "Activation / pooling",
            "subtitle": "NONLINEAR STAGE",
            "text": "Returns activations to UB.",
            "x": 940,
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            "from": "dram",
            "to": "fifo",
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            "from": "fifo",
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      "id": "queue-104",
      "name": "Google TPU v4 —4096-chip pod",
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        "parallel-tpu4"
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        "OCSes switch communication paths, not tensor arithmetic.",
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        },
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          "value": "ICI mesh/torus with optical circuit switches",
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      },
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        "title": "Chip compute, rack cubes, and optical topology",
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        "height": 530,
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          {
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            "h": 68,
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          },
          {
            "id": "hbm",
            "label": "HBM",
            "subtitle": "PACKAGE MEMORY",
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            "id": "ici",
            "label": "ICI links",
            "subtitle": "CHIP COMMUNICATION",
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            "w": 184,
            "h": 68,
            "source": "parallel-tpu4",
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            "control": false
          },
          {
            "id": "cube",
            "label": "4×4×4 chip block",
            "subtitle": "ELECTRICAL RACK MESH",
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            "y": 200,
            "w": 184,
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            "source": "parallel-tpu4",
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            "control": false
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            "id": "ocs",
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            "subtitle": "RECONFIGURABLE LINKS",
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            "w": 184,
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            "source": "parallel-tpu4",
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            "control": false
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          {
            "id": "other",
            "label": "Other64-chip blocks",
            "subtitle": "64 BLOCKS TOTAL",
            "text": "Forms4096-chip system.",
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            "h": 68,
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            "from": "cube",
            "to": "ocs",
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            "label": ""
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            "from": "ocs",
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            "from": "other",
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        ]
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      "originalCandidate": "Google TPU v4 pod"
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      "id": "queue-105",
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      "year": 2017,
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      "status": "dossier",
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        "parallel"
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        "simt",
        "smp",
        "distributed"
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        "integrated"
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        "register",
        "neural"
      ],
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        "parallel-dgx1-v100",
        "parallel-dgx1-guide"
      ],
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      "config": "V10016GB edition, eight GPUs/512GB host RAM; P100 and32GB variants excluded.",
      "gaps": [
        "Graph shows neighbor relationships; some edges contain two physical NVLinks."
      ],
      "insight": "Which GPU pairs have direct NVLink paths and which route through a peer?",
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        "state": {
          "value": "Xeon host and Volta GPU state",
          "source": "parallel-dgx1-v100",
          "locator": "System overview"
        },
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          "value": "Two20-core Xeons; eight V100s",
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        },
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          "value": "512GB host DDR4;16GB HBM2/GPU",
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        },
        "control": {
          "value": "Host software commands GPU work",
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        },
        "io": {
          "value": "Four EDR NICs and PCIe tree",
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        },
        "software": {
          "value": "Ubuntu, Docker, NVIDIA drivers",
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          "locator": "Introduction"
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        }
      },
      "diagram": {
        "title": "The actual eight-GPU hybrid cube-mesh",
        "scope": "CPU/PCIe domains grouped; each edge marked NVLink denotes direct bidirectional connectivity, not equal lane count.",
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        "nodes": [
          {
            "id": "c0",
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          },
          {
            "id": "c1",
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          },
          {
            "id": "g3",
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          {
            "id": "g0",
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          },
          {
            "id": "g4",
            "label": "V100 GPU4",
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            "source": "parallel-dgx1-v100",
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            "control": false
          },
          {
            "id": "g7",
            "label": "V100 GPU7",
            "subtitle": "16GB HBM2",
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            "y": 200,
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            "h": 68,
            "source": "parallel-dgx1-v100",
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          {
            "id": "g2",
            "label": "V100 GPU2",
            "subtitle": "16GB HBM2",
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            "y": 370,
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          },
          {
            "id": "g1",
            "label": "V100 GPU1",
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          {
            "id": "g6",
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            "type": "data",
            "source": "parallel-dgx1-v100",
            "locator": "Fig.4",
            "label": "NVLink",
            "bidirectional": true
          },
          {
            "from": "g1",
            "to": "g5",
            "type": "data",
            "source": "parallel-dgx1-v100",
            "locator": "Fig.4",
            "label": "NVLink",
            "bidirectional": true
          }
        ]
      },
      "originalCandidate": "NVIDIA DGX-1"
    },
    {
      "id": "queue-106",
      "name": "NVIDIA DGX H100 —640GB GPU configuration",
      "organization": "NVIDIA",
      "year": 2026,
      "yearLabel": "October2026 manual edition",
      "kind": "Commercial accelerator server configuration",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "heterogeneous",
        "simt",
        "smp",
        "distributed"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "neural"
      ],
      "aliases": [],
      "sources": [
        "parallel-dgxh100",
        "parallel-dgx-hopper-fabric"
      ],
      "summary": "Eight H100 GPUs use a four-switch NVLink fabric and individual cluster-network paths.",
      "config": "H100640GB model in October2026 manual; H200 is excluded.",
      "gaps": [
        "NVLink4 and third-generation NVSwitch are different generation labels."
      ],
      "insight": "How does switched GPU communication differ from DGX-1’s direct mesh?",
      "fields": {
        "state": {
          "value": "Xeon host and Hopper GPU state",
          "source": "parallel-dgxh100",
          "locator": "§1.1"
        },
        "compute": {
          "value": "Two56-core Xeon8480C CPUs; eight H100s",
          "source": "parallel-dgxh100",
          "locator": "§1.1"
        },
        "memory": {
          "value": "2TB host RAM;640GB total GPU memory",
          "source": "parallel-dgxh100",
          "locator": "§1.1"
        },
        "control": {
          "value": "DGX OS, drivers and fabric management",
          "source": "parallel-dgxh100",
          "locator": "§1.4"
        },
        "io": {
          "value": "Eight cluster ConnectX7s plus storage networking/NVMe",
          "source": "parallel-dgxh100",
          "locator": "§1.1"
        },
        "software": {
          "value": "Ubuntu, GPU driver and Container Toolkit",
          "source": "parallel-dgxh100",
          "locator": "§1.4"
        },
        "workload": {
          "value": "AI training, inference and analytics",
          "source": "parallel-dgxh100",
          "locator": "Introduction"
        }
      },
      "diagram": {
        "title": "PCIe host paths and switched GPU collectives",
        "scope": "GPU groups aggregate four devices each; every GPU connects to all four NVSwitches.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "c0",
            "label": "CPU0 /host memory",
            "subtitle": "XEON8480C",
            "text": "Runs host services for one PCIe/memory domain.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-dgxh100",
            "locator": "§§1.1/1.3",
            "control": false
          },
          {
            "id": "c1",
            "label": "CPU1 /host memory",
            "subtitle": "XEON8480C",
            "text": "Runs host services for the second domain.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-dgxh100",
            "locator": "§§1.1/1.3",
            "control": false
          },
          {
            "id": "pcie0",
            "label": "CPU0 PCIe domain",
            "subtitle": "HOST /DEVICE ACCESS",
            "text": "Connects CPU0 to accelerators and network devices.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "control": false
          },
          {
            "id": "pcie1",
            "label": "CPU1 PCIe domain",
            "subtitle": "HOST /DEVICE ACCESS",
            "text": "Connects CPU1 to accelerators and network devices.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "control": false
          },
          {
            "id": "g0",
            "label": "H100 GPUs0–3",
            "subtitle": "4 ×80GB",
            "text": "Groups four80GB H100 accelerator devices.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-dgxh100",
            "locator": "§§1.1/1.3",
            "control": false
          },
          {
            "id": "g1",
            "label": "H100 GPUs4–7",
            "subtitle": "4 ×80GB",
            "text": "Groups the other four80GB H100 devices.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-dgxh100",
            "locator": "§§1.1/1.3",
            "control": false
          },
          {
            "id": "sw",
            "label": "Four NVSwitches",
            "subtitle": "EIGHT-GPU NVLINK DOMAIN",
            "text": "Connects every GPU through four NVSwitch chips.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-dgx-hopper-fabric",
            "locator": "H100 system architecture",
            "control": false
          },
          {
            "id": "cx0",
            "label": "Cluster ConnectX7s0–3",
            "subtitle": "GPU NETWORK PATHS",
            "text": "Provides individual cluster interfaces for GPUs0–3.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "control": false
          },
          {
            "id": "cx1",
            "label": "Cluster ConnectX7s4–7",
            "subtitle": "GPU NETWORK PATHS",
            "text": "Provides individual cluster interfaces for GPUs4–7.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "control": false
          },
          {
            "id": "storage",
            "label": "NVMe /storage NICs",
            "subtitle": "PCIe DEVICES",
            "text": "Supplies local NVMe and separate storage networking.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "c0",
            "to": "c1",
            "type": "data",
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "label": "CPU link"
          },
          {
            "from": "c0",
            "to": "pcie0",
            "type": "data",
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "label": ""
          },
          {
            "from": "c1",
            "to": "pcie1",
            "type": "data",
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "label": ""
          },
          {
            "from": "pcie0",
            "to": "g0",
            "type": "data",
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "label": ""
          },
          {
            "from": "pcie1",
            "to": "g1",
            "type": "data",
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "label": ""
          },
          {
            "from": "g0",
            "to": "sw",
            "type": "data",
            "source": "parallel-dgx-hopper-fabric",
            "locator": "H100 system architecture",
            "label": "NVLink"
          },
          {
            "from": "sw",
            "to": "g0",
            "type": "data",
            "source": "parallel-dgx-hopper-fabric",
            "locator": "H100 system architecture",
            "label": ""
          },
          {
            "from": "g1",
            "to": "sw",
            "type": "data",
            "source": "parallel-dgx-hopper-fabric",
            "locator": "H100 system architecture",
            "label": "NVLink"
          },
          {
            "from": "sw",
            "to": "g1",
            "type": "data",
            "source": "parallel-dgx-hopper-fabric",
            "locator": "H100 system architecture",
            "label": ""
          },
          {
            "from": "g0",
            "to": "cx0",
            "type": "data",
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "label": ""
          },
          {
            "from": "g1",
            "to": "cx1",
            "type": "data",
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "label": ""
          },
          {
            "from": "pcie0",
            "to": "storage",
            "type": "data",
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "label": ""
          },
          {
            "from": "pcie1",
            "to": "storage",
            "type": "data",
            "source": "parallel-dgxh100",
            "locator": "§1.3",
            "label": ""
          }
        ]
      },
      "originalCandidate": "NVIDIA DGX H100"
    },
    {
      "id": "queue-107",
      "name": "NVIDIA GB200 NVL72 —DGX reference rack",
      "organization": "NVIDIA",
      "year": 2025,
      "yearLabel": "November2025 reference architecture",
      "kind": "Commercial rack reference configuration",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "heterogeneous",
        "simt",
        "distributed",
        "numa"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "neural"
      ],
      "aliases": [],
      "sources": [
        "parallel-gb200-components",
        "parallel-gb200-network"
      ],
      "summary": "Eighteen Grace/Blackwell compute trays share one72-GPU switched NVLink domain, with distinct external network fabrics.",
      "config": "DGX GB20072×1 rack:36 Grace CPUs,72 B200 GPUs, nine two-chip switch trays.",
      "gaps": [
        "A72-GPU NVLink domain spans multiple OS instances.",
        "GB300 and OEM variants are excluded."
      ],
      "insight": "Which links scale up within a rack and which scale out to other racks?",
      "fields": {
        "state": {
          "value": "Grace CPU and Blackwell GPU state",
          "source": "parallel-gb200-components",
          "locator": "Compute Tray"
        },
        "compute": {
          "value": "Two Grace/four B200 GPUs per tray",
          "source": "parallel-gb200-components",
          "locator": "Compute Tray"
        },
        "memory": {
          "value": "CPU-attached memory and GPU HBM",
          "source": "parallel-gb200-components",
          "locator": "Figure5"
        },
        "control": {
          "value": "One OS instance/tray; NMX/Mission Control",
          "source": "parallel-gb200-components",
          "locator": "Compute Tray; Tables1–2"
        },
        "io": {
          "value": "ConnectX7 compute; BlueField3 storage/management",
          "source": "parallel-gb200-components",
          "locator": "Compute Tray"
        },
        "software": {
          "value": "Mission Control, CUDA containers and Slurm",
          "source": "parallel-gb200-components",
          "locator": "Table2"
        },
        "workload": {
          "value": "Large model training/inference and HPC",
          "source": "parallel-gb200-components",
          "locator": "System Design"
        }
      },
      "diagram": {
        "title": "Tray coherence, rack NVLink, and external fabrics",
        "scope": "One tray expanded; rack GPU domain includes17 other trays. NVLink switches are distinct from InfiniBand switches.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "gr0",
            "label": "Tray:Grace CPU0/memory",
            "subtitle": "FIRST SUPERCHIP",
            "text": "Runs one Grace host domain in the expanded tray.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-gb200-components",
            "locator": "Figure5",
            "control": false
          },
          {
            "id": "gr1",
            "label": "Tray:Grace CPU1/memory",
            "subtitle": "SECOND SUPERCHIP",
            "text": "Runs the tray’s second Grace host domain.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-gb200-components",
            "locator": "Figure5",
            "control": false
          },
          {
            "id": "gp0",
            "label": "B200 GPUs0–1 /HBM",
            "subtitle": "NVLINK-C2C ATTACHED",
            "text": "Groups two Blackwell GPUs attached to Grace0.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-gb200-components",
            "locator": "Figure5",
            "control": false
          },
          {
            "id": "gp1",
            "label": "B200 GPUs2–3 /HBM",
            "subtitle": "NVLINK-C2C ATTACHED",
            "text": "Groups two Blackwell GPUs attached to Grace1.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-gb200-components",
            "locator": "Figure5",
            "control": false
          },
          {
            "id": "switch",
            "label": "Nine NVLink switch trays",
            "subtitle": "18 SWITCH CHIPS",
            "text": "Connects all72 rack GPUs through eighteen switch chips.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-gb200-network",
            "locator": "Multi-node NVLink",
            "control": false
          },
          {
            "id": "others",
            "label": "Other17 compute trays",
            "subtitle": "68 OTHER GPUs",
            "text": "Adds the remaining68 GPUs in seventeen trays.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-gb200-network",
            "locator": "Multi-node NVLink",
            "control": false
          },
          {
            "id": "cx",
            "label": "Four ConnectX7 NICs",
            "subtitle": "COMPUTE FABRIC",
            "text": "Carries compute traffic beyond the rack.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-gb200-components",
            "locator": "Compute Tray",
            "control": false
          },
          {
            "id": "ib",
            "label": "Inter-rack InfiniBand",
            "subtitle": "SCALE-OUT FABRIC",
            "text": "Connects multiple racks through InfiniBand.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-gb200-network",
            "locator": "Compute Fabric",
            "control": false
          },
          {
            "id": "bf",
            "label": "Two BlueField3 DPUs",
            "subtitle": "STORAGE /IN-BAND",
            "text": "Provides storage and infrastructure service offload.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-gb200-components",
            "locator": "Compute Tray",
            "control": false
          },
          {
            "id": "eth",
            "label": "Ethernet /OOB services",
            "subtitle": "STORAGE /CONTROL",
            "text": "Carries Ethernet services and out-of-band management.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-gb200-network",
            "locator": "Ethernet/OOB sections",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "gr0",
            "to": "gr1",
            "type": "data",
            "source": "parallel-gb200-components",
            "locator": "Figure5",
            "label": "C2C"
          },
          {
            "from": "gr0",
            "to": "gp0",
            "type": "data",
            "source": "parallel-gb200-components",
            "locator": "Figure5",
            "label": "NVLink-C2C"
          },
          {
            "from": "gr1",
            "to": "gp1",
            "type": "data",
            "source": "parallel-gb200-components",
            "locator": "Figure5",
            "label": "NVLink-C2C"
          },
          {
            "from": "gp0",
            "to": "switch",
            "type": "data",
            "source": "parallel-gb200-network",
            "locator": "Multi-node NVLink",
            "label": "NVLink5"
          },
          {
            "from": "gp1",
            "to": "switch",
            "type": "data",
            "source": "parallel-gb200-network",
            "locator": "Multi-node NVLink",
            "label": "NVLink5"
          },
          {
            "from": "switch",
            "to": "others",
            "type": "data",
            "source": "parallel-gb200-network",
            "locator": "Multi-node NVLink",
            "label": ""
          },
          {
            "from": "others",
            "to": "switch",
            "type": "data",
            "source": "parallel-gb200-network",
            "locator": "Multi-node NVLink",
            "label": ""
          },
          {
            "from": "gr0",
            "to": "cx",
            "type": "data",
            "source": "parallel-gb200-components",
            "locator": "Figure5",
            "label": "PCIe"
          },
          {
            "from": "gr1",
            "to": "cx",
            "type": "data",
            "source": "parallel-gb200-components",
            "locator": "Figure5",
            "label": "PCIe"
          },
          {
            "from": "cx",
            "to": "ib",
            "type": "data",
            "source": "parallel-gb200-components",
            "locator": "Compute Tray",
            "label": ""
          },
          {
            "from": "gr0",
            "to": "bf",
            "type": "data",
            "source": "parallel-gb200-components",
            "locator": "Figure5",
            "label": "PCIe"
          },
          {
            "from": "bf",
            "to": "eth",
            "type": "data",
            "source": "parallel-gb200-network",
            "locator": "Storage/In-band",
            "label": ""
          },
          {
            "from": "eth",
            "to": "switch",
            "type": "control",
            "source": "parallel-gb200-network",
            "locator": "Out-of-Band Management",
            "label": ""
          }
        ]
      },
      "originalCandidate": "NVIDIA GB200 NVL72"
    },
    {
      "id": "queue-108",
      "name": "Cerebras CS-2 — WSE-2 with weight streaming",
      "organization": "Cerebras Systems",
      "year": 2023,
      "yearLabel": "2023 detailed architecture description",
      "kind": "Commercial accelerator configuration",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "architectures": [
        "wafer-scale",
        "distributed",
        "dataflow-arch",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "dataflow-model",
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-cs2",
        "parallel-cs2-streaming"
      ],
      "summary": "A wafer-scale mesh combines local SRAM, tensor datapaths and data-triggered execution; external MemoryX supplies weights.",
      "config": "WSE-2/CS-2 weight-streaming organization described in2023; WSE-3 is excluded.",
      "gaps": [
        "External weight streaming is a particular execution mode.",
        "The graph omits SwarmX cluster replication."
      ],
      "insight": "Which tensors stay local while weights stream past?",
      "fields": {
        "state": {
          "value": "FP16/BF16 tensor operands with optional FP32 accumulation",
          "source": "parallel-cs2",
          "locator": "preprint pp.4–5"
        },
        "compute": {
          "value": "850,000 cores; four16-bit FMACs/core",
          "source": "parallel-cs2",
          "locator": "Overview; Programmability"
        },
        "memory": {
          "value": "48KB local SRAM/core plus256-byte software-managed cache",
          "source": "parallel-cs2",
          "locator": "Memory; Fig.3"
        },
        "control": {
          "value": "Fabric events trigger instructions; eight tensor microthreads",
          "source": "parallel-cs2",
          "locator": "Fine-Grained Data Flow Scheduling"
        },
        "io": {
          "value": "Weight/gradient streaming to MemoryX",
          "source": "parallel-cs2-streaming",
          "locator": "Weight Streaming"
        },
        "software": {
          "value": "Compiler lowers TensorFlow/PyTorch programs",
          "source": "parallel-cs2",
          "locator": "Programmability"
        },
        "workload": {
          "value": "Sparse/dense neural-network training",
          "source": "parallel-cs2-streaming",
          "locator": "Weight Streaming"
        }
      },
      "diagram": {
        "title": "Local activations, colored mesh, streamed weights",
        "scope": "One expanded core and aggregated wafer fabric; MemoryX is external.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "sram",
            "label": "Local SRAM",
            "subtitle": "48KB /CORE",
            "text": "Stores instructions and local tensor data.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cs2",
            "locator": "Memory; Fig.3",
            "control": false
          },
          {
            "id": "cache",
            "label": "Software-managed cache",
            "subtitle": "256 BYTES",
            "text": "Keeps frequently updated accumulators near arithmetic.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-cs2",
            "locator": "Memory; Fig.3",
            "control": false
          },
          {
            "id": "instr",
            "label": "Instruction pipeline",
            "subtitle": "LOCAL CORE PROGRAM",
            "text": "Executes local control and tensor instructions.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cs2",
            "locator": "Programmability",
            "control": false
          },
          {
            "id": "dsr",
            "label": "Data structure registers",
            "subtitle": "TENSOR DESCRIPTORS",
            "text": "Describe memory or fabric tensor operands.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cs2",
            "locator": "Programmability; Fig.5",
            "control": false
          },
          {
            "id": "sched",
            "label": "Dataflow scheduler",
            "subtitle": "EIGHT MICROTHREADS",
            "text": "Selects work when tensor inputs/outputs permit.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-cs2",
            "locator": "Fine-Grained Data Flow Scheduling",
            "control": true
          },
          {
            "id": "fmac",
            "label": "Tensor datapath",
            "subtitle": "FOUR16-BIT FMACs",
            "text": "Combines streamed weights with resident activations.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cs2",
            "locator": "Programmability; Fig.6",
            "control": false
          },
          {
            "id": "router",
            "label": "Five-port core router",
            "subtitle": "24 ROUTING COLORS",
            "text": "Routes local/cardinal traffic and multicasts.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cs2",
            "locator": "Scale-Up; Fig.8",
            "control": false
          },
          {
            "id": "wafer",
            "label": "Other wafer cores",
            "subtitle": "2D MESH /DIE CROSSINGS",
            "text": "Explicit fabric transfers connect distributed memories.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-cs2",
            "locator": "Scale-Up; Figs.7–8",
            "control": false
          },
          {
            "id": "stream",
            "label": "CS-2 streaming interface",
            "subtitle": "WEIGHTS /GRADIENTS",
            "text": "Feeds weights and returns backward-pass gradients.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-cs2-streaming",
            "locator": "Weight Streaming",
            "control": false
          },
          {
            "id": "mx",
            "label": "External MemoryX",
            "subtitle": "WEIGHTS /OPTIMIZER STATE",
            "text": "Stores and updates weights outside the wafer.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-cs2-streaming",
            "locator": "Weight Streaming",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "sram",
            "to": "instr",
            "type": "data",
            "source": "parallel-cs2",
            "locator": "Programmability",
            "label": ""
          },
          {
            "from": "instr",
            "to": "dsr",
            "type": "control",
            "source": "parallel-cs2",
            "locator": "Programmability",
            "label": ""
          },
          {
            "from": "dsr",
            "to": "fmac",
            "type": "control",
            "source": "parallel-cs2",
            "locator": "Fig.5",
            "label": ""
          },
          {
            "from": "sram",
            "to": "fmac",
            "type": "data",
            "source": "parallel-cs2",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "fmac",
            "to": "cache",
            "type": "data",
            "source": "parallel-cs2-streaming",
            "locator": "Weight Streaming",
            "label": ""
          },
          {
            "from": "cache",
            "to": "fmac",
            "type": "data",
            "source": "parallel-cs2-streaming",
            "locator": "Weight Streaming",
            "label": ""
          },
          {
            "from": "router",
            "to": "sched",
            "type": "control",
            "source": "parallel-cs2",
            "locator": "Fig.6",
            "label": ""
          },
          {
            "from": "sched",
            "to": "instr",
            "type": "control",
            "source": "parallel-cs2",
            "locator": "Fine-Grained Data Flow Scheduling",
            "label": ""
          },
          {
            "from": "router",
            "to": "fmac",
            "type": "data",
            "source": "parallel-cs2",
            "locator": "Fig.6",
            "label": "fabric operand"
          },
          {
            "from": "fmac",
            "to": "router",
            "type": "data",
            "source": "parallel-cs2",
            "locator": "Fig.6",
            "label": ""
          },
          {
            "from": "router",
            "to": "wafer",
            "type": "data",
            "source": "parallel-cs2",
            "locator": "Fig.8",
            "label": ""
          },
          {
            "from": "wafer",
            "to": "router",
            "type": "data",
            "source": "parallel-cs2",
            "locator": "Fig.8",
            "label": ""
          },
          {
            "from": "mx",
            "to": "stream",
            "type": "data",
            "source": "parallel-cs2-streaming",
            "locator": "Weight Streaming",
            "label": "weights"
          },
          {
            "from": "stream",
            "to": "router",
            "type": "data",
            "source": "parallel-cs2-streaming",
            "locator": "Weight Streaming",
            "label": ""
          },
          {
            "from": "router",
            "to": "stream",
            "type": "data",
            "source": "parallel-cs2-streaming",
            "locator": "Weight Streaming",
            "label": ""
          },
          {
            "from": "stream",
            "to": "mx",
            "type": "data",
            "source": "parallel-cs2-streaming",
            "locator": "Weight Streaming",
            "label": "gradients"
          }
        ]
      },
      "originalCandidate": "Cerebras CS-2"
    },
    {
      "id": "queue-109",
      "name": "Graphcore IPU-M2000 — standalone GC200 configuration",
      "organization": "Graphcore",
      "year": 2020,
      "yearLabel": "30September2020 datasheet version1.0",
      "kind": "Commercial accelerator system",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "distributed",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-m2000",
        "parallel-gc200",
        "parallel-ipu-bsp"
      ],
      "summary": "Four GC200 IPUs combine tile-local SRAM and explicit exchange with a separate host and streaming-memory service.",
      "config": "One M2000 with default2×64GB DDR4, external Poplar host and RoCEv2 link; Bow variants excluded.",
      "gaps": [
        "128GB is the default module capacity, not the maximum advertised addressable Exchange Memory.",
        "The graph aggregates internal link wiring; no specific POD topology is implied."
      ],
      "insight": "Why separate tile computation from synchronized exchange?",
      "fields": {
        "state": {
          "value": "FP32 and mixed FP16 accumulation formats",
          "source": "parallel-gc200",
          "locator": "Compute"
        },
        "compute": {
          "value": "Four IPUs;1472 independent cores/IPU",
          "source": "parallel-gc200",
          "locator": "Compute"
        },
        "memory": {
          "value": "3.6GB on-IPU SRAM plus128GB default streaming DDR4",
          "source": "parallel-m2000",
          "locator": "§3.2"
        },
        "control": {
          "value": "Bulk-synchronous compute, synchronization, exchange phases",
          "source": "parallel-ipu-bsp",
          "locator": "BSP trace description"
        },
        "io": {
          "value": "RoCEv2 host link; IPU-Link and GW-Link scaling",
          "source": "parallel-m2000",
          "locator": "§§2,3.2"
        },
        "software": {
          "value": "Poplar builds compute, memory and communication programs",
          "source": "parallel-gc200",
          "locator": "Poplar description"
        },
        "workload": {
          "value": "Machine-learning training and inference",
          "source": "parallel-m2000",
          "locator": "§2"
        }
      },
      "diagram": {
        "title": "Tile-local computation and fabric-mediated exchange",
        "scope": "IPU0 expanded logically; three peers aggregated. Gateway relationships show services rather than board traces.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "host",
            "label": "Poplar host",
            "subtitle": "EXTERNAL SERVER",
            "text": "Compiles and launches accelerator graph programs.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-m2000",
            "locator": "§3.1.1",
            "control": false
          },
          {
            "id": "nic",
            "label": "RoCEv2 host link",
            "subtitle": "100GbE /PCIe NIC",
            "text": "Carries IPU-over-Fabric host communication.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-m2000",
            "locator": "§§2,3.1.1",
            "control": false
          },
          {
            "id": "gw",
            "label": "GC4000 IPU-Gateway",
            "subtitle": "SYSTEM COMMUNICATION",
            "text": "Provides M2000 fabric and host connectivity.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-gc200",
            "locator": "Communication",
            "control": false
          },
          {
            "id": "ddr",
            "label": "Streaming DDR4",
            "subtitle": "DEFAULT2×64GB",
            "text": "Holds data streamed under Poplar control.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-m2000",
            "locator": "§3.2",
            "control": false
          },
          {
            "id": "tile",
            "label": "IPU0 tile cores",
            "subtitle": "1472 INDEPENDENT CORES",
            "text": "Each core executes its assigned program.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-gc200",
            "locator": "Compute",
            "control": false
          },
          {
            "id": "local",
            "label": "IPU0 local SRAM",
            "subtitle": "900MB DISTRIBUTED",
            "text": "Memory sits beside each processor core.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-gc200",
            "locator": "Data",
            "control": false
          },
          {
            "id": "exchange",
            "label": "IPU exchange fabric",
            "subtitle": "EXPLICIT DATA EXCHANGE",
            "text": "Moves graph data during exchange phases.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-gc200",
            "locator": "Data; Poplar description",
            "control": false
          },
          {
            "id": "peer",
            "label": "Other three GC200s",
            "subtitle": "PEER COMPUTATION",
            "text": "Extend graph placement across the blade.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-m2000",
            "locator": "§§2,3.2",
            "control": false
          },
          {
            "id": "sync",
            "label": "BSP synchronization",
            "subtitle": "DEDICATED SIGNALING",
            "text": "Coordinates completion before data exchange.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-m2000",
            "locator": "§2",
            "control": true
          },
          {
            "id": "scale",
            "label": "IPU-Link /GW-Link",
            "subtitle": "EXTERNAL SCALING",
            "text": "Connects other IPUs and M2000 systems.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-m2000",
            "locator": "§3.2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "nic",
            "type": "data",
            "source": "parallel-m2000",
            "locator": "§3.1.1",
            "label": ""
          },
          {
            "from": "nic",
            "to": "host",
            "type": "data",
            "source": "parallel-m2000",
            "locator": "§3.1.1",
            "label": ""
          },
          {
            "from": "nic",
            "to": "gw",
            "type": "association",
            "source": "parallel-m2000",
            "locator": "§2",
            "label": "host service"
          },
          {
            "from": "gw",
            "to": "ddr",
            "type": "association",
            "source": "parallel-m2000",
            "locator": "§§2,3.2",
            "label": "streaming-memory service"
          },
          {
            "from": "ddr",
            "to": "exchange",
            "type": "data",
            "source": "parallel-gc200",
            "locator": "Data",
            "label": "explicit streaming"
          },
          {
            "from": "exchange",
            "to": "ddr",
            "type": "data",
            "source": "parallel-gc200",
            "locator": "Data",
            "label": ""
          },
          {
            "from": "local",
            "to": "tile",
            "type": "data",
            "source": "parallel-gc200",
            "locator": "Data",
            "label": ""
          },
          {
            "from": "tile",
            "to": "local",
            "type": "data",
            "source": "parallel-gc200",
            "locator": "Data",
            "label": ""
          },
          {
            "from": "local",
            "to": "exchange",
            "type": "data",
            "source": "parallel-gc200",
            "locator": "Data",
            "label": ""
          },
          {
            "from": "exchange",
            "to": "local",
            "type": "data",
            "source": "parallel-gc200",
            "locator": "Data",
            "label": ""
          },
          {
            "from": "exchange",
            "to": "peer",
            "type": "data",
            "source": "parallel-m2000",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "peer",
            "to": "exchange",
            "type": "data",
            "source": "parallel-m2000",
            "locator": "§2",
            "label": ""
          },
          {
            "from": "sync",
            "to": "tile",
            "type": "control",
            "source": "parallel-ipu-bsp",
            "locator": "BSP trace description",
            "label": ""
          },
          {
            "from": "sync",
            "to": "exchange",
            "type": "control",
            "source": "parallel-ipu-bsp",
            "locator": "BSP trace description",
            "label": ""
          },
          {
            "from": "gw",
            "to": "scale",
            "type": "association",
            "source": "parallel-gc200",
            "locator": "Communication",
            "label": ""
          },
          {
            "from": "peer",
            "to": "scale",
            "type": "association",
            "source": "parallel-m2000",
            "locator": "§3.2",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Graphcore IPU systems"
    },
    {
      "id": "queue-110",
      "name": "Groq TSP — first-generation PCIe ASIC",
      "organization": "Groq",
      "year": 2020,
      "yearLabel": "ISCA2020 first implementation",
      "kind": "Built accelerator processor/card",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "architectures": [
        "simd",
        "systolic",
        "dataflow-arch",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "parallel-groq-tsp"
      ],
      "summary": "Scheduled instructions move vertically while register streams move horizontally across functional slices.",
      "config": "2020 first-generation ASIC; later multi-TSP systems excluded.",
      "gaps": [
        "Indexed paper inspected; author mirror TLS expired.",
        "The graph aggregates repeated superlanes."
      ],
      "insight": "Where must an instruction meet its operand stream?",
      "fields": {
        "state": {
          "value": "int8/FP16 operands; INT32/FP32 matrix results",
          "source": "parallel-groq-tsp",
          "locator": "§III-D"
        },
        "compute": {
          "value": "VXM vector ALUs and four MXM arrays",
          "source": "parallel-groq-tsp",
          "locator": "§II"
        },
        "memory": {
          "value": "220MiB SRAM across88 MEM slices",
          "source": "parallel-groq-tsp",
          "locator": "§II-B"
        },
        "control": {
          "value": "144 compiler-scheduled instruction queues",
          "source": "parallel-groq-tsp",
          "locator": "§§II,III-A"
        },
        "io": {
          "value": "PCIe Gen4 DMA and C2C links",
          "source": "parallel-groq-tsp",
          "locator": "§II"
        },
        "software": {
          "value": "Compiler schedules producer-consumer streams",
          "source": "parallel-groq-tsp",
          "locator": "§III"
        },
        "workload": {
          "value": "Neural-network tensor operations",
          "source": "parallel-groq-tsp",
          "locator": "§I"
        }
      },
      "diagram": {
        "title": "Orthogonal instruction and data streams",
        "scope": "Functional relationships, not a complete floorplan.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "icu",
            "label": "Instruction control units",
            "subtitle": "144 QUEUES",
            "text": "Dispatch timed instructions into slices.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-groq-tsp",
            "locator": "§III-A",
            "control": false
          },
          {
            "id": "west",
            "label": "West MEM slices",
            "subtitle": "44 SRAM SLICES",
            "text": "Load/store vectors onto streams.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-groq-tsp",
            "locator": "§II-B",
            "control": false
          },
          {
            "id": "east",
            "label": "East MEM slices",
            "subtitle": "44 SRAM SLICES",
            "text": "Provide the second memory hemisphere.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-groq-tsp",
            "locator": "§II-B",
            "control": false
          },
          {
            "id": "sr",
            "label": "Streaming registers",
            "subtitle": "EAST /WEST",
            "text": "Carry operands between slices.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-groq-tsp",
            "locator": "§I-B",
            "control": false
          },
          {
            "id": "vxm",
            "label": "VXM",
            "subtitle": "VECTOR ALUs",
            "text": "Performs elementwise operations.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-groq-tsp",
            "locator": "§III-C",
            "control": false
          },
          {
            "id": "sxm",
            "label": "SXM",
            "subtitle": "PERMUTE /SHIFT",
            "text": "Rearranges lanes and streams.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-groq-tsp",
            "locator": "§III-E",
            "control": false
          },
          {
            "id": "mxm",
            "label": "MXM arrays",
            "subtitle": "MATRIX MULTIPLY",
            "text": "Consumes weights and activations.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-groq-tsp",
            "locator": "§III-D",
            "control": false
          },
          {
            "id": "c2c",
            "label": "C2C module",
            "subtitle": "VECTOR SEND /RECEIVE",
            "text": "Transfers vectors between chips.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-groq-tsp",
            "locator": "§II",
            "control": false
          },
          {
            "id": "host",
            "label": "PCIe host /DMA",
            "subtitle": "MODEL LOADING",
            "text": "Initializes memory and execution.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-groq-tsp",
            "locator": "§II",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "west",
            "to": "sr",
            "type": "data",
            "source": "parallel-groq-tsp",
            "locator": "§II-B",
            "label": ""
          },
          {
            "from": "sr",
            "to": "west",
            "type": "data",
            "source": "parallel-groq-tsp",
            "locator": "§II-B",
            "label": ""
          },
          {
            "from": "east",
            "to": "sr",
            "type": "data",
            "source": "parallel-groq-tsp",
            "locator": "§II-B",
            "label": ""
          },
          {
            "from": "sr",
            "to": "east",
            "type": "data",
            "source": "parallel-groq-tsp",
            "locator": "§II-B",
            "label": ""
          },
          {
            "from": "sr",
            "to": "vxm",
            "type": "data",
            "source": "parallel-groq-tsp",
            "locator": "§III-C",
            "label": ""
          },
          {
            "from": "vxm",
            "to": "sr",
            "type": "data",
            "source": "parallel-groq-tsp",
            "locator": "§III-C",
            "label": ""
          },
          {
            "from": "sr",
            "to": "sxm",
            "type": "data",
            "source": "parallel-groq-tsp",
            "locator": "§III-E",
            "label": ""
          },
          {
            "from": "sxm",
            "to": "sr",
            "type": "data",
            "source": "parallel-groq-tsp",
            "locator": "§III-E",
            "label": ""
          },
          {
            "from": "sr",
            "to": "mxm",
            "type": "data",
            "source": "parallel-groq-tsp",
            "locator": "§III-D",
            "label": ""
          },
          {
            "from": "mxm",
            "to": "sr",
            "type": "data",
            "source": "parallel-groq-tsp",
            "locator": "§III-D",
            "label": ""
          },
          {
            "from": "icu",
            "to": "west",
            "type": "control",
            "source": "parallel-groq-tsp",
            "locator": "§I-A",
            "label": ""
          },
          {
            "from": "icu",
            "to": "east",
            "type": "control",
            "source": "parallel-groq-tsp",
            "locator": "§I-A",
            "label": ""
          },
          {
            "from": "icu",
            "to": "vxm",
            "type": "control",
            "source": "parallel-groq-tsp",
            "locator": "§I-A",
            "label": ""
          },
          {
            "from": "icu",
            "to": "mxm",
            "type": "control",
            "source": "parallel-groq-tsp",
            "locator": "§I-A",
            "label": ""
          },
          {
            "from": "sr",
            "to": "icu",
            "type": "data",
            "source": "parallel-groq-tsp",
            "locator": "§III-A.3",
            "label": "instruction fetch"
          },
          {
            "from": "host",
            "to": "west",
            "type": "association",
            "source": "parallel-groq-tsp",
            "locator": "§II",
            "label": "DMA loading"
          },
          {
            "from": "c2c",
            "to": "sr",
            "type": "association",
            "source": "parallel-groq-tsp",
            "locator": "§II",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Groq TSP systems"
    },
    {
      "id": "queue-111",
      "name": "Anton2 — 512-node SC14 system",
      "organization": "D. E. Shaw Research",
      "year": 2014,
      "yearLabel": "SC14 operational configuration",
      "kind": "Built special-purpose supercomputer",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "architectures": [
        "distributed",
        "heterogeneous",
        "simd",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "parallel-anton2"
      ],
      "summary": "Event-driven geometry cores overlap molecular-dynamics tasks with specialized pairwise pipelines.",
      "config": "512-node machine reported operational in2014.",
      "gaps": [
        "Primary paper inspected through mirrored transcription.",
        "4096 nodes is an architectural limit, not this installation."
      ],
      "insight": "How do arriving force results enable integration tasks?",
      "fields": {
        "state": {
          "value": "128-bit communication quads;32-bit geometry cores",
          "source": "parallel-anton2",
          "locator": "§§IV-A,V"
        },
        "compute": {
          "value": "66 geometry cores and76 PPIMs/node",
          "source": "parallel-anton2",
          "locator": "Table1"
        },
        "memory": {
          "value": "Distributed SRAM and local caches",
          "source": "parallel-anton2",
          "locator": "Figs.3–4"
        },
        "control": {
          "value": "Counted writes and dispatch thresholds",
          "source": "parallel-anton2",
          "locator": "§IV-A"
        },
        "io": {
          "value": "PCIe host;3D torus among ASICs",
          "source": "parallel-anton2",
          "locator": "§III"
        },
        "software": {
          "value": "Embedded C++ via ported GCC",
          "source": "parallel-anton2",
          "locator": "§V"
        },
        "workload": {
          "value": "All-atom molecular dynamics",
          "source": "parallel-anton2",
          "locator": "§II"
        }
      },
      "diagram": {
        "title": "Fine-grained dispatch and pairwise interaction streaming",
        "scope": "One flex tile and one HTIS expanded; repeated tiles aggregated.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "gc",
            "label": "Flex geometry cores",
            "subtitle": "FOUR /FLEX TILE",
            "text": "Integrate positions and compute bond terms.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-anton2",
            "locator": "Figs.2,4",
            "control": false
          },
          {
            "id": "ram",
            "label": "Flex SRAM",
            "subtitle": "256KB /TILE",
            "text": "Receives counted remote writes.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-anton2",
            "locator": "Figs.4,6",
            "control": false
          },
          {
            "id": "dispatch",
            "label": "Dispatch unit",
            "subtitle": "READY-TASK COUNTERS",
            "text": "Releases tasks at input thresholds.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-anton2",
            "locator": "§IV-A",
            "control": true
          },
          {
            "id": "mesh",
            "label": "On-chip mesh",
            "subtitle": "FLEX /HTIS /HOST",
            "text": "Carries fine-grained data packets.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-anton2",
            "locator": "§III",
            "control": false
          },
          {
            "id": "mini",
            "label": "HTIS mini-flex core",
            "subtitle": "CONTROL SOFTWARE",
            "text": "Issues interaction-controller commands.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-anton2",
            "locator": "Fig.4b",
            "control": false
          },
          {
            "id": "icb",
            "label": "Interaction controller",
            "subtitle": "128 QUEUES /640KB",
            "text": "Sorts and streams atom/grid inputs.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-anton2",
            "locator": "Fig.4b",
            "control": false
          },
          {
            "id": "ppim",
            "label": "PPIM array",
            "subtitle": "38 /HTIS TILE",
            "text": "Computes pairwise force interactions.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-anton2",
            "locator": "Fig.4b",
            "control": false
          },
          {
            "id": "tiles",
            "label": "Other computational tiles",
            "subtitle": "16 FLEX +2 HTIS TOTAL",
            "text": "Supply remaining node parallelism.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-anton2",
            "locator": "Fig.3",
            "control": false
          },
          {
            "id": "torus",
            "label": "3D torus channels",
            "subtitle": "SIX NEIGHBORS",
            "text": "Connects512 ASIC nodes.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-anton2",
            "locator": "§III",
            "control": false
          },
          {
            "id": "host",
            "label": "External host",
            "subtitle": "PCI EXPRESS",
            "text": "Provides host system access.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-anton2",
            "locator": "§III",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "ram",
            "to": "gc",
            "type": "data",
            "source": "parallel-anton2",
            "locator": "Fig.4a",
            "label": ""
          },
          {
            "from": "gc",
            "to": "ram",
            "type": "data",
            "source": "parallel-anton2",
            "locator": "Fig.4a",
            "label": ""
          },
          {
            "from": "ram",
            "to": "dispatch",
            "type": "control",
            "source": "parallel-anton2",
            "locator": "Fig.6",
            "label": "counted write"
          },
          {
            "from": "dispatch",
            "to": "gc",
            "type": "control",
            "source": "parallel-anton2",
            "locator": "Fig.6",
            "label": "ready task"
          },
          {
            "from": "mesh",
            "to": "ram",
            "type": "data",
            "source": "parallel-anton2",
            "locator": "Fig.6",
            "label": ""
          },
          {
            "from": "gc",
            "to": "mesh",
            "type": "data",
            "source": "parallel-anton2",
            "locator": "Fig.4a",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "icb",
            "type": "data",
            "source": "parallel-anton2",
            "locator": "§III",
            "label": ""
          },
          {
            "from": "mini",
            "to": "icb",
            "type": "control",
            "source": "parallel-anton2",
            "locator": "Fig.4b",
            "label": ""
          },
          {
            "from": "icb",
            "to": "ppim",
            "type": "data",
            "source": "parallel-anton2",
            "locator": "Fig.4b",
            "label": ""
          },
          {
            "from": "ppim",
            "to": "icb",
            "type": "data",
            "source": "parallel-anton2",
            "locator": "Fig.4b",
            "label": ""
          },
          {
            "from": "icb",
            "to": "mesh",
            "type": "data",
            "source": "parallel-anton2",
            "locator": "Fig.4b",
            "label": "force packets"
          },
          {
            "from": "mesh",
            "to": "tiles",
            "type": "data",
            "source": "parallel-anton2",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "tiles",
            "to": "mesh",
            "type": "data",
            "source": "parallel-anton2",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "mesh",
            "to": "torus",
            "type": "data",
            "source": "parallel-anton2",
            "locator": "§III",
            "label": ""
          },
          {
            "from": "torus",
            "to": "mesh",
            "type": "data",
            "source": "parallel-anton2",
            "locator": "§III",
            "label": ""
          },
          {
            "from": "host",
            "to": "mesh",
            "type": "association",
            "source": "parallel-anton2",
            "locator": "§III",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Anton 2"
    },
    {
      "id": "queue-112",
      "name": "GRAPE-6 — four-cluster system",
      "organization": "University of Tokyo / collaborators",
      "year": 2003,
      "yearLabel": "2003 designer paper configuration",
      "kind": "Built special-purpose computer",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "heterogeneous",
        "pipelined",
        "distributed",
        "hardwired"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-grape6"
      ],
      "summary": "Hosts integrate particle orbits; specialized chips predict source particles and reduce gravitational interactions.",
      "config": "Four clusters,16 boards/cluster,32 chips/board.",
      "gaps": [
        "GRAPE-6A is a different board.",
        "Pipeline numeric formats vary by operation."
      ],
      "insight": "Why broadcast target particles but reduce partial forces?",
      "fields": {
        "state": {
          "value": "Mixed fixed/floating precision by pipeline stage",
          "source": "parallel-grape6",
          "locator": "Table1"
        },
        "compute": {
          "value": "Six force pipelines/chip;2048 chips",
          "source": "parallel-grape6",
          "locator": "§3"
        },
        "memory": {
          "value": "Private particle memory/chip",
          "source": "parallel-grape6",
          "locator": "§2.3"
        },
        "control": {
          "value": "Host-selected timesteps and target particles",
          "source": "parallel-grape6",
          "locator": "§2.1"
        },
        "io": {
          "value": "Network boards; Gigabit Ethernet between clusters",
          "source": "parallel-grape6",
          "locator": "§2.2"
        },
        "software": {
          "value": "Host Hermite integration with hardware force calls",
          "source": "parallel-grape6",
          "locator": "§2.1"
        },
        "workload": {
          "value": "Collisional gravitational N-body simulation",
          "source": "parallel-grape6",
          "locator": "§1"
        }
      },
      "diagram": {
        "title": "Particle prediction and hierarchical force reduction",
        "scope": "One host/board path expanded; other boards and clusters aggregated.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "host",
            "label": "Host PC",
            "subtitle": "ORBIT INTEGRATION",
            "text": "Selects targets and integrates returned forces.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-grape6",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "nb",
            "label": "Network board",
            "subtitle": "BROADCAST /REDUCE",
            "text": "Combines forces from four boards.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-grape6",
            "locator": "§2.2",
            "control": false
          },
          {
            "id": "broadcast",
            "label": "Board broadcast",
            "subtitle": "TARGET PARTICLES",
            "text": "Sends target data to processor modules.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-grape6",
            "locator": "§2.3, Fig.4",
            "control": false
          },
          {
            "id": "memory",
            "label": "Chip particle memory",
            "subtitle": "SOURCE PARTICLES",
            "text": "Stores predictor coefficients per source particle.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-grape6",
            "locator": "§2.3",
            "control": false
          },
          {
            "id": "predict",
            "label": "Predictor pipeline",
            "subtitle": "CURRENT-TIME STATE",
            "text": "Predicts source positions and velocities.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-grape6",
            "locator": "§3",
            "control": false
          },
          {
            "id": "force",
            "label": "Six force pipelines",
            "subtitle": "FORCE /DERIVATIVE",
            "text": "Accumulates target interactions with sources.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-grape6",
            "locator": "§3, Figs.6–7",
            "control": false
          },
          {
            "id": "sum",
            "label": "Module /board adders",
            "subtitle": "PARTIAL FORCE REDUCTION",
            "text": "Sums results from32 chips.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-grape6",
            "locator": "§2.3, Figs.4–5",
            "control": false
          },
          {
            "id": "boards",
            "label": "Other processor boards",
            "subtitle": "16 /CLUSTER",
            "text": "Provide other source-particle subsets.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-grape6",
            "locator": "§2.2",
            "control": false
          },
          {
            "id": "ether",
            "label": "Inter-cluster Ethernet",
            "subtitle": "FOUR CLUSTERS",
            "text": "Exchanges host-updated particle data.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-grape6",
            "locator": "§2.2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "nb",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "nb",
            "to": "broadcast",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§2.3",
            "label": ""
          },
          {
            "from": "broadcast",
            "to": "force",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§2.1",
            "label": "target state"
          },
          {
            "from": "broadcast",
            "to": "memory",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§2.1",
            "label": "particle updates"
          },
          {
            "from": "memory",
            "to": "predict",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "predict",
            "to": "force",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§3",
            "label": ""
          },
          {
            "from": "force",
            "to": "sum",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§2.3",
            "label": ""
          },
          {
            "from": "sum",
            "to": "nb",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§2.3",
            "label": ""
          },
          {
            "from": "boards",
            "to": "nb",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "nb",
            "to": "boards",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "nb",
            "to": "host",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "host",
            "to": "ether",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "ether",
            "to": "host",
            "type": "data",
            "source": "parallel-grape6",
            "locator": "§2.2",
            "label": ""
          }
        ]
      },
      "originalCandidate": "GRAPE-6"
    },
    {
      "id": "queue-113",
      "name": "Ambric Am2045 — 2008 production device",
      "organization": "Ambric",
      "year": 2008,
      "yearLabel": "September2008 production description",
      "kind": "Commercial embedded parallel processor",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "architectures": [
        "mimd",
        "distributed",
        "reconfigurable"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "process",
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "parallel-am2045"
      ],
      "summary": "Sequential software objects exchange words through dedicated channels that synchronize by backpressure.",
      "config": "Production336-processor Am2045 described at HPEC2008.",
      "gaps": [
        "336 is the production count; earlier360-core claims excluded.",
        "Channels are circuit-switched, not packet-routed cache coherence."
      ],
      "insight": "How can a blocked channel synchronize two ordinary processors?",
      "fields": {
        "state": {
          "value": "32-bit streams; DSP64-bit accumulators",
          "source": "parallel-am2045",
          "locator": "slide21"
        },
        "compute": {
          "value": "336 processors in45 brics",
          "source": "parallel-am2045",
          "locator": "slide22"
        },
        "memory": {
          "value": "7.1Mbit distributed SRAM",
          "source": "parallel-am2045",
          "locator": "slide22"
        },
        "control": {
          "value": "Sends/receives stall on channel readiness",
          "source": "parallel-am2045",
          "locator": "slide19"
        },
        "io": {
          "value": "PCIe, two DDR2 controllers, GPIO, flash",
          "source": "parallel-am2045",
          "locator": "slide22"
        },
        "software": {
          "value": "aJava/aStruct and aDesigner tools",
          "source": "parallel-am2045",
          "locator": "slide24"
        },
        "workload": {
          "value": "Video, imaging, radio and network streams",
          "source": "parallel-am2045",
          "locator": "slides2,23"
        }
      },
      "diagram": {
        "title": "Software objects connected by self-synchronizing channels",
        "scope": "One bric expanded by role; external controller attachment aggregated.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "risc",
            "label": "Streaming RISC cores",
            "subtitle": "SEQUENTIAL OBJECTS",
            "text": "Execute independent object programs.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-am2045",
            "locator": "slides18,21",
            "control": false
          },
          {
            "id": "dsp",
            "label": "Streaming DSP cores",
            "subtitle": "DSP ARITHMETIC",
            "text": "Process streams with DSP extensions.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-am2045",
            "locator": "slide21",
            "control": false
          },
          {
            "id": "local",
            "label": "Processor local memories",
            "subtitle": "PRIVATE STATE",
            "text": "Hold each processor’s local program/state.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-am2045",
            "locator": "slides20–21",
            "control": false
          },
          {
            "id": "channel",
            "label": "Local channel interconnect",
            "subtitle": "REGISTERED WORD PATHS",
            "text": "Transfers words with ready/valid stalling.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-am2045",
            "locator": "slides19,21",
            "control": false
          },
          {
            "id": "ru",
            "label": "RAM banks /engines",
            "subtitle": "DISTRIBUTED RAM UNITS",
            "text": "Supply memory through channel interfaces.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-am2045",
            "locator": "slide21",
            "control": false
          },
          {
            "id": "hops",
            "label": "Bric-hopping channels",
            "subtitle": "CONFIGURED CIRCUITS",
            "text": "Carry dedicated channels across brics.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-am2045",
            "locator": "slide21",
            "control": false
          },
          {
            "id": "array",
            "label": "Other brics",
            "subtitle": "45-BRIC DEVICE",
            "text": "Execute other mapped software objects.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-am2045",
            "locator": "slide22",
            "control": false
          },
          {
            "id": "ddr",
            "label": "Two DDR2 controllers",
            "subtitle": "EXTERNAL STREAM STORAGE",
            "text": "Provide external DRAM interfaces.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-am2045",
            "locator": "slide22",
            "control": false
          },
          {
            "id": "io",
            "label": "PCIe /GPIO /flash",
            "subtitle": "DEVICE INTERFACES",
            "text": "Connect host and streaming peripherals.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-am2045",
            "locator": "slide22",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "local",
            "to": "risc",
            "type": "data",
            "source": "parallel-am2045",
            "locator": "slide21",
            "label": ""
          },
          {
            "from": "local",
            "to": "dsp",
            "type": "data",
            "source": "parallel-am2045",
            "locator": "slide21",
            "label": ""
          },
          {
            "from": "risc",
            "to": "channel",
            "type": "data",
            "source": "parallel-am2045",
            "locator": "slides19,21",
            "label": ""
          },
          {
            "from": "channel",
            "to": "risc",
            "type": "data",
            "source": "parallel-am2045",
            "locator": "slides19,21",
            "label": ""
          },
          {
            "from": "dsp",
            "to": "channel",
            "type": "data",
            "source": "parallel-am2045",
            "locator": "slides19,21",
            "label": ""
          },
          {
            "from": "channel",
            "to": "dsp",
            "type": "data",
            "source": "parallel-am2045",
            "locator": "slides19,21",
            "label": ""
          },
          {
            "from": "ru",
            "to": "channel",
            "type": "data",
            "source": "parallel-am2045",
            "locator": "slide21",
            "label": ""
          },
          {
            "from": "channel",
            "to": "ru",
            "type": "data",
            "source": "parallel-am2045",
            "locator": "slide21",
            "label": ""
          },
          {
            "from": "channel",
            "to": "hops",
            "type": "data",
            "source": "parallel-am2045",
            "locator": "slide21",
            "label": ""
          },
          {
            "from": "hops",
            "to": "array",
            "type": "data",
            "source": "parallel-am2045",
            "locator": "slide21",
            "label": ""
          },
          {
            "from": "array",
            "to": "hops",
            "type": "data",
            "source": "parallel-am2045",
            "locator": "slide21",
            "label": ""
          },
          {
            "from": "hops",
            "to": "channel",
            "type": "data",
            "source": "parallel-am2045",
            "locator": "slide21",
            "label": ""
          },
          {
            "from": "array",
            "to": "ddr",
            "type": "association",
            "source": "parallel-am2045",
            "locator": "slide22",
            "label": ""
          },
          {
            "from": "array",
            "to": "io",
            "type": "association",
            "source": "parallel-am2045",
            "locator": "slide22",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Ambric AM2045"
    },
    {
      "id": "queue-114",
      "name": "DIMA lineage — 2016 multifunctional SRAM inference IC",
      "organization": "University of Illinois at Urbana-Champaign",
      "year": 2016,
      "yearLabel": "24October2016 prototype report",
      "kind": "Measured mixed-signal inference prototype",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "hybrid",
        "digital",
        "analog"
      ],
      "architectures": [
        "in-memory",
        "reconfigurable"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural",
        "continuous"
      ],
      "aliases": [],
      "sources": [
        "parallel-dima-2016"
      ],
      "summary": "Multi-row SRAM reads and bitline charge processing compute dot products or Manhattan distances before conversion.",
      "config": "One measured512×256-bit6T SRAM array in65nm CMOS.",
      "gaps": [
        "A representative measured IC resolves the broad prototype-family candidate.",
        "Multi-bank energy improvements are estimates, not fabricated-system measurements."
      ],
      "insight": "Which arithmetic happens before data becomes a digital word?",
      "fields": {
        "state": {
          "value": "8-bit stored/streamed operands; analog intermediate voltages",
          "source": "parallel-dima-2016",
          "locator": "pp.2–4"
        },
        "compute": {
          "value": "MR-FR,BLP,CBLP and ADC/slicing stages",
          "source": "parallel-dima-2016",
          "locator": "p.2,Fig.1"
        },
        "memory": {
          "value": "16KB standard6T SRAM plus replica input cells",
          "source": "parallel-dima-2016",
          "locator": "Figs.2–3"
        },
        "control": {
          "value": "Digital controller and reconfiguration word",
          "source": "parallel-dima-2016",
          "locator": "p.3,Fig.2"
        },
        "io": {
          "value": "Streamed input buffer and decision scan-out",
          "source": "parallel-dima-2016",
          "locator": "Fig.2"
        },
        "software": {
          "value": "Reconfigured dot-product/Manhattan-distance modes",
          "source": "parallel-dima-2016",
          "locator": "pp.2–4"
        },
        "workload": {
          "value": "SVM,KNN,template matching,matched filtering",
          "source": "parallel-dima-2016",
          "locator": "Figs.1,6"
        }
      },
      "diagram": {
        "title": "Arithmetic embedded in SRAM reads and bitlines",
        "scope": "Measured single-bank IC; normal read/write circuitry remains separate.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "ctrl",
            "label": "Digital CTRL /RCFG",
            "subtitle": "MODE /SEQUENCING",
            "text": "Configures local processing-stage controllers.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-dima-2016",
            "locator": "Fig.2",
            "control": true
          },
          {
            "id": "input",
            "label": "Streamed input buffer",
            "subtitle": "16×128 BITS",
            "text": "Buffers external inference operands.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-dima-2016",
            "locator": "Fig.2",
            "control": false
          },
          {
            "id": "wl",
            "label": "Functional wordline driver",
            "subtitle": "PWM /SUBRANGED READ",
            "text": "Activates multiple rows per precharge.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-dima-2016",
            "locator": "Fig.3",
            "control": false
          },
          {
            "id": "array",
            "label": "6T SRAM bitcell array",
            "subtitle": "512×256 BITS",
            "text": "Stores inference data in standard cells.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-dima-2016",
            "locator": "Fig.2",
            "control": false
          },
          {
            "id": "replica",
            "label": "Replica bitcell array",
            "subtitle": "4×256 BITS",
            "text": "Stores streamed data for add/subtract.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-dima-2016",
            "locator": "pp.3–4,Fig.3",
            "control": false
          },
          {
            "id": "blp",
            "label": "Bitline processors",
            "subtitle": "MULT /COMPARE /ABS",
            "text": "Operate on analog bitline voltages.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-dima-2016",
            "locator": "Fig.4",
            "control": false
          },
          {
            "id": "cblp",
            "label": "Cross-bitline aggregation",
            "subtitle": "CHARGE SHARING",
            "text": "Combines column results into a scalar.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-dima-2016",
            "locator": "p.4,Fig.4",
            "control": false
          },
          {
            "id": "adc",
            "label": "Samplers +four ADCs",
            "subtitle": "8-BIT SINGLE-SLOPE",
            "text": "Converts accumulated analog outputs.",
            "x": 940,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-dima-2016",
            "locator": "p.3,Fig.2",
            "control": false
          },
          {
            "id": "slice",
            "label": "Slicing /decision output",
            "subtitle": "SCAN-OUT",
            "text": "Forms the final inference decision.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-dima-2016",
            "locator": "Figs.1–2",
            "control": false
          },
          {
            "id": "rw",
            "label": "Normal read/write circuitry",
            "subtitle": "SEPARATE PATH",
            "text": "Retains conventional memory operation.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-dima-2016",
            "locator": "p.3,Fig.2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "ctrl",
            "to": "input",
            "type": "control",
            "source": "parallel-dima-2016",
            "locator": "Fig.2",
            "label": "fetch"
          },
          {
            "from": "ctrl",
            "to": "wl",
            "type": "control",
            "source": "parallel-dima-2016",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "ctrl",
            "to": "blp",
            "type": "control",
            "source": "parallel-dima-2016",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "ctrl",
            "to": "adc",
            "type": "control",
            "source": "parallel-dima-2016",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "input",
            "to": "replica",
            "type": "data",
            "source": "parallel-dima-2016",
            "locator": "p.3,Fig.3",
            "label": ""
          },
          {
            "from": "wl",
            "to": "array",
            "type": "control",
            "source": "parallel-dima-2016",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "array",
            "to": "blp",
            "type": "data",
            "source": "parallel-dima-2016",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "replica",
            "to": "blp",
            "type": "data",
            "source": "parallel-dima-2016",
            "locator": "Fig.3",
            "label": ""
          },
          {
            "from": "blp",
            "to": "cblp",
            "type": "data",
            "source": "parallel-dima-2016",
            "locator": "Fig.4",
            "label": ""
          },
          {
            "from": "cblp",
            "to": "adc",
            "type": "data",
            "source": "parallel-dima-2016",
            "locator": "p.3,Fig.2",
            "label": ""
          },
          {
            "from": "adc",
            "to": "slice",
            "type": "data",
            "source": "parallel-dima-2016",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "rw",
            "to": "array",
            "type": "data",
            "source": "parallel-dima-2016",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "array",
            "to": "rw",
            "type": "data",
            "source": "parallel-dima-2016",
            "locator": "Fig.2",
            "label": ""
          },
          {
            "from": "ctrl",
            "to": "rw",
            "type": "control",
            "source": "parallel-dima-2016",
            "locator": "Fig.2",
            "label": ""
          }
        ]
      },
      "originalCandidate": "DIMA / compute-in-memory prototypes"
    },
    {
      "id": "queue-115",
      "name": "UPMEM P21 — 2556-DPU experimental server",
      "organization": "UPMEM hardware / Gómez-Luna et al. evaluation",
      "year": 2022,
      "yearLabel": "4May2022 paper revision",
      "kind": "Measured commercial PIM configuration",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "near-memory",
        "distributed",
        "heterogeneous",
        "pipelined"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register",
        "process"
      ],
      "aliases": [],
      "sources": [
        "parallel-upmem-p21"
      ],
      "summary": "DRAM-resident processors stage data through private scratchpads; hosts mediate all inter-DPU communication.",
      "config": "P21:20 DIMMs,2556 usable DPUs, dual Xeon Silver4215.",
      "gaps": [
        "Four of2560 nominal DPUs were unusable.",
        "Host and DPU cannot concurrently access one MRAM bank."
      ],
      "insight": "Why does putting processors in DRAM still require explicit DMA?",
      "fields": {
        "state": {
          "value": "32-bit RISC;24 hardware threads/DPU",
          "source": "parallel-upmem-p21",
          "locator": "§2.2"
        },
        "compute": {
          "value": "2556 usable350MHz DPUs",
          "source": "parallel-upmem-p21",
          "locator": "Table1"
        },
        "memory": {
          "value": "64MB MRAM,64KB WRAM,24KB IRAM/DPU",
          "source": "parallel-upmem-p21",
          "locator": "§2.1"
        },
        "control": {
          "value": "Host kernel launch; tasklets synchronize locally",
          "source": "parallel-upmem-p21",
          "locator": "§2.3"
        },
        "io": {
          "value": "DDR4 host data/control interface",
          "source": "parallel-upmem-p21",
          "locator": "Fig.1"
        },
        "software": {
          "value": "C/LLVM and UPMEM SDK2021.1.1",
          "source": "parallel-upmem-p21",
          "locator": "§2.3.1"
        },
        "workload": {
          "value": "PrIM memory-intensive benchmarks",
          "source": "parallel-upmem-p21",
          "locator": "§4"
        }
      },
      "diagram": {
        "title": "Host orchestration and DPU-local scratchpad execution",
        "scope": "One DPU expanded; remaining DPUs have no direct communication path.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "host",
            "label": "Dual Xeon host",
            "subtitle": "ALLOCATE /LAUNCH /MERGE",
            "text": "Mediates every inter-DPU transfer.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-upmem-p21",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "main",
            "label": "Host main memory",
            "subtitle": "256GB CONVENTIONAL DRAM",
            "text": "Stages inputs and merged results.",
            "x": 20,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-upmem-p21",
            "locator": "Table1",
            "control": false
          },
          {
            "id": "ddr",
            "label": "DDR4 interface",
            "subtitle": "CONTROL /STATUS /DATA",
            "text": "Connects PIM DIMMs to host.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-upmem-p21",
            "locator": "Fig.1",
            "control": false
          },
          {
            "id": "mram",
            "label": "DPU MRAM bank",
            "subtitle": "64MB PRIVATE DRAM",
            "text": "Holds data before/after local computation.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-upmem-p21",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "dma",
            "label": "DPU DMA engine",
            "subtitle": "EXPLICIT TRANSFERS",
            "text": "Moves MRAM data into scratchpad.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-upmem-p21",
            "locator": "§2.2",
            "control": false
          },
          {
            "id": "wram",
            "label": "WRAM scratchpad",
            "subtitle": "64KB SHARED BY TASKLETS",
            "text": "Supplies ordinary DPU loads/stores.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-upmem-p21",
            "locator": "§2.2",
            "control": false
          },
          {
            "id": "iram",
            "label": "IRAM",
            "subtitle": "24KB /4096 INSTRUCTIONS",
            "text": "Feeds the multithreaded pipeline.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-upmem-p21",
            "locator": "§2.2",
            "control": false
          },
          {
            "id": "pipe",
            "label": "DPU pipeline /registers",
            "subtitle": "24 HARDWARE THREADS",
            "text": "Interleaves in-order tasklet instructions.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-upmem-p21",
            "locator": "§2.2",
            "control": false
          },
          {
            "id": "other",
            "label": "Remaining usable DPUs",
            "subtitle": "2556 TOTAL",
            "text": "Exchange intermediate data through host.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-upmem-p21",
            "locator": "§§2.1,2.3",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "main",
            "to": "host",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "Fig.1",
            "label": ""
          },
          {
            "from": "host",
            "to": "main",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "Fig.1",
            "label": ""
          },
          {
            "from": "host",
            "to": "ddr",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "ddr",
            "to": "host",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "§2.1",
            "label": ""
          },
          {
            "from": "ddr",
            "to": "mram",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "Fig.1",
            "label": ""
          },
          {
            "from": "mram",
            "to": "ddr",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "Fig.1",
            "label": ""
          },
          {
            "from": "mram",
            "to": "dma",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "dma",
            "to": "mram",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "dma",
            "to": "wram",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "wram",
            "to": "dma",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "dma",
            "to": "iram",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "§2.2",
            "label": "instruction transfer"
          },
          {
            "from": "iram",
            "to": "pipe",
            "type": "control",
            "source": "parallel-upmem-p21",
            "locator": "Fig.1",
            "label": ""
          },
          {
            "from": "wram",
            "to": "pipe",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "pipe",
            "to": "wram",
            "type": "data",
            "source": "parallel-upmem-p21",
            "locator": "§2.2",
            "label": ""
          },
          {
            "from": "ddr",
            "to": "pipe",
            "type": "control",
            "source": "parallel-upmem-p21",
            "locator": "Fig.1",
            "label": "control/status"
          },
          {
            "from": "host",
            "to": "other",
            "type": "association",
            "source": "parallel-upmem-p21",
            "locator": "§2.3",
            "label": "host-mediated exchange"
          }
        ]
      },
      "originalCandidate": "UPMEM processing-in-memory systems"
    },
    {
      "id": "queue-116",
      "name": "Mythic M1076 — 76-tile AMP",
      "organization": "Mythic / Codasip processor IP",
      "year": 2021,
      "yearLabel": "Product brief v202106-1;2022 integration detail",
      "kind": "Commercial mixed-signal inference accelerator",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "hybrid",
        "digital",
        "analog",
        "dataflow"
      ],
      "architectures": [
        "in-memory",
        "crossbar",
        "heterogeneous",
        "distributed"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural",
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "parallel-m1076",
        "parallel-m1076-codasip"
      ],
      "summary": "Flash arrays retain neural weights and perform analog matrix operations beside digital control and vector processing.",
      "config": "M1076 chip or one-chip M.2 card; M1108/M1 excluded.",
      "gaps": [
        "ADC precision and internal bus widths are not disclosed here.",
        "Supplier case-study replication wording differs; manufacturer76-tile count is retained."
      ],
      "insight": "Which operations need digital processing after an analog matrix multiply?",
      "fields": {
        "state": {
          "value": "Analog weight-array state;32-bit RISC-V and16-bit SIMD",
          "source": "parallel-m1076",
          "locator": "p.1"
        },
        "compute": {
          "value": "76 analog/digital tiles",
          "source": "parallel-m1076",
          "locator": "p.1"
        },
        "memory": {
          "value": "On-chip flash weights and dedicated tile SRAM",
          "source": "parallel-m1076",
          "locator": "p.1"
        },
        "control": {
          "value": "Custom RV32IC core plus dependency scoreboard",
          "source": "parallel-m1076-codasip",
          "locator": "pp.3–4"
        },
        "io": {
          "value": "Four-lane PCIe2.1 host interface",
          "source": "parallel-m1076",
          "locator": "pp.1–2"
        },
        "software": {
          "value": "Compiled pretrained models and host runtime libraries",
          "source": "parallel-m1076",
          "locator": "p.2"
        },
        "workload": {
          "value": "Edge visual-perception inference",
          "source": "parallel-m1076",
          "locator": "p.2"
        }
      },
      "diagram": {
        "title": "Flash matrix computation with digital tile orchestration",
        "scope": "One AMP tile expanded; companion tiles and PCIe host aggregated.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "host",
            "label": "Host /PCIe interface",
            "subtitle": "APPLICATION /DRIVERS",
            "text": "Loads models and exchanges inference data.",
            "x": 20,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-m1076",
            "locator": "p.2",
            "control": false
          },
          {
            "id": "sram",
            "label": "Tile SRAM",
            "subtitle": "LOCAL DIGITAL STATE",
            "text": "Holds data passed between network nodes.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-m1076-codasip",
            "locator": "p.2",
            "control": false
          },
          {
            "id": "cpu",
            "label": "RISC-V nano-processor",
            "subtitle": "CUSTOMRV32IC",
            "text": "Sequences resource-dependent workload commands.",
            "x": 250,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-m1076-codasip",
            "locator": "pp.3–4",
            "control": false
          },
          {
            "id": "score",
            "label": "Hardware scoreboard",
            "subtitle": "DEPENDENCY TRACKING",
            "text": "Assists command trigger-condition management.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-m1076-codasip",
            "locator": "p.3",
            "control": true
          },
          {
            "id": "dac",
            "label": "ACE input conversion",
            "subtitle": "DIGITAL TO ANALOG",
            "text": "Presents inputs to the analog array.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-m1076-codasip",
            "locator": "p.2 tile diagram",
            "control": false
          },
          {
            "id": "flash",
            "label": "Flash matrix array",
            "subtitle": "WEIGHTS +COMPUTATION",
            "text": "Computes matrix products where weights reside.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-m1076-codasip",
            "locator": "p.2",
            "control": false
          },
          {
            "id": "adc",
            "label": "ACE output conversion",
            "subtitle": "ANALOG TO DIGITAL",
            "text": "Returns analog array outputs to digital form.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-m1076-codasip",
            "locator": "p.2 tile diagram",
            "control": false
          },
          {
            "id": "simd",
            "label": "16-bit SIMD engine",
            "subtitle": "NON-MATRIX OPERATIONS",
            "text": "Complements analog computation with digital processing.",
            "x": 710,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-m1076",
            "locator": "p.1",
            "control": false
          },
          {
            "id": "router",
            "label": "NoC router",
            "subtitle": "INTER-TILE DATAFLOW",
            "text": "Connects the tile to the array.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-m1076",
            "locator": "p.1",
            "control": false
          },
          {
            "id": "other",
            "label": "Other AMP tiles",
            "subtitle": "76 TOTAL",
            "text": "Hold other model weights and operations.",
            "x": 940,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-m1076",
            "locator": "p.1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "router",
            "type": "association",
            "source": "parallel-m1076",
            "locator": "p.2 host diagram",
            "label": "chip-level PCIe"
          },
          {
            "from": "sram",
            "to": "dac",
            "type": "data",
            "source": "parallel-m1076-codasip",
            "locator": "p.2 tile diagram",
            "label": ""
          },
          {
            "from": "dac",
            "to": "flash",
            "type": "data",
            "source": "parallel-m1076-codasip",
            "locator": "p.2 tile diagram",
            "label": ""
          },
          {
            "from": "flash",
            "to": "adc",
            "type": "data",
            "source": "parallel-m1076-codasip",
            "locator": "p.2 tile diagram",
            "label": ""
          },
          {
            "from": "adc",
            "to": "sram",
            "type": "data",
            "source": "parallel-m1076-codasip",
            "locator": "p.2 tile diagram",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "score",
            "type": "association",
            "source": "parallel-m1076-codasip",
            "locator": "p.3",
            "label": ""
          },
          {
            "from": "cpu",
            "to": "flash",
            "type": "control",
            "source": "parallel-m1076-codasip",
            "locator": "p.3",
            "label": "workload commands"
          },
          {
            "from": "cpu",
            "to": "simd",
            "type": "control",
            "source": "parallel-m1076-codasip",
            "locator": "pp.2–3",
            "label": ""
          },
          {
            "from": "sram",
            "to": "simd",
            "type": "association",
            "source": "parallel-m1076-codasip",
            "locator": "p.2",
            "label": "tile data processing"
          },
          {
            "from": "sram",
            "to": "router",
            "type": "association",
            "source": "parallel-m1076-codasip",
            "locator": "p.2",
            "label": "inter-node data"
          },
          {
            "from": "router",
            "to": "other",
            "type": "data",
            "source": "parallel-m1076",
            "locator": "p.1",
            "label": ""
          },
          {
            "from": "other",
            "to": "router",
            "type": "data",
            "source": "parallel-m1076",
            "locator": "p.1",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Mythic M1076"
    },
    {
      "id": "queue-117",
      "name": "Samsung Aquabolt-XL — U280 HBM-PIM demonstrator",
      "organization": "Samsung Electronics / Xilinx collaboration",
      "year": 2021,
      "yearLabel": "2021 fabricated HBM-PIM lineage; later public tutorial",
      "kind": "Built accelerator/memory demonstrator",
      "status": "dossier",
      "track": "special",
      "trackName": "Spatial, dataflow & specialized engines",
      "discoveryParadigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "near-memory",
        "simd",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "parallel-hbm-pim",
        "parallel-hbm-pim-model"
      ],
      "summary": "Host DRAM commands trigger bank-adjacent SIMD operations while preserving standard HBM access mode.",
      "config": "U280-PIM board with two Aquabolt-XL stacks and12GB memory.",
      "gaps": [
        "Tutorial date unspecified;2021 identifies the underlying silicon work.",
        "Simulator details are evidence for the public programming model, not additional measured silicon claims."
      ],
      "insight": "What changes when a memory read/write command triggers arithmetic?",
      "fields": {
        "state": {
          "value": "16-bit floating-point bank datapaths",
          "source": "parallel-hbm-pim",
          "locator": "PDFslide6"
        },
        "compute": {
          "value": "Lockstep PIM units at bank-pair boundaries",
          "source": "parallel-hbm-pim",
          "locator": "PDFslides6–7"
        },
        "memory": {
          "value": "Two HBM-PIM stacks,12GB total",
          "source": "parallel-hbm-pim",
          "locator": "PDFslide13"
        },
        "control": {
          "value": "Host commands trigger PIM instructions",
          "source": "parallel-hbm-pim",
          "locator": "PDFslide6"
        },
        "io": {
          "value": "Unmodified HBM controller and standard mode",
          "source": "parallel-hbm-pim",
          "locator": "PDFslides6–7"
        },
        "software": {
          "value": "Host generates mode/control/memory transactions",
          "source": "parallel-hbm-pim-model",
          "locator": "README§4.2"
        },
        "workload": {
          "value": "Memory-bound matrix-vector/RNN inference",
          "source": "parallel-hbm-pim",
          "locator": "PDFslides15,17–18"
        }
      },
      "diagram": {
        "title": "Host-triggered computation at the DRAM bank boundary",
        "scope": "One PIM bank pair expanded in a two-stack FPGA demonstrator.",
        "width": 1145,
        "height": 530,
        "nodes": [
          {
            "id": "host",
            "label": "U280 FPGA host",
            "subtitle": "HBM CONTROLLER",
            "text": "Issues commands that trigger PIM work.",
            "x": 20,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-hbm-pim",
            "locator": "PDFslides6–7,13",
            "control": false
          },
          {
            "id": "buffer",
            "label": "Buffer die /TSVs",
            "subtitle": "STANDARD HBM INTERFACE",
            "text": "Connects host channels to stacked dies.",
            "x": 250,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-hbm-pim",
            "locator": "PDFslides7–8",
            "control": false
          },
          {
            "id": "cmd",
            "label": "PIM command sequencing",
            "subtitle": "HOST-TRIGGERED",
            "text": "Advances programmed operations on DRAM commands.",
            "x": 480,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-hbm-pim-model",
            "locator": "README§2.3",
            "control": true
          },
          {
            "id": "even",
            "label": "Even bank array",
            "subtitle": "DRAM STORAGE",
            "text": "Supplies one side of a PIM pair.",
            "x": 480,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-hbm-pim",
            "locator": "PDFslides6–7",
            "control": false
          },
          {
            "id": "odd",
            "label": "Odd bank array",
            "subtitle": "DRAM STORAGE",
            "text": "Shares the paired PIM execution boundary.",
            "x": 480,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-hbm-pim",
            "locator": "PDFslides6–7",
            "control": false
          },
          {
            "id": "sense",
            "label": "Sense /write circuitry",
            "subtitle": "BANK I/O BOUNDARY",
            "text": "Exposes bank data and writes results.",
            "x": 710,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-hbm-pim",
            "locator": "PDFslide6",
            "control": false
          },
          {
            "id": "regs",
            "label": "PIM operand registers",
            "subtitle": "LOCAL VALUES",
            "text": "Provide retained operands to SIMD FPUs.",
            "x": 710,
            "y": 30,
            "w": 184,
            "h": 68,
            "source": "parallel-hbm-pim",
            "locator": "PDFslide6",
            "control": false
          },
          {
            "id": "fpu",
            "label": "SIMD FPUs",
            "subtitle": "16-BIT FLOATING POINT",
            "text": "Computes on bank data and registers.",
            "x": 940,
            "y": 200,
            "w": 184,
            "h": 68,
            "source": "parallel-hbm-pim",
            "locator": "PDFslide6",
            "control": false
          },
          {
            "id": "other",
            "label": "Other banks /stack",
            "subtitle": "TWO STACKS TOTAL",
            "text": "Adds bank-parallel execution and capacity.",
            "x": 250,
            "y": 370,
            "w": 184,
            "h": 68,
            "source": "parallel-hbm-pim",
            "locator": "PDFslides6,13",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "buffer",
            "type": "control",
            "source": "parallel-hbm-pim",
            "locator": "PDFslide6",
            "label": ""
          },
          {
            "from": "host",
            "to": "buffer",
            "type": "data",
            "source": "parallel-hbm-pim",
            "locator": "PDFslide7",
            "label": ""
          },
          {
            "from": "buffer",
            "to": "cmd",
            "type": "control",
            "source": "parallel-hbm-pim-model",
            "locator": "README§2.3",
            "label": ""
          },
          {
            "from": "cmd",
            "to": "fpu",
            "type": "control",
            "source": "parallel-hbm-pim-model",
            "locator": "README§2.3",
            "label": ""
          },
          {
            "from": "even",
            "to": "sense",
            "type": "data",
            "source": "parallel-hbm-pim",
            "locator": "PDFslide6",
            "label": ""
          },
          {
            "from": "odd",
            "to": "sense",
            "type": "data",
            "source": "parallel-hbm-pim",
            "locator": "PDFslide6",
            "label": ""
          },
          {
            "from": "sense",
            "to": "fpu",
            "type": "data",
            "source": "parallel-hbm-pim",
            "locator": "PDFslide6",
            "label": ""
          },
          {
            "from": "regs",
            "to": "fpu",
            "type": "data",
            "source": "parallel-hbm-pim",
            "locator": "PDFslide6",
            "label": ""
          },
          {
            "from": "fpu",
            "to": "regs",
            "type": "data",
            "source": "parallel-hbm-pim",
            "locator": "PDFslide6",
            "label": ""
          },
          {
            "from": "fpu",
            "to": "sense",
            "type": "data",
            "source": "parallel-hbm-pim",
            "locator": "PDFslide6",
            "label": ""
          },
          {
            "from": "sense",
            "to": "even",
            "type": "data",
            "source": "parallel-hbm-pim",
            "locator": "PDFslide6",
            "label": ""
          },
          {
            "from": "sense",
            "to": "odd",
            "type": "data",
            "source": "parallel-hbm-pim",
            "locator": "PDFslide6",
            "label": ""
          },
          {
            "from": "buffer",
            "to": "other",
            "type": "data",
            "source": "parallel-hbm-pim",
            "locator": "PDFslides6–7",
            "label": ""
          },
          {
            "from": "buffer",
            "to": "even",
            "type": "association",
            "source": "parallel-hbm-pim",
            "locator": "PDFslide7",
            "label": ""
          },
          {
            "from": "buffer",
            "to": "odd",
            "type": "association",
            "source": "parallel-hbm-pim",
            "locator": "PDFslide7",
            "label": ""
          }
        ]
      },
      "originalCandidate": "Samsung HBM-PIM"
    },
    {
      "id": "queue-118",
      "name": "Rockefeller Differential Analyzer: Kopal configuration",
      "organization": "MIT Center of Analysis",
      "year": 1949,
      "yearLabel": "1949 published application configuration",
      "kind": "Electromechanical analog computer",
      "status": "dossier",
      "track": "analog",
      "trackName": "Analog, hybrid & physical dynamics",
      "discoveryParadigms": [
        "analog",
        "unconventional"
      ],
      "paradigms": [
        "analog",
        "parallel"
      ],
      "architectures": [
        "analog-integrator",
        "mechanical"
      ],
      "substrates": [
        "mechanical",
        "relay",
        "vacuum-tube"
      ],
      "models": [
        "continuous"
      ],
      "aliases": [],
      "sources": [
        "alt-rockefeller-kopal"
      ],
      "summary": "A nine-integrator configuration searches stellar-oscillation eigenvalues with tabulated functions and adjustable gear ratios.",
      "config": "Kopal’s published setup on the Rockefeller analyzer, using nine of its 18 integrators; the date identifies this application, not machine completion.",
      "gaps": [
        "Final higher-precision tabulations in the paper were refined by hand after analyzer trials.",
        "Complete machine relay, servo and paper-tape paths remain undocumented here."
      ],
      "insight": "How are multiplication and division rewritten into operations an integrator network can perform?",
      "fields": {
        "state": {
          "value": "Continuous mechanical variables x, w and z",
          "locator": "§II; Fig. 1",
          "source": "alt-rockefeller-kopal"
        },
        "compute": {
          "value": "Nine configured integrators",
          "locator": "p. 515",
          "source": "alt-rockefeller-kopal"
        },
        "memory": {
          "value": "Integrator state and input tables",
          "locator": "§II",
          "source": "alt-rockefeller-kopal"
        },
        "control": {
          "value": "Gear ratios and operator-set initial conditions",
          "locator": "pp. 515–517",
          "source": "alt-rockefeller-kopal"
        },
        "io": {
          "value": "Three tabulated-function inputs; solution curves",
          "locator": "p. 515; Fig. 1",
          "source": "alt-rockefeller-kopal"
        },
        "software": {
          "value": "Equation transformation and machine setup",
          "locator": "Eqs. 17.2, 18.3",
          "source": "alt-rockefeller-kopal"
        },
        "workload": {
          "value": "Trial eigenvalues for stellar oscillations",
          "locator": "pp. 514, 517",
          "source": "alt-rockefeller-kopal"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "The published stellar-oscillation computation",
        "scope": "Fig. 1 functional groups; aggregated integrators and mathematical/mechanical dependencies.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "x",
            "label": "Independent variable x",
            "subtitle": "MACHINE DRIVE",
            "text": "Advances the integration.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-rockefeller-kopal",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "tables",
            "label": "Three input tables",
            "subtitle": "KNOWN FUNCTIONS",
            "text": "Supplies f1, f2 and g2.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-rockefeller-kopal",
            "locator": "p. 515",
            "control": false
          },
          {
            "id": "reciprocal",
            "label": "Reciprocal generation",
            "subtitle": "INVERSE INTEGRATION",
            "text": "Obtains g1 from f1.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-rockefeller-kopal",
            "locator": "p. 515",
            "control": false
          },
          {
            "id": "gear",
            "label": "Adjustable gear ratios",
            "subtitle": "TRIAL PARAMETERS",
            "text": "Sets eigenvalue-dependent factors.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-rockefeller-kopal",
            "locator": "p. 515",
            "control": true
          },
          {
            "id": "coeff",
            "label": "f and g combinations",
            "subtitle": "COEFFICIENT FUNCTIONS",
            "text": "Combines table and parameter values.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-rockefeller-kopal",
            "locator": "Eqs. 17.1–18.1",
            "control": false
          },
          {
            "id": "w",
            "label": "w integral branch",
            "subtitle": "INTEGRATOR NETWORK",
            "text": "Computes integral of fz.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-rockefeller-kopal",
            "locator": "Eq. 17.2",
            "control": false
          },
          {
            "id": "h",
            "label": "Integral of gw",
            "subtitle": "INTEGRATOR NETWORK",
            "text": "Supplies the second branch.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-rockefeller-kopal",
            "locator": "Eq. 18.3",
            "control": false
          },
          {
            "id": "xinv",
            "label": "x inverse-square branch",
            "subtitle": "TWO INTEGRATORS",
            "text": "Generates x⁻² from x.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-rockefeller-kopal",
            "locator": "p. 515",
            "control": false
          },
          {
            "id": "z",
            "label": "z combination",
            "subtitle": "PARTIAL INTEGRATION",
            "text": "Combines transformed integrals.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-rockefeller-kopal",
            "locator": "Eq. 18.3",
            "control": false
          },
          {
            "id": "trial",
            "label": "Boundary / trial assessment",
            "subtitle": "OPERATOR READOUT",
            "text": "Brackets eigenvalues.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-rockefeller-kopal",
            "locator": "p. 517",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "x",
            "to": "tables",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "tables",
            "to": "reciprocal",
            "type": "data",
            "locator": "p. 515",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "reciprocal",
            "to": "coeff",
            "type": "data",
            "locator": "p. 515",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "tables",
            "to": "coeff",
            "type": "data",
            "locator": "Eqs. 17.1–18.1",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "gear",
            "to": "coeff",
            "type": "control",
            "locator": "p. 515",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "coeff",
            "to": "w",
            "type": "data",
            "locator": "Eq. 17.2",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "z",
            "to": "w",
            "type": "data",
            "locator": "Eq. 17.2",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "w",
            "to": "h",
            "type": "data",
            "locator": "Eq. 18.3",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "coeff",
            "to": "h",
            "type": "data",
            "locator": "Eq. 18.3",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "x",
            "to": "xinv",
            "type": "data",
            "locator": "p. 515",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "xinv",
            "to": "z",
            "type": "data",
            "locator": "Eq. 18.3",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "h",
            "to": "z",
            "type": "data",
            "locator": "Eq. 18.3",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "w",
            "to": "trial",
            "type": "data",
            "locator": "p. 517",
            "label": "",
            "source": "alt-rockefeller-kopal"
          },
          {
            "from": "trial",
            "to": "gear",
            "type": "control",
            "locator": "p. 517",
            "label": "successive trials",
            "source": "alt-rockefeller-kopal"
          }
        ]
      },
      "originalCandidate": "Rockefeller Differential Analyzer"
    },
    {
      "id": "queue-119",
      "name": "EAI 231R-V (1964 manual configuration)",
      "organization": "Electronic Associates, Inc.",
      "year": 1964,
      "yearLabel": "August 1964 information manual",
      "kind": "Electronic analog computer",
      "status": "dossier",
      "track": "analog",
      "trackName": "Analog, hybrid & physical dynamics",
      "discoveryParadigms": [
        "analog",
        "unconventional"
      ],
      "paradigms": [
        "analog",
        "hybrid"
      ],
      "architectures": [
        "analog-integrator"
      ],
      "substrates": [
        "vacuum-tube",
        "transistor"
      ],
      "models": [
        "continuous",
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "alt-eai231rv"
      ],
      "summary": "A patched analog network combines continuous computation with separate mode logic and selectable voltage readout.",
      "config": "231R-V system described in the 1964 manual; complement varies with expansion and accessories.",
      "gaps": [
        "The information manual does not certify performance for an installed specimen.",
        "Optional fully expanded equipment is not silently assigned to every 231R-family installation."
      ],
      "insight": "How can logic sequence a continuous network without replacing its analog state?",
      "fields": {
        "state": {
          "value": "Computing voltages",
          "locator": "pp. 6–8",
          "source": "alt-eai231rv"
        },
        "compute": {
          "value": "Summers, integrators, multipliers and function generators",
          "locator": "pp. 21–24; contents",
          "source": "alt-eai231rv"
        },
        "memory": {
          "value": "Integrator capacitors and track/store units",
          "locator": "pp. 23–24",
          "source": "alt-eai231rv"
        },
        "control": {
          "value": "Separate mode-logic patching and timers",
          "locator": "pp. 13–17",
          "source": "alt-eai231rv"
        },
        "io": {
          "value": "AERO selection, voltmeters and optional recorders",
          "locator": "pp. 6–8",
          "source": "alt-eai231rv"
        },
        "software": {
          "value": "Removable pre-patched programs",
          "locator": "p. 6",
          "source": "alt-eai231rv"
        },
        "workload": {
          "value": "Continuous simulation / iterative solutions",
          "locator": "pp. 1–2, 24",
          "source": "alt-eai231rv"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Analog patching with a separate logic/control plane",
        "scope": "Published functional subsystems; optional digital attachment is identified as an interface rather than a mandatory stored-program CPU.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "patch",
            "label": "Analog pre-patch panel",
            "subtitle": "PROGRAM CONNECTIONS",
            "text": "Connects computing elements.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-eai231rv",
            "locator": "p. 6",
            "control": false
          },
          {
            "id": "pot",
            "label": "Coefficient attenuators",
            "subtitle": "PARAMETERS",
            "text": "Sets analog scaling.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-eai231rv",
            "locator": "p. 25",
            "control": false
          },
          {
            "id": "compute",
            "label": "Summers / nonlinear units",
            "subtitle": "CONTINUOUS OPERATORS",
            "text": "Combines input voltages.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-eai231rv",
            "locator": "pp. 21–24",
            "control": false
          },
          {
            "id": "integ",
            "label": "Summer-integrators",
            "subtitle": "CAPACITOR STATE",
            "text": "Integrates and retains values.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-eai231rv",
            "locator": "p. 23",
            "control": false
          },
          {
            "id": "store",
            "label": "Track / store units",
            "subtitle": "POINT STORAGE",
            "text": "Retains selected analog values.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-eai231rv",
            "locator": "p. 24",
            "control": false
          },
          {
            "id": "logic",
            "label": "Mode-logic panel",
            "subtitle": "CONTROL PROGRAM",
            "text": "Sequences IC, operate and hold.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-eai231rv",
            "locator": "Fig. 20",
            "control": true
          },
          {
            "id": "clock",
            "label": "Oscillator / timers",
            "subtitle": "INTERVAL CONTROL",
            "text": "Times repetitive operation.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-eai231rv",
            "locator": "p. 17",
            "control": true
          },
          {
            "id": "aero",
            "label": "AERO selector",
            "subtitle": "SIGNAL MONITOR",
            "text": "Selects outputs and settings.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-eai231rv",
            "locator": "pp. 6–7",
            "control": false
          },
          {
            "id": "meter",
            "label": "Voltmeter / printer",
            "subtitle": "READOUT",
            "text": "Measures selected voltages.",
            "x": 30,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-eai231rv",
            "locator": "pp. 7–8",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "patch",
            "to": "compute",
            "type": "association",
            "locator": "p. 6",
            "label": "",
            "source": "alt-eai231rv"
          },
          {
            "from": "pot",
            "to": "compute",
            "type": "data",
            "locator": "p. 25",
            "label": "",
            "source": "alt-eai231rv"
          },
          {
            "from": "compute",
            "to": "integ",
            "type": "data",
            "locator": "p. 23",
            "label": "",
            "source": "alt-eai231rv"
          },
          {
            "from": "integ",
            "to": "patch",
            "type": "data",
            "locator": "p. 6",
            "label": "",
            "source": "alt-eai231rv"
          },
          {
            "from": "integ",
            "to": "store",
            "type": "data",
            "locator": "p. 24",
            "label": "",
            "source": "alt-eai231rv"
          },
          {
            "from": "store",
            "to": "compute",
            "type": "data",
            "locator": "p. 24",
            "label": "",
            "source": "alt-eai231rv"
          },
          {
            "from": "clock",
            "to": "logic",
            "type": "control",
            "locator": "Fig. 20",
            "label": "",
            "source": "alt-eai231rv"
          },
          {
            "from": "logic",
            "to": "integ",
            "type": "control",
            "locator": "Fig. 20",
            "label": "",
            "source": "alt-eai231rv"
          },
          {
            "from": "logic",
            "to": "store",
            "type": "control",
            "locator": "p. 24",
            "label": "",
            "source": "alt-eai231rv"
          },
          {
            "from": "integ",
            "to": "aero",
            "type": "data",
            "locator": "Table II",
            "label": "",
            "source": "alt-eai231rv"
          },
          {
            "from": "aero",
            "to": "meter",
            "type": "data",
            "locator": "pp. 7–8",
            "label": "",
            "source": "alt-eai231rv"
          }
        ]
      },
      "originalCandidate": "EAI 231R"
    },
    {
      "id": "queue-120",
      "name": "EAI 680 (1966 reference configuration)",
      "organization": "Electronic Associates, Inc.",
      "year": 1966,
      "yearLabel": "October 1966 reference handbook",
      "kind": "Analog/hybrid computing system",
      "status": "dossier",
      "track": "analog",
      "trackName": "Analog, hybrid & physical dynamics",
      "discoveryParadigms": [
        "analog",
        "unconventional"
      ],
      "paradigms": [
        "analog",
        "hybrid"
      ],
      "architectures": [
        "analog-integrator"
      ],
      "substrates": [
        "transistor"
      ],
      "models": [
        "continuous",
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "alt-eai680"
      ],
      "summary": "Patched operational networks use logic-controlled capacitors and gates to change integration modes and time scales.",
      "config": "Standard 680 reference architecture, up to 30 combination integrator/summers when fully expanded; not a particular attached digital host.",
      "gaps": [
        "Thirty combination channels is an expanded complement, not every delivered system.",
        "The diagram does not attach a PDP-9, PDP-10 or other digital computer without an installation-specific source."
      ],
      "insight": "Why do IC and operate inputs use distinct summing paths?",
      "fields": {
        "state": {
          "value": "Continuous normalized voltages",
          "locator": "Chapter 6",
          "source": "alt-eai680"
        },
        "compute": {
          "value": "Combination amplifiers and quarter-square multipliers",
          "locator": "Chapters 6, 11",
          "source": "alt-eai680"
        },
        "memory": {
          "value": "Selectable feedback capacitors / track-store",
          "locator": "§6.4; Chapter 7",
          "source": "alt-eai680"
        },
        "control": {
          "value": "IC / operate gates and mode/timer logic",
          "locator": "§6.4; Chapter 20",
          "source": "alt-eai680"
        },
        "io": {
          "value": "Signal selector and digital voltmeter",
          "locator": "Chapter 3",
          "source": "alt-eai680"
        },
        "software": {
          "value": "Patch-panel topology and parameter setting",
          "locator": "Chapters 2–5",
          "source": "alt-eai680"
        },
        "workload": {
          "value": "Analog and hybrid dynamic simulation",
          "locator": "Chapter 1",
          "source": "alt-eai680"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Inside a combination integrator, with its control boundary",
        "scope": "One representative combination-amplifier channel. Four feedback capacitances change time scale; physical component count is configuration-dependent.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "input",
            "label": "Patched input network",
            "subtitle": "WEIGHTED SIGNALS",
            "text": "Feeds the operate junction.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-eai680",
            "locator": "§6.5",
            "control": false
          },
          {
            "id": "op",
            "label": "Operate gate",
            "subtitle": "OP MODE",
            "text": "Connects dynamic inputs.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-eai680",
            "locator": "Fig. 6.2",
            "control": false
          },
          {
            "id": "amp",
            "label": "High-gain amplifier",
            "subtitle": "COMPUTATION",
            "text": "Maintains summing-junction balance.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-eai680",
            "locator": "Fig. 6.2",
            "control": false
          },
          {
            "id": "cap",
            "label": "Feedback capacitors",
            "subtitle": "INTEGRATOR STATE",
            "text": "Stores the integral voltage.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-eai680",
            "locator": "§6.4.2; Fig. 6.2",
            "control": false
          },
          {
            "id": "ic",
            "label": "IC resistor / gate",
            "subtitle": "INITIALIZATION",
            "text": "Charges starting conditions.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-eai680",
            "locator": "§6.5.1",
            "control": false
          },
          {
            "id": "mode",
            "label": "Mode / timer logic",
            "subtitle": "IC / HOLD / OP",
            "text": "Selects computational mode.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-eai680",
            "locator": "§6.4; Chapter 20",
            "control": true
          },
          {
            "id": "scale",
            "label": "F / MS controls",
            "subtitle": "TIME SCALE",
            "text": "Selects feedback capacitance.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-eai680",
            "locator": "§6.4.2",
            "control": true
          },
          {
            "id": "selector",
            "label": "Signal selector / DVM",
            "subtitle": "OUTPUT MONITOR",
            "text": "Reads selected values.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-eai680",
            "locator": "Chapter 3; §6.5.1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "input",
            "to": "op",
            "type": "data",
            "locator": "§6.5.1",
            "label": "",
            "source": "alt-eai680"
          },
          {
            "from": "op",
            "to": "amp",
            "type": "data",
            "locator": "Fig. 6.2",
            "label": "",
            "source": "alt-eai680"
          },
          {
            "from": "amp",
            "to": "cap",
            "type": "data",
            "locator": "Fig. 6.2",
            "label": "",
            "source": "alt-eai680"
          },
          {
            "from": "cap",
            "to": "amp",
            "type": "data",
            "locator": "Fig. 6.2",
            "label": "feedback",
            "source": "alt-eai680"
          },
          {
            "from": "ic",
            "to": "amp",
            "type": "data",
            "locator": "§6.5.1",
            "label": "",
            "source": "alt-eai680"
          },
          {
            "from": "mode",
            "to": "op",
            "type": "control",
            "locator": "§6.4.1",
            "label": "",
            "source": "alt-eai680"
          },
          {
            "from": "mode",
            "to": "ic",
            "type": "control",
            "locator": "§6.4.1",
            "label": "",
            "source": "alt-eai680"
          },
          {
            "from": "scale",
            "to": "cap",
            "type": "control",
            "locator": "§6.4.2",
            "label": "",
            "source": "alt-eai680"
          },
          {
            "from": "amp",
            "to": "selector",
            "type": "data",
            "locator": "Chapter 3",
            "label": "",
            "source": "alt-eai680"
          },
          {
            "from": "amp",
            "to": "input",
            "type": "data",
            "locator": "Chapter 2",
            "label": "patched network feedback",
            "source": "alt-eai680"
          }
        ]
      },
      "originalCandidate": "EAI 680"
    },
    {
      "id": "queue-121",
      "name": "Heathkit EC-1 spring–mass configuration",
      "organization": "Heath Company",
      "year": 1965,
      "yearLabel": "1965 operational manual",
      "kind": "Educational analog computer",
      "status": "dossier",
      "track": "analog",
      "trackName": "Analog, hybrid & physical dynamics",
      "discoveryParadigms": [
        "analog",
        "unconventional"
      ],
      "paradigms": [
        "analog"
      ],
      "architectures": [
        "analog-integrator"
      ],
      "substrates": [
        "vacuum-tube"
      ],
      "models": [
        "continuous"
      ],
      "aliases": [],
      "sources": [
        "alt-heath-ec1"
      ],
      "summary": "A small vacuum-tube analog computer solves a patched differential equation with reset and repetitive operation.",
      "config": "EC-1 manual’s damped spring–mass example, Fig. 30; nine DC amplifiers are available, with only the illustrated subset used here.",
      "gaps": [
        "Analog accuracy depends on amplifier drift, scaling, component tolerances and calibration.",
        "The dated manual is evidence for this configuration, not the product’s original introduction date."
      ],
      "insight": "How do feedback coefficients turn two integrators into an oscillator model?",
      "fields": {
        "state": {
          "value": "Voltages representing displacement and velocity",
          "locator": "pp. 24–25",
          "source": "alt-heath-ec1"
        },
        "compute": {
          "value": "Tube operational amplifiers",
          "locator": "p. 13; p. 32",
          "source": "alt-heath-ec1"
        },
        "memory": {
          "value": "Integrator feedback capacitors",
          "locator": "Fig. 30",
          "source": "alt-heath-ec1"
        },
        "control": {
          "value": "Operation/reset relay; optional repetition oscillator",
          "locator": "p. 15",
          "source": "alt-heath-ec1"
        },
        "io": {
          "value": "Meter, oscilloscope or pen recorder",
          "locator": "pp. 13, 16, 25",
          "source": "alt-heath-ec1"
        },
        "software": {
          "value": "Plug-connected resistor/capacitor network",
          "locator": "p. 32; Fig. 30",
          "source": "alt-heath-ec1"
        },
        "workload": {
          "value": "Damped driven spring–mass equation",
          "locator": "pp. 24–25",
          "source": "alt-heath-ec1"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "A damped spring–mass equation in analog feedback",
        "scope": "Functional rewriting of the manual example, not a transistor schematic. Resistor scaling and signs are represented by the coefficient blocks.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "force",
            "label": "Applied force F(t)",
            "subtitle": "INPUT VOLTAGE",
            "text": "Drives the model.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-heath-ec1",
            "locator": "p. 25",
            "control": false
          },
          {
            "id": "sum",
            "label": "Acceleration combination",
            "subtitle": "F − S·v − K·y",
            "text": "Forms the differential equation.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-heath-ec1",
            "locator": "Fig. 30",
            "control": false
          },
          {
            "id": "velocity",
            "label": "Velocity integrator",
            "subtitle": "CAPACITOR STATE",
            "text": "Integrates acceleration.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-heath-ec1",
            "locator": "Fig. 30",
            "control": false
          },
          {
            "id": "position",
            "label": "Position integrator",
            "subtitle": "CAPACITOR STATE",
            "text": "Integrates velocity.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-heath-ec1",
            "locator": "Fig. 30",
            "control": false
          },
          {
            "id": "spring",
            "label": "Spring coefficient K",
            "subtitle": "DISPLACEMENT FEEDBACK",
            "text": "Scales restoring force.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-heath-ec1",
            "locator": "Fig. 30",
            "control": false
          },
          {
            "id": "damper",
            "label": "Damping coefficient S",
            "subtitle": "VELOCITY FEEDBACK",
            "text": "Scales damping force.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-heath-ec1",
            "locator": "Fig. 30",
            "control": false
          },
          {
            "id": "reset",
            "label": "Reset / operation relay",
            "subtitle": "CONTROL",
            "text": "Initializes the integrators.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-heath-ec1",
            "locator": "p. 15; Fig. 30",
            "control": true
          },
          {
            "id": "repeat",
            "label": "Repetitive oscillator",
            "subtitle": "OPTIONAL CONTROL",
            "text": "Cycles reset and solve.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-heath-ec1",
            "locator": "p. 15",
            "control": true
          },
          {
            "id": "readout",
            "label": "Meter / external display",
            "subtitle": "OUTPUT",
            "text": "Observes the solution.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-heath-ec1",
            "locator": "pp. 16, 25",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "force",
            "to": "sum",
            "type": "data",
            "locator": "Fig. 30",
            "label": "",
            "source": "alt-heath-ec1"
          },
          {
            "from": "sum",
            "to": "velocity",
            "type": "data",
            "locator": "Fig. 30",
            "label": "",
            "source": "alt-heath-ec1"
          },
          {
            "from": "velocity",
            "to": "position",
            "type": "data",
            "locator": "Fig. 30",
            "label": "",
            "source": "alt-heath-ec1"
          },
          {
            "from": "velocity",
            "to": "damper",
            "type": "data",
            "locator": "Fig. 30",
            "label": "",
            "source": "alt-heath-ec1"
          },
          {
            "from": "position",
            "to": "spring",
            "type": "data",
            "locator": "Fig. 30",
            "label": "",
            "source": "alt-heath-ec1"
          },
          {
            "from": "damper",
            "to": "sum",
            "type": "data",
            "locator": "Fig. 30",
            "label": "",
            "source": "alt-heath-ec1"
          },
          {
            "from": "spring",
            "to": "sum",
            "type": "data",
            "locator": "Fig. 30",
            "label": "",
            "source": "alt-heath-ec1"
          },
          {
            "from": "reset",
            "to": "velocity",
            "type": "control",
            "locator": "Fig. 30",
            "label": "",
            "source": "alt-heath-ec1"
          },
          {
            "from": "reset",
            "to": "position",
            "type": "control",
            "locator": "Fig. 30",
            "label": "",
            "source": "alt-heath-ec1"
          },
          {
            "from": "repeat",
            "to": "reset",
            "type": "control",
            "locator": "p. 15",
            "label": "",
            "source": "alt-heath-ec1"
          },
          {
            "from": "position",
            "to": "readout",
            "type": "data",
            "locator": "Fig. 31",
            "label": "",
            "source": "alt-heath-ec1"
          }
        ]
      },
      "originalCandidate": "Heathkit EC-1"
    },
    {
      "id": "queue-122",
      "name": "EAI PACE TR-10 linear-equation configuration",
      "organization": "Electronic Associates, Inc.",
      "year": null,
      "yearLabel": "Undated manufacturer brochure configuration",
      "kind": "Transistor analog computer",
      "status": "dossier",
      "track": "analog",
      "trackName": "Analog, hybrid & physical dynamics",
      "discoveryParadigms": [
        "analog",
        "unconventional"
      ],
      "paradigms": [
        "analog"
      ],
      "architectures": [
        "analog-integrator"
      ],
      "substrates": [
        "transistor"
      ],
      "models": [
        "continuous"
      ],
      "aliases": [],
      "sources": [
        "alt-pace-tr10"
      ],
      "summary": "A desktop patched network solves a scaled second-order equation while a separate integrator supplies the display time base.",
      "config": "Basic TR-10 linear differential-equation example on brochure p. 6; nonlinear plug-in complements vary.",
      "gaps": [
        "Brochure date is deliberately null until independently verified.",
        "Brochure accuracy claims are not substituted for an installed machine calibration."
      ],
      "insight": "Why does a waveform display need a time-base channel as well as the computed solution?",
      "fields": {
        "state": {
          "value": "Scaled analog voltages within ±10 V",
          "locator": "p. 6",
          "source": "alt-pace-tr10"
        },
        "compute": {
          "value": "Patched integrators and inverter",
          "locator": "p. 6",
          "source": "alt-pace-tr10"
        },
        "memory": {
          "value": "Integration capacitor state",
          "locator": "p. 6",
          "source": "alt-pace-tr10"
        },
        "control": {
          "value": "Reset, hold, operate and repetitive controls",
          "locator": "p. 4",
          "source": "alt-pace-tr10"
        },
        "io": {
          "value": "Null meter and optional external plotter/display",
          "locator": "p. 4",
          "source": "alt-pace-tr10"
        },
        "software": {
          "value": "Physical patching and attenuator settings",
          "locator": "pp. 2, 6",
          "source": "alt-pace-tr10"
        },
        "workload": {
          "value": "Second-order linear differential equation",
          "locator": "p. 6",
          "source": "alt-pace-tr10"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Solution channel and display time base",
        "scope": "Original functional diagram of the brochure example; coefficients aggregate potentiometers and input gains.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "constant",
            "label": "Reference / forcing",
            "subtitle": "CONSTANT INPUT",
            "text": "Supplies the driving term.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-pace-tr10",
            "locator": "p. 6",
            "control": false
          },
          {
            "id": "first",
            "label": "First integrator",
            "subtitle": "SCALED DERIVATIVE",
            "text": "Combines feedback and integrates.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-pace-tr10",
            "locator": "p. 6",
            "control": false
          },
          {
            "id": "second",
            "label": "Second integrator",
            "subtitle": "SCALED SOLUTION",
            "text": "Produces displacement-like output.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-pace-tr10",
            "locator": "p. 6",
            "control": false
          },
          {
            "id": "invert",
            "label": "Feedback inverter",
            "subtitle": "SIGN CHANGE",
            "text": "Returns the solution term.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-pace-tr10",
            "locator": "p. 6",
            "control": false
          },
          {
            "id": "damping",
            "label": "Damping attenuator",
            "subtitle": "PARAMETER",
            "text": "Scales derivative feedback.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-pace-tr10",
            "locator": "p. 6",
            "control": false
          },
          {
            "id": "time",
            "label": "Time-base integrator",
            "subtitle": "RAMP",
            "text": "Integrates a constant.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-pace-tr10",
            "locator": "p. 6",
            "control": false
          },
          {
            "id": "mode",
            "label": "Mode / repetition",
            "subtitle": "CONTROL PANEL",
            "text": "Sets reset, hold and run.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-pace-tr10",
            "locator": "p. 4",
            "control": true
          },
          {
            "id": "display",
            "label": "External display",
            "subtitle": "X / Y INPUTS",
            "text": "Plots solution against time.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-pace-tr10",
            "locator": "pp. 4, 6",
            "control": false
          },
          {
            "id": "meter",
            "label": "Null voltmeter",
            "subtitle": "SETUP / READOUT",
            "text": "Checks coefficients and outputs.",
            "x": 30,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-pace-tr10",
            "locator": "p. 4",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "constant",
            "to": "first",
            "type": "data",
            "locator": "p. 6",
            "label": "",
            "source": "alt-pace-tr10"
          },
          {
            "from": "first",
            "to": "second",
            "type": "data",
            "locator": "p. 6",
            "label": "",
            "source": "alt-pace-tr10"
          },
          {
            "from": "second",
            "to": "invert",
            "type": "data",
            "locator": "p. 6",
            "label": "",
            "source": "alt-pace-tr10"
          },
          {
            "from": "invert",
            "to": "first",
            "type": "data",
            "locator": "p. 6",
            "label": "",
            "source": "alt-pace-tr10"
          },
          {
            "from": "first",
            "to": "damping",
            "type": "data",
            "locator": "p. 6",
            "label": "",
            "source": "alt-pace-tr10"
          },
          {
            "from": "damping",
            "to": "first",
            "type": "data",
            "locator": "p. 6",
            "label": "",
            "source": "alt-pace-tr10"
          },
          {
            "from": "constant",
            "to": "time",
            "type": "data",
            "locator": "p. 6",
            "label": "",
            "source": "alt-pace-tr10"
          },
          {
            "from": "time",
            "to": "display",
            "type": "data",
            "locator": "p. 6",
            "label": "time axis",
            "source": "alt-pace-tr10"
          },
          {
            "from": "second",
            "to": "display",
            "type": "data",
            "locator": "p. 6",
            "label": "solution axis",
            "source": "alt-pace-tr10"
          },
          {
            "from": "mode",
            "to": "first",
            "type": "control",
            "locator": "p. 4",
            "label": "",
            "source": "alt-pace-tr10"
          },
          {
            "from": "mode",
            "to": "second",
            "type": "control",
            "locator": "p. 4",
            "label": "",
            "source": "alt-pace-tr10"
          },
          {
            "from": "first",
            "to": "meter",
            "type": "data",
            "locator": "p. 4",
            "label": "",
            "source": "alt-pace-tr10"
          }
        ]
      },
      "originalCandidate": "PACE analog computer"
    },
    {
      "id": "queue-123",
      "name": "EAI HYDAC 2400",
      "organization": "Electronic Associates, Inc.",
      "year": 1964,
      "yearLabel": "1964 seminar configuration",
      "kind": "Analog–digital hybrid computer",
      "status": "dossier",
      "track": "analog",
      "trackName": "Analog, hybrid & physical dynamics",
      "discoveryParadigms": [
        "analog",
        "unconventional",
        "hybrid"
      ],
      "paradigms": [
        "analog",
        "digital",
        "hybrid",
        "parallel"
      ],
      "architectures": [
        "analog-integrator",
        "heterogeneous"
      ],
      "substrates": [
        "vacuum-tube",
        "transistor"
      ],
      "models": [
        "continuous",
        "register"
      ],
      "aliases": [],
      "sources": [
        "alt-hydac2400"
      ],
      "summary": "Three cooperating computers divide continuous dynamics, parallel control/conversion and sequential numerical computation.",
      "config": "231R-V analog section + DOS 350 parallel digital operations + EAI 375 (3C DDP-24) sequential digital computer, as specified in the seminar.",
      "gaps": [
        "Memory figures are product options, not a verified installed capacity.",
        "Several software aids are explicitly prospective in the 1964 account."
      ],
      "insight": "Why does the hybrid interface need event signals as well as numerical conversion?",
      "fields": {
        "state": {
          "value": "Analog voltages and 24-bit sign-magnitude words",
          "locator": "Chapter 2 §IV",
          "source": "alt-hydac2400"
        },
        "compute": {
          "value": "231R-V, DOS 350 and 375 cooperate",
          "locator": "Fig. 11",
          "source": "alt-hydac2400"
        },
        "memory": {
          "value": "Analog storage and 375 random-access memory",
          "locator": "Chapter 2 §IV",
          "source": "alt-hydac2400"
        },
        "control": {
          "value": "DOS timing, sense lines and prioritized interrupts",
          "locator": "pp. 26–27",
          "source": "alt-hydac2400"
        },
        "io": {
          "value": "Multiplexed ADC/DAC plus comparator / DA-switch interface",
          "locator": "pp. 26–27",
          "source": "alt-hydac2400"
        },
        "software": {
          "value": "Digital routines plus patched analog/logic programs",
          "locator": "Chapter 5",
          "source": "alt-hydac2400"
        },
        "workload": {
          "value": "Partitioned aerospace / re-entry simulation",
          "locator": "Chapter 3",
          "source": "alt-hydac2400"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Three computing sections, two kinds of communication",
        "scope": "Fig. 11 organization; prospective HYTRAN/compiler features remain developmental.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "analog",
            "label": "231R-V analog",
            "subtitle": "CONTINUOUS",
            "text": "Solves selected dynamic equations.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-hydac2400",
            "locator": "Chapter 2 §IV.A",
            "control": false
          },
          {
            "id": "sample",
            "label": "Multiplexer / ADC",
            "subtitle": "WHOLE-WORD INPUT",
            "text": "Samples selected voltages.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-hydac2400",
            "locator": "Chapter 2 §IV.C",
            "control": false
          },
          {
            "id": "dos",
            "label": "DOS 350",
            "subtitle": "PARALLEL CONTROL",
            "text": "Sequences and communicates.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-hydac2400",
            "locator": "Chapter 2 §IV.C",
            "control": false
          },
          {
            "id": "cpu",
            "label": "375 / DDP-24",
            "subtitle": "SEQUENTIAL DIGITAL",
            "text": "Executes numerical routines.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-hydac2400",
            "locator": "Chapter 2 §IV.B",
            "control": false
          },
          {
            "id": "mem",
            "label": "375 memory",
            "subtitle": "4K–32K WORD OPTIONS",
            "text": "Stores programs and values.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-hydac2400",
            "locator": "Chapter 2 §IV.B",
            "control": false
          },
          {
            "id": "dac",
            "label": "DAC output",
            "subtitle": "WHOLE-WORD OUTPUT",
            "text": "Returns numerical values.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-hydac2400",
            "locator": "Chapter 2 §IV.C",
            "control": false
          },
          {
            "id": "compare",
            "label": "Analog comparator",
            "subtitle": "EVENT SIGNAL",
            "text": "Reports an analog condition.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-hydac2400",
            "locator": "p. 27",
            "control": false
          },
          {
            "id": "switch",
            "label": "DA switch / mode",
            "subtitle": "LOGIC TO ANALOG",
            "text": "Gates signals and changes modes.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-hydac2400",
            "locator": "p. 27",
            "control": false
          },
          {
            "id": "io",
            "label": "Input / output desk",
            "subtitle": "PROGRAM + READOUT",
            "text": "Supports setup and records.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-hydac2400",
            "locator": "Fig. 11",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "analog",
            "to": "sample",
            "type": "data",
            "locator": "Chapter 2 §IV.C",
            "label": "",
            "source": "alt-hydac2400"
          },
          {
            "from": "sample",
            "to": "dos",
            "type": "data",
            "locator": "Chapter 2 §IV.C",
            "label": "",
            "source": "alt-hydac2400"
          },
          {
            "from": "dos",
            "to": "cpu",
            "type": "data",
            "locator": "Chapter 2 §IV.C",
            "label": "",
            "source": "alt-hydac2400"
          },
          {
            "from": "cpu",
            "to": "mem",
            "type": "data",
            "locator": "Chapter 2 §IV.B",
            "label": "",
            "source": "alt-hydac2400"
          },
          {
            "from": "mem",
            "to": "cpu",
            "type": "data",
            "locator": "Chapter 2 §IV.B",
            "label": "",
            "source": "alt-hydac2400"
          },
          {
            "from": "cpu",
            "to": "dos",
            "type": "data",
            "locator": "Chapter 2 §IV.C",
            "label": "",
            "source": "alt-hydac2400"
          },
          {
            "from": "dos",
            "to": "dac",
            "type": "data",
            "locator": "Chapter 2 §IV.C",
            "label": "",
            "source": "alt-hydac2400"
          },
          {
            "from": "dac",
            "to": "analog",
            "type": "data",
            "locator": "Chapter 2 §IV.C",
            "label": "",
            "source": "alt-hydac2400"
          },
          {
            "from": "analog",
            "to": "compare",
            "type": "data",
            "locator": "p. 27",
            "label": "",
            "source": "alt-hydac2400"
          },
          {
            "from": "compare",
            "to": "dos",
            "type": "control",
            "locator": "p. 27",
            "label": "",
            "source": "alt-hydac2400"
          },
          {
            "from": "dos",
            "to": "switch",
            "type": "control",
            "locator": "p. 27",
            "label": "",
            "source": "alt-hydac2400"
          },
          {
            "from": "switch",
            "to": "analog",
            "type": "control",
            "locator": "p. 27",
            "label": "",
            "source": "alt-hydac2400"
          },
          {
            "from": "dos",
            "to": "cpu",
            "type": "control",
            "locator": "p. 27",
            "label": "sense / interrupt",
            "source": "alt-hydac2400"
          },
          {
            "from": "io",
            "to": "cpu",
            "type": "control",
            "locator": "Fig. 11",
            "label": "",
            "source": "alt-hydac2400"
          }
        ]
      },
      "originalCandidate": "HYDAC 2400 hybrid computer"
    },
    {
      "id": "queue-124",
      "name": "Phillips hydraulic national-income model (1950)",
      "organization": "A. W. Phillips / Leeds and LSE",
      "year": 1950,
      "yearLabel": "1950 published hydraulic model",
      "kind": "Hydraulic economic analog computer",
      "status": "dossier",
      "track": "analog",
      "trackName": "Analog, hybrid & physical dynamics",
      "discoveryParadigms": [
        "analog",
        "unconventional"
      ],
      "paradigms": [
        "analog",
        "unconventional"
      ],
      "architectures": [
        "fluidic",
        "analog-integrator"
      ],
      "substrates": [
        "fluid",
        "mechanical"
      ],
      "models": [
        "continuous"
      ],
      "aliases": [],
      "sources": [
        "alt-phillips1950"
      ],
      "summary": "Water stocks and flow controls implement an economic dynamical model, with mechanical feedback and chart readout.",
      "config": "National-income/savings/investment model of Fig. 3 in Phillips (1950), not every later MONIAC arrangement.",
      "gaps": [
        "Model relationships and nonlinear curves are chosen by the operator.",
        "The article distinguishes the completed Leeds machine from an improved LSE version under construction."
      ],
      "insight": "How do stored money balances create a lag between expenditure and income?",
      "fields": {
        "state": {
          "value": "Water levels and flows represent balances and money rates",
          "locator": "pp. 290–292",
          "source": "alt-phillips1950"
        },
        "compute": {
          "value": "Hydraulic integration and valve characteristics",
          "locator": "Fig. 3",
          "source": "alt-phillips1950"
        },
        "memory": {
          "value": "Active balance M1 and idle balance M2 tanks",
          "locator": "Fig. 3",
          "source": "alt-phillips1950"
        },
        "control": {
          "value": "Floats, linkages and adjustable function curves",
          "locator": "Fig. 3",
          "source": "alt-phillips1950"
        },
        "io": {
          "value": "Mechanical recorder; adjustable external money supply",
          "locator": "pp. 291–292",
          "source": "alt-phillips1950"
        },
        "software": {
          "value": "Physical economic relationships and settings",
          "locator": "pp. 283, 287",
          "source": "alt-phillips1950"
        },
        "workload": {
          "value": "Exposition of economic dynamics",
          "locator": "p. 283",
          "source": "alt-phillips1950"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Savings and investment around two money stocks",
        "scope": "Fig. 3 closed-economy model; operator-selected economic assumptions.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "m1",
            "label": "Active balances M1",
            "subtitle": "WATER STOCK",
            "text": "Supplies the circulating flow.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-phillips1950",
            "locator": "Fig. 3",
            "control": false
          },
          {
            "id": "pump",
            "label": "Electric pump",
            "subtitle": "CIRCULATION",
            "text": "Lifts income flow to the top.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-phillips1950",
            "locator": "p. 291",
            "control": false
          },
          {
            "id": "split",
            "label": "Savings valves",
            "subtitle": "FLOW DIVISION",
            "text": "Splits saving from consumption.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-phillips1950",
            "locator": "p. 291",
            "control": false
          },
          {
            "id": "m2",
            "label": "Idle balances M2",
            "subtitle": "WATER STOCK",
            "text": "Accumulates savings.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-phillips1950",
            "locator": "p. 291",
            "control": false
          },
          {
            "id": "invest",
            "label": "Investment valves",
            "subtitle": "RETURN FLOW",
            "text": "Controls investment expenditure.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-phillips1950",
            "locator": "p. 291",
            "control": false
          },
          {
            "id": "consume",
            "label": "Consumption C",
            "subtitle": "RESIDUAL FLOW",
            "text": "Returns directly toward M1.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-phillips1950",
            "locator": "p. 291",
            "control": false
          },
          {
            "id": "external",
            "label": "Movable supply box",
            "subtitle": "EXTERNAL CONDITION",
            "text": "Adds or withdraws money.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-phillips1950",
            "locator": "p. 291",
            "control": false
          },
          {
            "id": "link",
            "label": "Float / function links",
            "subtitle": "FEEDBACK",
            "text": "Makes flows depend on levels.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-phillips1950",
            "locator": "Fig. 3",
            "control": false
          },
          {
            "id": "record",
            "label": "Income recorder",
            "subtitle": "MECHANICAL OUTPUT",
            "text": "Traces evolution against time.",
            "x": 30,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-phillips1950",
            "locator": "p. 292",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "m1",
            "to": "pump",
            "type": "data",
            "locator": "p. 291",
            "label": "",
            "source": "alt-phillips1950"
          },
          {
            "from": "pump",
            "to": "split",
            "type": "data",
            "locator": "p. 291",
            "label": "",
            "source": "alt-phillips1950"
          },
          {
            "from": "split",
            "to": "m2",
            "type": "data",
            "locator": "p. 291",
            "label": "saving",
            "source": "alt-phillips1950"
          },
          {
            "from": "split",
            "to": "consume",
            "type": "data",
            "locator": "p. 291",
            "label": "",
            "source": "alt-phillips1950"
          },
          {
            "from": "m2",
            "to": "invest",
            "type": "data",
            "locator": "p. 291",
            "label": "",
            "source": "alt-phillips1950"
          },
          {
            "from": "invest",
            "to": "m1",
            "type": "data",
            "locator": "p. 291",
            "label": "",
            "source": "alt-phillips1950"
          },
          {
            "from": "consume",
            "to": "m1",
            "type": "data",
            "locator": "p. 291",
            "label": "",
            "source": "alt-phillips1950"
          },
          {
            "from": "external",
            "to": "m2",
            "type": "data",
            "locator": "p. 291",
            "label": "",
            "source": "alt-phillips1950"
          },
          {
            "from": "m2",
            "to": "link",
            "type": "data",
            "locator": "Fig. 3",
            "label": "",
            "source": "alt-phillips1950"
          },
          {
            "from": "link",
            "to": "split",
            "type": "control",
            "locator": "Fig. 3",
            "label": "",
            "source": "alt-phillips1950"
          },
          {
            "from": "link",
            "to": "invest",
            "type": "control",
            "locator": "Fig. 3",
            "label": "",
            "source": "alt-phillips1950"
          },
          {
            "from": "m1",
            "to": "record",
            "type": "data",
            "locator": "p. 292",
            "label": "",
            "source": "alt-phillips1950"
          }
        ]
      },
      "originalCandidate": "MONIAC"
    },
    {
      "id": "queue-125",
      "name": "Lukyanov 1-IGL-1-3 museum specimen",
      "organization": "Ryazan SAM / Polytechnic Museum, Moscow",
      "year": 2000,
      "yearLabel": "2000 museum documentation of preserved machine",
      "kind": "Preserved hydraulic analog computer",
      "status": "dossier",
      "track": "analog",
      "trackName": "Analog, hybrid & physical dynamics",
      "discoveryParadigms": [
        "analog",
        "unconventional"
      ],
      "paradigms": [
        "analog",
        "unconventional"
      ],
      "architectures": [
        "fluidic",
        "analog-integrator"
      ],
      "substrates": [
        "fluid",
        "mechanical"
      ],
      "models": [
        "continuous"
      ],
      "aliases": [],
      "sources": [
        "alt-lukyanov-museum"
      ],
      "summary": "Connected water vessels evolve an analog thermal model; movable boundary vessels and manual level records close the computation loop.",
      "config": "One-dimensional 1-IGL-1-3 named in the museum illustration; diagram shows the account’s documented method, not a complete specimen piping plan.",
      "gaps": [
        "Original technical manual and specimen-specific metrology remain unavailable.",
        "The 2000 date is a documentation event, not invention or manufacture."
      ],
      "insight": "How do changing boundary conditions enter a hydraulic differential-equation solution?",
      "fields": {
        "state": {
          "value": "Water heads represent modeled thermal variables",
          "locator": "Apparatus and run paragraphs",
          "source": "alt-lukyanov-museum"
        },
        "compute": {
          "value": "Flow through adjustable hydraulic resistances",
          "locator": "Apparatus paragraph",
          "source": "alt-lukyanov-museum"
        },
        "memory": {
          "value": "Water levels in connected vessels",
          "locator": "Setup and run paragraphs",
          "source": "alt-lukyanov-museum"
        },
        "control": {
          "value": "Common valves and movable vessels",
          "locator": "Apparatus paragraph",
          "source": "alt-lukyanov-museum"
        },
        "io": {
          "value": "Boundary-condition drum and piezometer readings",
          "locator": "Detailed illustration description",
          "source": "alt-lukyanov-museum"
        },
        "software": {
          "value": "Physical model layout, resistances and initial levels",
          "locator": "Four-step setup",
          "source": "alt-lukyanov-museum"
        },
        "workload": {
          "value": "One-dimensional transient hydraulic analog model",
          "locator": "Specimen caption; model discussion",
          "source": "alt-lukyanov-museum"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Boundary-condition control and level readout",
        "scope": "Custodially documented operating principle. Vessel count and exact specimen interconnections remain unverified.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "model",
            "label": "Model preparation",
            "subtitle": "OPERATOR",
            "text": "Chooses network and resistances.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-lukyanov-museum",
            "locator": "Four-step setup",
            "control": false
          },
          {
            "id": "initial",
            "label": "Initial water levels",
            "subtitle": "INITIAL CONDITIONS",
            "text": "Sets heads with valves closed.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-lukyanov-museum",
            "locator": "Run paragraph",
            "control": false
          },
          {
            "id": "vessels",
            "label": "Connected vessels",
            "subtitle": "CONTINUOUS STATE",
            "text": "Retains evolving water levels.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-lukyanov-museum",
            "locator": "Apparatus paragraph",
            "control": false
          },
          {
            "id": "resist",
            "label": "Resistance tubes",
            "subtitle": "FLOW LINKS",
            "text": "Sets inter-vessel coupling.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-lukyanov-museum",
            "locator": "Apparatus paragraph",
            "control": false
          },
          {
            "id": "boundary",
            "label": "Boundary-condition graph",
            "subtitle": "ROTATING DRUM",
            "text": "Specifies external variation.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-lukyanov-museum",
            "locator": "Detailed illustration description",
            "control": false
          },
          {
            "id": "moving",
            "label": "Movable vessels",
            "subtitle": "VARIABLE HEAD",
            "text": "Applies graph-following boundaries.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-lukyanov-museum",
            "locator": "Detailed illustration description",
            "control": false
          },
          {
            "id": "valves",
            "label": "Common valve control",
            "subtitle": "START / STOP",
            "text": "Releases or arrests flow.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-lukyanov-museum",
            "locator": "Apparatus paragraph",
            "control": true
          },
          {
            "id": "piezo",
            "label": "Piezometer levels",
            "subtitle": "OBSERVATION",
            "text": "Shows model state.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-lukyanov-museum",
            "locator": "Readout paragraph",
            "control": false
          },
          {
            "id": "paper",
            "label": "Graph-paper record",
            "subtitle": "RESULT",
            "text": "Records solution snapshots.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-lukyanov-museum",
            "locator": "Readout paragraph",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "model",
            "to": "resist",
            "type": "control",
            "locator": "Four-step setup",
            "label": "",
            "source": "alt-lukyanov-museum"
          },
          {
            "from": "initial",
            "to": "vessels",
            "type": "control",
            "locator": "Run paragraph",
            "label": "",
            "source": "alt-lukyanov-museum"
          },
          {
            "from": "vessels",
            "to": "resist",
            "type": "association",
            "locator": "Apparatus paragraph",
            "label": "",
            "source": "alt-lukyanov-museum"
          },
          {
            "from": "resist",
            "to": "vessels",
            "type": "association",
            "locator": "Apparatus paragraph",
            "label": "",
            "source": "alt-lukyanov-museum"
          },
          {
            "from": "boundary",
            "to": "moving",
            "type": "control",
            "locator": "Detailed illustration description",
            "label": "",
            "source": "alt-lukyanov-museum"
          },
          {
            "from": "moving",
            "to": "vessels",
            "type": "data",
            "locator": "Run paragraph",
            "label": "",
            "source": "alt-lukyanov-museum"
          },
          {
            "from": "valves",
            "to": "resist",
            "type": "control",
            "locator": "Apparatus paragraph",
            "label": "",
            "source": "alt-lukyanov-museum"
          },
          {
            "from": "vessels",
            "to": "piezo",
            "type": "data",
            "locator": "Readout paragraph",
            "label": "",
            "source": "alt-lukyanov-museum"
          },
          {
            "from": "piezo",
            "to": "paper",
            "type": "data",
            "locator": "Readout paragraph",
            "label": "",
            "source": "alt-lukyanov-museum"
          },
          {
            "from": "valves",
            "to": "paper",
            "type": "control",
            "locator": "Readout paragraph",
            "label": "stop for readings",
            "source": "alt-lukyanov-museum"
          }
        ]
      },
      "originalCandidate": "Lukyanov water integrator"
    },
    {
      "id": "queue-126",
      "name": "Anadigm AN231E04 FPAA",
      "organization": "Anadigm",
      "year": 2021,
      "yearLabel": "2021 datasheet revision",
      "kind": "Field-programmable analog processor",
      "status": "dossier",
      "track": "analog",
      "trackName": "Analog, hybrid & physical dynamics",
      "discoveryParadigms": [
        "analog",
        "unconventional"
      ],
      "paradigms": [
        "analog",
        "hybrid",
        "dataflow"
      ],
      "architectures": [
        "reconfigurable"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "continuous",
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "alt-an231e04"
      ],
      "summary": "Four configurable analog blocks form a reconfigurable signal path while shadow SRAM permits background configuration loading.",
      "config": "AN231E04 architecture in datasheet rev. 1.5; the date identifies this documentation revision, not original device introduction.",
      "gaps": [
        "Bandwidth and precision depend on the mapped CAM and clock settings.",
        "Configurable analog fabric is not interchangeable with a digital FPGA’s gate fabric."
      ],
      "insight": "Why must signal paths, sampled-analog clocks and configuration activation be considered separately?",
      "fields": {
        "state": {
          "value": "Differential analog signals and programmed settings",
          "locator": "p. 3",
          "source": "alt-an231e04"
        },
        "compute": {
          "value": "2 × 2 configurable analog-block matrix",
          "locator": "p. 3",
          "source": "alt-an231e04"
        },
        "memory": {
          "value": "Active / shadow configuration SRAM; 256-byte LUT",
          "locator": "p. 3",
          "source": "alt-an231e04"
        },
        "control": {
          "value": "SPI-like loading and clock generation",
          "locator": "p. 3",
          "source": "alt-an231e04"
        },
        "io": {
          "value": "Configurable analog I/O cells",
          "locator": "p. 3; Fig. 1",
          "source": "alt-an231e04"
        },
        "software": {
          "value": "AnadigmDesigner2 CAM-to-CAB mapping",
          "locator": "p. 3",
          "source": "alt-an231e04"
        },
        "workload": {
          "value": "Filtering, signal conditioning and nonlinear functions",
          "locator": "p. 3",
          "source": "alt-an231e04"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Signal fabric under shadowed configuration control",
        "scope": "Functional hierarchy of Fig. 1; CAMs are software functions mapped onto CAB resources, not additional physical processors.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "host",
            "label": "Designer / host",
            "subtitle": "CONFIGURATION",
            "text": "Maps and loads a circuit.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-an231e04",
            "locator": "p. 3",
            "control": false
          },
          {
            "id": "serial",
            "label": "Serial configuration",
            "subtitle": "SPI-LIKE",
            "text": "Receives configuration data.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-an231e04",
            "locator": "p. 3",
            "control": false
          },
          {
            "id": "shadow",
            "label": "Shadow SRAM",
            "subtitle": "BACKGROUND LOAD",
            "text": "Holds a pending configuration.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-an231e04",
            "locator": "p. 3",
            "control": false
          },
          {
            "id": "active",
            "label": "Active configuration",
            "subtitle": "SWITCH CONTROL",
            "text": "Selects the running circuit.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-an231e04",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "io",
            "label": "Analog I/O cells",
            "subtitle": "DIFFERENTIAL PORTS",
            "text": "Interfaces external signals.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-an231e04",
            "locator": "p. 3",
            "control": false
          },
          {
            "id": "route",
            "label": "Programmable routing",
            "subtitle": "SIGNAL CONNECTIONS",
            "text": "Connects I/O and CABs.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-an231e04",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "cabs",
            "label": "Four CABs",
            "subtitle": "ANALOG COMPUTE",
            "text": "Implements mapped functions.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-an231e04",
            "locator": "p. 3",
            "control": false
          },
          {
            "id": "clock",
            "label": "Clock generator",
            "subtitle": "NONOVERLAP DOMAINS",
            "text": "Times analog operations.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-an231e04",
            "locator": "p. 3",
            "control": true
          },
          {
            "id": "ref",
            "label": "Reference generator",
            "subtitle": "BAND-GAP",
            "text": "Supplies reference voltages.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-an231e04",
            "locator": "p. 3",
            "control": false
          },
          {
            "id": "lut",
            "label": "8 × 256-bit LUT",
            "subtitle": "FUNCTION SUPPORT",
            "text": "Supports nonlinear synthesis.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-an231e04",
            "locator": "p. 3",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "serial",
            "type": "control",
            "locator": "p. 3",
            "label": "",
            "source": "alt-an231e04"
          },
          {
            "from": "serial",
            "to": "shadow",
            "type": "data",
            "locator": "p. 3",
            "label": "",
            "source": "alt-an231e04"
          },
          {
            "from": "shadow",
            "to": "active",
            "type": "control",
            "locator": "p. 3",
            "label": "",
            "source": "alt-an231e04"
          },
          {
            "from": "active",
            "to": "route",
            "type": "control",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-an231e04"
          },
          {
            "from": "active",
            "to": "cabs",
            "type": "control",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-an231e04"
          },
          {
            "from": "io",
            "to": "route",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-an231e04"
          },
          {
            "from": "route",
            "to": "cabs",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-an231e04"
          },
          {
            "from": "cabs",
            "to": "route",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-an231e04"
          },
          {
            "from": "route",
            "to": "io",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-an231e04"
          },
          {
            "from": "clock",
            "to": "cabs",
            "type": "control",
            "locator": "p. 3",
            "label": "",
            "source": "alt-an231e04"
          },
          {
            "from": "ref",
            "to": "cabs",
            "type": "association",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-an231e04"
          },
          {
            "from": "lut",
            "to": "cabs",
            "type": "association",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-an231e04"
          }
        ]
      },
      "originalCandidate": "FPAA analog computing systems"
    },
    {
      "id": "queue-127",
      "name": "Wang–Roychowdhury 32-oscillator Ising prototype",
      "organization": "UC Berkeley",
      "year": 2019,
      "yearLabel": "2019 hardware account",
      "kind": "Electronic optimization experiment",
      "status": "dossier",
      "track": "analog",
      "trackName": "Analog, hybrid & physical dynamics",
      "discoveryParadigms": [
        "analog",
        "unconventional",
        "probabilistic"
      ],
      "paradigms": [
        "analog",
        "probabilistic"
      ],
      "architectures": [
        "ising-machine"
      ],
      "substrates": [
        "integrated",
        "transistor"
      ],
      "models": [
        "ising",
        "continuous"
      ],
      "aliases": [],
      "sources": [
        "alt-wang-oim"
      ],
      "summary": "Resistively coupled LC oscillator phases encode spins, with injection locking and electronic phase readout.",
      "config": "32-node perfboard prototype, Chimera-like connectivity, rotary coupling potentiometers and sign-selecting jumpers.",
      "gaps": [
        "Global optimality is not guaranteed on every run.",
        "Larger benchmark results in this chapter are simulations, not this 32-node hardware."
      ],
      "insight": "How does phase readout turn a continuous waveform into an Ising spin assignment?",
      "fields": {
        "state": {
          "value": "Oscillator phases relative to a reference",
          "locator": "§4.1",
          "source": "alt-wang-oim"
        },
        "compute": {
          "value": "Coupled nonlinear LC oscillators",
          "locator": "§4.1",
          "source": "alt-wang-oim"
        },
        "memory": {
          "value": "Evolving phase state; fixed coupling settings",
          "locator": "§4.1",
          "source": "alt-wang-oim"
        },
        "control": {
          "value": "SYNC injection and programmable resistive couplings",
          "locator": "§§3–4.1",
          "source": "alt-wang-oim"
        },
        "io": {
          "value": "XOR phase detectors and logic analyzer",
          "locator": "§4.1",
          "source": "alt-wang-oim"
        },
        "software": {
          "value": "Graph weights mapped to physical connections",
          "locator": "§4.1",
          "source": "alt-wang-oim"
        },
        "workload": {
          "value": "Small Ising / maximum-cut instances",
          "locator": "§4.1",
          "source": "alt-wang-oim"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Continuous phases, resistive weights, digital spin readout",
        "scope": "32-node hardware, not the much larger simulated G-set networks. Coupling graph is grouped, not all-to-all.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "graph",
            "label": "Ising coefficients",
            "subtitle": "CLASSICAL PROBLEM",
            "text": "Sets coupling weights and signs.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-wang-oim",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "pot",
            "label": "Rotary potentiometers",
            "subtitle": "COUPLING MAGNITUDE",
            "text": "Sets resistive strength.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-wang-oim",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "jump",
            "label": "Polarity jumpers",
            "subtitle": "COUPLING SIGN",
            "text": "Chooses interaction polarity.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-wang-oim",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "network",
            "label": "32 LC oscillators",
            "subtitle": "PHASE SPINS",
            "text": "Evolves on a sparse graph.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-wang-oim",
            "locator": "Fig. 9",
            "control": false
          },
          {
            "id": "sync",
            "label": "SYNC / reference",
            "subtitle": "INJECTION LOCKING",
            "text": "Supports binary phase states.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-wang-oim",
            "locator": "§§3–4.1",
            "control": true
          },
          {
            "id": "xor",
            "label": "XOR phase detectors",
            "subtitle": "REFERENCE COMPARISON",
            "text": "Converts phase to voltage levels.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-wang-oim",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "logic",
            "label": "Logic analyzer",
            "subtitle": "CLASSICAL READOUT",
            "text": "Collects spin assignments.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-wang-oim",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "usb",
            "label": "Analog Discovery 2",
            "subtitle": "POWER / INSTRUMENTS",
            "text": "Supplies and observes the setup.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-wang-oim",
            "locator": "§4.1",
            "control": false
          },
          {
            "id": "energy",
            "label": "Objective assessment",
            "subtitle": "REPEATED RUNS",
            "text": "Evaluates observed states.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-wang-oim",
            "locator": "Fig. 9c",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "graph",
            "to": "pot",
            "type": "control",
            "locator": "§4.1",
            "label": "",
            "source": "alt-wang-oim"
          },
          {
            "from": "graph",
            "to": "jump",
            "type": "control",
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            "label": "",
            "source": "alt-wang-oim"
          },
          {
            "from": "pot",
            "to": "network",
            "type": "association",
            "locator": "§4.1",
            "label": "",
            "source": "alt-wang-oim"
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          {
            "from": "jump",
            "to": "network",
            "type": "association",
            "locator": "§4.1",
            "label": "",
            "source": "alt-wang-oim"
          },
          {
            "from": "sync",
            "to": "network",
            "type": "control",
            "locator": "§§3–4.1",
            "label": "",
            "source": "alt-wang-oim"
          },
          {
            "from": "network",
            "to": "xor",
            "type": "data",
            "locator": "§4.1",
            "label": "",
            "source": "alt-wang-oim"
          },
          {
            "from": "sync",
            "to": "xor",
            "type": "data",
            "locator": "§4.1",
            "label": "",
            "source": "alt-wang-oim"
          },
          {
            "from": "xor",
            "to": "logic",
            "type": "data",
            "locator": "§4.1",
            "label": "",
            "source": "alt-wang-oim"
          },
          {
            "from": "usb",
            "to": "network",
            "type": "association",
            "locator": "§4.1",
            "label": "power",
            "source": "alt-wang-oim"
          },
          {
            "from": "logic",
            "to": "energy",
            "type": "data",
            "locator": "Fig. 9c",
            "label": "",
            "source": "alt-wang-oim"
          }
        ]
      },
      "originalCandidate": "Coupled-oscillator Ising prototypes"
    },
    {
      "id": "queue-128",
      "name": "Yaremkevich phonon–magnon reservoir",
      "organization": "TU Dortmund / Loughborough / Nottingham and collaborators",
      "year": 2023,
      "yearLabel": "December 2023 experiment",
      "kind": "Acoustic / spin-wave reservoir experiment",
      "status": "dossier",
      "track": "analog",
      "trackName": "Analog, hybrid & physical dynamics",
      "discoveryParadigms": [
        "analog",
        "unconventional",
        "reservoir"
      ],
      "paradigms": [
        "analog",
        "reservoir",
        "hybrid",
        "unconventional"
      ],
      "architectures": [
        "reservoir-arch"
      ],
      "substrates": [
        "acoustic",
        "magnetic",
        "photonic"
      ],
      "models": [
        "continuous",
        "neural"
      ],
      "aliases": [],
      "sources": [
        "alt-phonon-magnon"
      ],
      "summary": "Laser-generated acoustic modes propagate in a semiconductor waveguide and interact with magnons before optical readout.",
      "config": "GaAs/AlAs waveguide capped by patterned FeGa; visual shapes drawn by a write laser are classified using a PC ANN.",
      "gaps": [
        "The paper states the nonlinear contribution is manifested only indirectly.",
        "Wave frequency is not end-to-end classification throughput; optical acquisition and averaging matter."
      ],
      "insight": "Which physical transformation belongs to the reservoir, and which recognition step remains on the PC?",
      "fields": {
        "state": {
          "value": "Multimode phonon/magnon wavepackets",
          "locator": "Fig. 1",
          "source": "alt-phonon-magnon"
        },
        "compute": {
          "value": "Wave propagation, interference and mode interaction",
          "locator": "Results",
          "source": "alt-phonon-magnon"
        },
        "memory": {
          "value": "Transient propagating mode content",
          "locator": "Results",
          "source": "alt-phonon-magnon"
        },
        "control": {
          "value": "Laser position/timing and applied magnetic field",
          "locator": "Methods; Fig. 2",
          "source": "alt-phonon-magnon"
        },
        "io": {
          "value": "Kerr rotation and balanced photoreceiver",
          "locator": "Methods",
          "source": "alt-phonon-magnon"
        },
        "software": {
          "value": "Trajectory integration and PC ANN readout",
          "locator": "Results",
          "source": "alt-phonon-magnon"
        },
        "workload": {
          "value": "Visual-shape recognition",
          "locator": "Fig. 3",
          "source": "alt-phonon-magnon"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Optical input → acoustic reservoir → magnon readout",
        "scope": "Laboratory system boundary includes both lasers and the classical classifier; an integrated device does not imply an integrated complete computer.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "shape",
            "label": "Shape trajectory",
            "subtitle": "CLASSICAL INPUT",
            "text": "Sets write-spot positions.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-phonon-magnon",
            "locator": "Methods: Sequential drawing",
            "control": false
          },
          {
            "id": "write",
            "label": "Write laser",
            "subtitle": "ULTRAFAST PULSES",
            "text": "Excites the patterned layer.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-phonon-magnon",
            "locator": "Methods: Optical writing",
            "control": false
          },
          {
            "id": "grating",
            "label": "FeGa nanograting",
            "subtitle": "TRANSDUCTION",
            "text": "Generates multimode phonons.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-phonon-magnon",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "wave",
            "label": "GaAs/AlAs waveguide",
            "subtitle": "ACOUSTIC RESERVOIR",
            "text": "Propagates and mixes modes.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-phonon-magnon",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "magnon",
            "label": "Magnon modes",
            "subtitle": "COUPLED RESPONSE",
            "text": "Responds to the phonon packet.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-phonon-magnon",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "field",
            "label": "Applied magnetic field",
            "subtitle": "MODE CONTROL",
            "text": "Tunes magnon response.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-phonon-magnon",
            "locator": "Fig. 2",
            "control": true
          },
          {
            "id": "read",
            "label": "Read laser",
            "subtitle": "KERR PROBE",
            "text": "Measures magnetic dynamics.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-phonon-magnon",
            "locator": "Methods: Optical reading",
            "control": false
          },
          {
            "id": "detect",
            "label": "Balanced photoreceiver",
            "subtitle": "OPTICAL READOUT",
            "text": "Detects polarization rotation.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-phonon-magnon",
            "locator": "Methods: Optical reading",
            "control": false
          },
          {
            "id": "ann",
            "label": "PC ANN / integration",
            "subtitle": "CLASSICAL RECOGNITION",
            "text": "Classifies measured waveforms.",
            "x": 30,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-phonon-magnon",
            "locator": "Results",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "shape",
            "to": "write",
            "type": "control",
            "locator": "Methods: Sequential drawing",
            "label": "",
            "source": "alt-phonon-magnon"
          },
          {
            "from": "write",
            "to": "grating",
            "type": "control",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-phonon-magnon"
          },
          {
            "from": "grating",
            "to": "wave",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-phonon-magnon"
          },
          {
            "from": "wave",
            "to": "magnon",
            "type": "association",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-phonon-magnon"
          },
          {
            "from": "field",
            "to": "magnon",
            "type": "control",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-phonon-magnon"
          },
          {
            "from": "magnon",
            "to": "read",
            "type": "data",
            "locator": "Methods: Optical reading",
            "label": "",
            "source": "alt-phonon-magnon"
          },
          {
            "from": "read",
            "to": "detect",
            "type": "data",
            "locator": "Methods: Optical reading",
            "label": "",
            "source": "alt-phonon-magnon"
          },
          {
            "from": "detect",
            "to": "ann",
            "type": "data",
            "locator": "Results",
            "label": "",
            "source": "alt-phonon-magnon"
          },
          {
            "from": "shape",
            "to": "ann",
            "type": "association",
            "locator": "Results",
            "label": "trajectory integration",
            "source": "alt-phonon-magnon"
          },
          {
            "from": "write",
            "to": "read",
            "type": "control",
            "locator": "Methods: Optical reading",
            "label": "ASOPS timing",
            "source": "alt-phonon-magnon"
          }
        ]
      },
      "originalCandidate": "Acoustic reservoir experiments"
    },
    {
      "id": "queue-129",
      "name": "Steinbock printed chemical-wave OR gate",
      "organization": "West Virginia University",
      "year": 1996,
      "yearLabel": "1996 chemical-gate experiment",
      "kind": "Reaction–diffusion logic experiment",
      "status": "dossier",
      "track": "analog",
      "trackName": "Analog, hybrid & physical dynamics",
      "discoveryParadigms": [
        "analog",
        "unconventional"
      ],
      "paradigms": [
        "molecular",
        "analog",
        "unconventional"
      ],
      "architectures": [
        "cellular-arch"
      ],
      "substrates": [
        "molecular-material"
      ],
      "models": [
        "chemical",
        "continuous",
        "logic"
      ],
      "aliases": [],
      "sources": [
        "alt-chemical-wave-gates"
      ],
      "summary": "A catalyst pattern routes chemical waves so output arrival synchrony encodes a three-input OR result.",
      "config": "Experimentally demonstrated OR(x,y,z) gate in Fig. 1, using printed bathoferroin membrane on BZ-containing agarose.",
      "gaps": [
        "The finite-lived chemical medium ages; it is not indefinite nonvolatile program memory.",
        "A demonstrated gate does not establish that the separately simulated cascaded circuit was physically built."
      ],
      "insight": "Why does this gate encode output using timing rather than simply wave presence?",
      "fields": {
        "state": {
          "value": "Propagating excitation waves",
          "locator": "Fig. 1",
          "source": "alt-chemical-wave-gates"
        },
        "compute": {
          "value": "Geometry-constrained wave propagation",
          "locator": "Experimental Results",
          "source": "alt-chemical-wave-gates"
        },
        "memory": {
          "value": "Transient excitation / refractory state",
          "locator": "Main text",
          "source": "alt-chemical-wave-gates"
        },
        "control": {
          "value": "Printed geometry and synchronized silver-wire initiation",
          "locator": "Experimental Procedures",
          "source": "alt-chemical-wave-gates"
        },
        "io": {
          "value": "CCD reflected-light gray-level measurement",
          "locator": "Experimental Procedures",
          "source": "alt-chemical-wave-gates"
        },
        "software": {
          "value": "Gate geometry and timing convention",
          "locator": "Fig. 1",
          "source": "alt-chemical-wave-gates"
        },
        "workload": {
          "value": "Three-input Boolean OR demonstration",
          "locator": "Fig. 1",
          "source": "alt-chemical-wave-gates"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Four initiation channels and a timing-coded output",
        "scope": "Physical OR experiment; the paper’s later simulated serial gate constructions are separate.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "pattern",
            "label": "Printed catalyst geometry",
            "subtitle": "FIXED PROGRAM",
            "text": "Constrains wave paths.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-chemical-wave-gates",
            "locator": "Experimental Procedures",
            "control": false
          },
          {
            "id": "reagents",
            "label": "BZ agarose / membrane",
            "subtitle": "EXCITABLE MEDIUM",
            "text": "Supports reaction–diffusion.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-chemical-wave-gates",
            "locator": "Experimental Procedures",
            "control": false
          },
          {
            "id": "clock",
            "label": "Clock initiation",
            "subtitle": "INPUT 1",
            "text": "Establishes the zero-input case.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-chemical-wave-gates",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "input",
            "label": "x, y, z initiation",
            "subtitle": "BOOLEAN INPUTS",
            "text": "Launches selected input waves.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-chemical-wave-gates",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "network",
            "label": "Chemical-wave paths",
            "subtitle": "PHYSICAL COMPUTE",
            "text": "Converts inputs to travel timing.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-chemical-wave-gates",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "outa",
            "label": "Output channel A",
            "subtitle": "WAVE ARRIVAL",
            "text": "First timing observation.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-chemical-wave-gates",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "outb",
            "label": "Output channel B",
            "subtitle": "WAVE ARRIVAL",
            "text": "Second timing observation.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-chemical-wave-gates",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "camera",
            "label": "CCD / gray-level trace",
            "subtitle": "CLASSICAL READOUT",
            "text": "Measures both output regions.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-chemical-wave-gates",
            "locator": "Experimental Procedures",
            "control": false
          },
          {
            "id": "decision",
            "label": "Synchrony decision",
            "subtitle": "OR RESULT",
            "text": "Single peak true; double false.",
            "x": 30,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-chemical-wave-gates",
            "locator": "Fig. 1b",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "pattern",
            "to": "network",
            "type": "control",
            "locator": "Experimental Procedures",
            "label": "",
            "source": "alt-chemical-wave-gates"
          },
          {
            "from": "reagents",
            "to": "network",
            "type": "association",
            "locator": "Experimental Procedures",
            "label": "",
            "source": "alt-chemical-wave-gates"
          },
          {
            "from": "clock",
            "to": "network",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-chemical-wave-gates"
          },
          {
            "from": "input",
            "to": "network",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-chemical-wave-gates"
          },
          {
            "from": "network",
            "to": "outa",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-chemical-wave-gates"
          },
          {
            "from": "network",
            "to": "outb",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-chemical-wave-gates"
          },
          {
            "from": "outa",
            "to": "camera",
            "type": "data",
            "locator": "Experimental Results",
            "label": "",
            "source": "alt-chemical-wave-gates"
          },
          {
            "from": "outb",
            "to": "camera",
            "type": "data",
            "locator": "Experimental Results",
            "label": "",
            "source": "alt-chemical-wave-gates"
          },
          {
            "from": "camera",
            "to": "decision",
            "type": "data",
            "locator": "Fig. 1b",
            "label": "",
            "source": "alt-chemical-wave-gates"
          },
          {
            "from": "clock",
            "to": "decision",
            "type": "association",
            "locator": "Fig. 1",
            "label": "timing convention",
            "source": "alt-chemical-wave-gates"
          }
        ]
      },
      "originalCandidate": "Reaction–diffusion processors"
    },
    {
      "id": "queue-130",
      "name": "IBM TrueNorth",
      "organization": "IBM Research",
      "year": 2014,
      "yearLabel": "2014 chip paper",
      "kind": "Research processor",
      "status": "dossier",
      "track": "neural",
      "trackName": "Neuromorphic & reservoirs",
      "discoveryParadigms": [
        "neuromorphic"
      ],
      "paradigms": [
        "digital",
        "neuromorphic",
        "parallel"
      ],
      "architectures": [
        "spiking"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural"
      ],
      "aliases": [],
      "sources": [
        "alt-truenorth"
      ],
      "summary": "Digital spiking cores combine local state, delayed events, and a mesh extended across chip boundaries.",
      "config": "The 4,096-core TrueNorth chip in Merolla et al. (2014), not a later multi-board system.",
      "gaps": [
        "No on-chip synaptic learning is asserted.",
        "Routing graph aggregates individual hops; memory bit counts and power depend on the cited configuration."
      ],
      "insight": "How does local fan-out reduce long-range spike traffic?",
      "fields": {
        "state": {
          "value": "Spikes and discrete neuron state",
          "locator": "Fig. 2G–J",
          "source": "alt-truenorth"
        },
        "compute": {
          "value": "4,096 neurosynaptic cores",
          "locator": "p. 670",
          "source": "alt-truenorth"
        },
        "memory": {
          "value": "Local synapse, neuron, destination, and delay storage",
          "locator": "p. 670",
          "source": "alt-truenorth"
        },
        "control": {
          "value": "Event-driven controller; time-step synchronization",
          "locator": "Fig. 2J",
          "source": "alt-truenorth"
        },
        "io": {
          "value": "2D mesh and peripheral merge/split links",
          "locator": "Fig. 2H–I",
          "source": "alt-truenorth"
        },
        "software": {
          "value": "Offline mapping and software model",
          "locator": "p. 671",
          "source": "alt-truenorth"
        },
        "workload": {
          "value": "Spiking-network inference",
          "locator": "pp. 671–672",
          "source": "alt-truenorth"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Within a core, then across the mesh",
        "scope": "Functional interpretation of Fig. 2; one representative core. Synapses are configurable, nonplastic during inference.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "router",
            "label": "Mesh router",
            "subtitle": "PACKETS",
            "text": "Relays destination-addressed events.",
            "x": 320,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-truenorth",
            "locator": "Fig. 2H",
            "control": false
          },
          {
            "id": "scheduler",
            "label": "Spike scheduler",
            "subtitle": "AXONAL DELAY",
            "text": "Buffers events until their scheduled step.",
            "x": 320,
            "y": 180,
            "w": 160,
            "h": 62,
            "source": "alt-truenorth",
            "locator": "Fig. 2J",
            "control": false
          },
          {
            "id": "crossbar",
            "label": "Synaptic crossbar",
            "subtitle": "CONFIGURABLE LINKS",
            "text": "Fans axon events to neuron inputs.",
            "x": 550,
            "y": 180,
            "w": 160,
            "h": 62,
            "source": "alt-truenorth",
            "locator": "Fig. 2G",
            "control": false
          },
          {
            "id": "neuron",
            "label": "Neuron circuit",
            "subtitle": "TIME MULTIPLEXED",
            "text": "Updates membrane state and emits spikes.",
            "x": 550,
            "y": 335,
            "w": 160,
            "h": 62,
            "source": "alt-truenorth",
            "locator": "Fig. 2J",
            "control": false
          },
          {
            "id": "state",
            "label": "Local memory",
            "subtitle": "STATE + PARAMETERS",
            "text": "Stores core state and destinations.",
            "x": 95,
            "y": 335,
            "w": 160,
            "h": 62,
            "source": "alt-truenorth",
            "locator": "Fig. 2J",
            "control": false
          },
          {
            "id": "controller",
            "label": "Core controller",
            "subtitle": "EVENT SEQUENCING",
            "text": "Orchestrates core operations.",
            "x": 95,
            "y": 180,
            "w": 160,
            "h": 62,
            "source": "alt-truenorth",
            "locator": "Fig. 2J",
            "control": true
          },
          {
            "id": "mesh",
            "label": "Other core routers",
            "subtitle": "64 × 64 ARRAY",
            "text": "Routes across the chip.",
            "x": 550,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-truenorth",
            "locator": "Fig. 2H",
            "control": false
          },
          {
            "id": "link",
            "label": "Merge / split",
            "subtitle": "CHIP BOUNDARY",
            "text": "Serializes peripheral event traffic.",
            "x": 765,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-truenorth",
            "locator": "Fig. 2I",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "router",
            "to": "scheduler",
            "type": "data",
            "locator": "Fig. 2H–J",
            "label": "incoming spike",
            "source": "alt-truenorth"
          },
          {
            "from": "scheduler",
            "to": "crossbar",
            "type": "data",
            "locator": "Fig. 2G–J",
            "label": "axon activation",
            "source": "alt-truenorth"
          },
          {
            "from": "crossbar",
            "to": "neuron",
            "type": "data",
            "locator": "Fig. 2G",
            "label": "synaptic input",
            "source": "alt-truenorth"
          },
          {
            "from": "state",
            "to": "neuron",
            "type": "data",
            "locator": "Fig. 2J",
            "label": "state",
            "source": "alt-truenorth"
          },
          {
            "from": "neuron",
            "to": "state",
            "type": "data",
            "locator": "Fig. 2J",
            "label": "updated state",
            "source": "alt-truenorth"
          },
          {
            "from": "neuron",
            "to": "router",
            "type": "data",
            "locator": "p. 670",
            "label": "outgoing spike",
            "source": "alt-truenorth"
          },
          {
            "from": "controller",
            "to": "scheduler",
            "type": "control",
            "locator": "Fig. 2J",
            "label": "",
            "source": "alt-truenorth"
          },
          {
            "from": "controller",
            "to": "neuron",
            "type": "control",
            "locator": "Fig. 2J",
            "label": "",
            "source": "alt-truenorth"
          },
          {
            "from": "router",
            "to": "mesh",
            "type": "data",
            "locator": "Fig. 2H",
            "label": "",
            "source": "alt-truenorth"
          },
          {
            "from": "mesh",
            "to": "link",
            "type": "data",
            "locator": "Fig. 2I",
            "label": "",
            "source": "alt-truenorth"
          }
        ]
      },
      "originalCandidate": "IBM TrueNorth"
    },
    {
      "id": "queue-131",
      "name": "IBM NorthPole",
      "organization": "IBM Research",
      "year": 2023,
      "yearLabel": "2023 research prototype",
      "kind": "Research processor",
      "status": "dossier",
      "track": "neural",
      "trackName": "Neuromorphic & reservoirs",
      "discoveryParadigms": [
        "neuromorphic"
      ],
      "paradigms": [
        "digital",
        "neuromorphic",
        "dataflow",
        "parallel"
      ],
      "architectures": [
        "near-memory",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural"
      ],
      "aliases": [],
      "sources": [
        "alt-northpole",
        "alt-northpole-paper"
      ],
      "summary": "A spatial inference processor keeps model memory on-chip and presents an active-memory interface to the host.",
      "config": "The 256-core 12 nm prototype described by IBM in 2023; not a training accelerator.",
      "gaps": [
        "No transistor-level bank or NoC topology is inferred from the institutional overview.",
        "The scale-out block is an architectural option, not evidence that a specific multi-chip deployment was benchmarked."
      ],
      "insight": "What model partitioning is necessary when weights must fit locally?",
      "fields": {
        "state": {
          "value": "Low-precision neural activations and weights",
          "locator": "Architecture paragraphs",
          "source": "alt-northpole"
        },
        "compute": {
          "value": "256 cores; 8-, 4-, or 2-bit operation modes",
          "locator": "Architecture paragraphs",
          "source": "alt-northpole"
        },
        "memory": {
          "value": "Distributed on-chip model storage",
          "locator": "Memory constraint paragraphs",
          "source": "alt-northpole"
        },
        "control": {
          "value": "Co-optimized spatial programming model",
          "locator": "Abstract",
          "source": "alt-northpole-paper"
        },
        "io": {
          "value": "PCIe-card prototype; active-memory view",
          "locator": "PCIe photograph and interface paragraph",
          "source": "alt-northpole"
        },
        "software": {
          "value": "Pre-mapped neural inference",
          "locator": "Abstract",
          "source": "alt-northpole-paper"
        },
        "workload": {
          "value": "Vision inference; other models explored",
          "locator": "Applications section",
          "source": "alt-northpole"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Inference bounded by local model memory",
        "scope": "A system-level diagram using published interface and partitioning descriptions. Internal router geometry and bank wiring remain unspecified.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "host",
            "label": "Host machine",
            "subtitle": "SYSTEM BOUNDARY",
            "text": "Supplies an inference workload.",
            "x": 40,
            "y": 200,
            "w": 160,
            "h": 62,
            "source": "alt-northpole",
            "locator": "Active-memory interface paragraph",
            "control": false
          },
          {
            "id": "card",
            "label": "PCIe card",
            "subtitle": "PROTOTYPE",
            "text": "Hosts the NorthPole processor.",
            "x": 250,
            "y": 200,
            "w": 160,
            "h": 62,
            "source": "alt-northpole",
            "locator": "PCIe card photograph",
            "control": false
          },
          {
            "id": "input",
            "label": "Input activations",
            "subtitle": "INFERENCE INPUT",
            "text": "Enter the mapped network.",
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            "y": 45,
            "w": 160,
            "h": 62,
            "source": "alt-northpole",
            "locator": "Inference discussion",
            "control": false
          },
          {
            "id": "cores",
            "label": "Core array",
            "subtitle": "256 CORES",
            "text": "Computes low-precision network layers.",
            "x": 465,
            "y": 200,
            "w": 160,
            "h": 62,
            "source": "alt-northpole",
            "locator": "Architecture paragraphs",
            "control": false
          },
          {
            "id": "weights",
            "label": "On-chip memory",
            "subtitle": "MODEL PARTITION",
            "text": "Keeps weights near computation.",
            "x": 685,
            "y": 200,
            "w": 160,
            "h": 62,
            "source": "alt-northpole",
            "locator": "Memory constraint paragraphs",
            "control": false
          },
          {
            "id": "output",
            "label": "Output activations",
            "subtitle": "RESULTS",
            "text": "Return inference results.",
            "x": 465,
            "y": 360,
            "w": 160,
            "h": 62,
            "source": "alt-northpole",
            "locator": "Inference discussion",
            "control": false
          },
          {
            "id": "partition",
            "label": "Scale-out partition",
            "subtitle": "OPTIONAL SYSTEM",
            "text": "Splits larger models among chips.",
            "x": 685,
            "y": 360,
            "w": 160,
            "h": 62,
            "source": "alt-northpole",
            "locator": "Scale-out paragraph",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "card",
            "type": "association",
            "locator": "PCIe card photograph",
            "label": "",
            "source": "alt-northpole"
          },
          {
            "from": "card",
            "to": "cores",
            "type": "association",
            "locator": "PCIe card photograph",
            "label": "",
            "source": "alt-northpole"
          },
          {
            "from": "input",
            "to": "cores",
            "type": "data",
            "locator": "Inference discussion",
            "label": "",
            "source": "alt-northpole"
          },
          {
            "from": "weights",
            "to": "cores",
            "type": "data",
            "locator": "Memory discussion",
            "label": "",
            "source": "alt-northpole"
          },
          {
            "from": "cores",
            "to": "weights",
            "type": "association",
            "locator": "Memory discussion",
            "label": "local storage",
            "source": "alt-northpole"
          },
          {
            "from": "cores",
            "to": "output",
            "type": "data",
            "locator": "Inference discussion",
            "label": "",
            "source": "alt-northpole"
          },
          {
            "from": "output",
            "to": "host",
            "type": "data",
            "locator": "Active-memory interface paragraph",
            "label": "",
            "source": "alt-northpole"
          },
          {
            "from": "partition",
            "to": "weights",
            "type": "association",
            "locator": "Scale-out paragraph",
            "label": "fit sub-network",
            "source": "alt-northpole"
          },
          {
            "from": "partition",
            "to": "cores",
            "type": "association",
            "locator": "Scale-out paragraph",
            "label": "",
            "source": "alt-northpole"
          },
          {
            "from": "host",
            "to": "input",
            "type": "data",
            "locator": "Active-memory interface paragraph",
            "label": "",
            "source": "alt-northpole"
          }
        ]
      },
      "originalCandidate": "IBM NorthPole"
    },
    {
      "id": "queue-132",
      "name": "SpiNNaker",
      "organization": "University of Manchester",
      "year": 2018,
      "yearLabel": "2018 hardware/software reference",
      "kind": "Neuromorphic computing platform",
      "status": "dossier",
      "track": "neural",
      "trackName": "Neuromorphic & reservoirs",
      "discoveryParadigms": [
        "neuromorphic"
      ],
      "paradigms": [
        "digital",
        "neuromorphic",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "distributed",
        "spiking"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural",
        "process"
      ],
      "aliases": [],
      "sources": [
        "alt-spinnaker"
      ],
      "summary": "ARM cores simulate neural dynamics in software while packet routing communicates spikes.",
      "config": "First-generation 18-core SpiNNaker chip and sPyNNaker execution model described in 2018; full machine size is configuration-specific.",
      "gaps": [
        "Designed capacity is not an achieved network size for every model.",
        "Router tables and SDRAM contention vary with neural mapping."
      ],
      "insight": "Which neural data belongs in TCM, and which must be streamed?",
      "fields": {
        "state": {
          "value": "Software neuron/synapse state",
          "locator": "§2.1",
          "source": "alt-spinnaker"
        },
        "compute": {
          "value": "18 ARM968 cores per chip",
          "locator": "§2.1; Fig. 1",
          "source": "alt-spinnaker"
        },
        "memory": {
          "value": "32 kB ITCM + 64 kB DTCM per core; 128 MB shared SDRAM",
          "locator": "§2.1",
          "source": "alt-spinnaker"
        },
        "control": {
          "value": "Timer, packet, and DMA callbacks",
          "locator": "§3",
          "source": "alt-spinnaker"
        },
        "io": {
          "value": "Packet communication and chip-level NoC",
          "locator": "§2.1",
          "source": "alt-spinnaker"
        },
        "software": {
          "value": "PyNN → sPyNNaker mapping → ARM binaries",
          "locator": "§3",
          "source": "alt-spinnaker"
        },
        "workload": {
          "value": "Spiking-neural-network simulation",
          "locator": "§2.1",
          "source": "alt-spinnaker"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Software neurons over a packet machine",
        "scope": "One core expanded; SDRAM and routing are shared. Spike and bulk transfers remain distinct.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "host",
            "label": "PyNN / mapper",
            "subtitle": "HOST SOFTWARE",
            "text": "Partitions and loads the network.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker",
            "locator": "§3",
            "control": false
          },
          {
            "id": "arm",
            "label": "ARM968 core",
            "subtitle": "NEURON UPDATE",
            "text": "Runs event callbacks.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker",
            "locator": "§2.1; §3",
            "control": false
          },
          {
            "id": "tcm",
            "label": "Local TCM",
            "subtitle": "CODE + WORKING STATE",
            "text": "Supplies instructions and active state.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "dma",
            "label": "DMA controller",
            "subtitle": "SYNAPTIC BLOCKS",
            "text": "Transfers bulk synaptic data.",
            "x": 245,
            "y": 365,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "sdram",
            "label": "Shared SDRAM",
            "subtitle": "128 MB / CHIP",
            "text": "Holds larger synaptic structures.",
            "x": 465,
            "y": 365,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "noc",
            "label": "System NoC",
            "subtitle": "SHARED RESOURCES",
            "text": "Connects cores and memory controller.",
            "x": 465,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "comm",
            "label": "Communications",
            "subtitle": "PACKET EVENTS",
            "text": "Delivers and injects spike packets.",
            "x": 30,
            "y": 365,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker",
            "locator": "§2.1; §3",
            "control": false
          },
          {
            "id": "router",
            "label": "Packet router",
            "subtitle": "MULTICAST",
            "text": "Forwards spike traffic.",
            "x": 680,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "peers",
            "label": "Other cores / chips",
            "subtitle": "DISTRIBUTED NETWORK",
            "text": "Run other neural populations.",
            "x": 680,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker",
            "locator": "§2.1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "tcm",
            "type": "control",
            "locator": "§3",
            "label": "load program",
            "source": "alt-spinnaker"
          },
          {
            "from": "tcm",
            "to": "arm",
            "type": "data",
            "locator": "§2.1",
            "label": "",
            "source": "alt-spinnaker"
          },
          {
            "from": "arm",
            "to": "tcm",
            "type": "data",
            "locator": "§2.1",
            "label": "",
            "source": "alt-spinnaker"
          },
          {
            "from": "arm",
            "to": "dma",
            "type": "control",
            "locator": "§3",
            "label": "request",
            "source": "alt-spinnaker"
          },
          {
            "from": "sdram",
            "to": "dma",
            "type": "data",
            "locator": "§2.1",
            "label": "",
            "source": "alt-spinnaker"
          },
          {
            "from": "dma",
            "to": "tcm",
            "type": "data",
            "locator": "§2.1",
            "label": "",
            "source": "alt-spinnaker"
          },
          {
            "from": "dma",
            "to": "noc",
            "type": "association",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-spinnaker"
          },
          {
            "from": "noc",
            "to": "sdram",
            "type": "association",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-spinnaker"
          },
          {
            "from": "router",
            "to": "comm",
            "type": "data",
            "locator": "§3",
            "label": "incoming spike",
            "source": "alt-spinnaker"
          },
          {
            "from": "comm",
            "to": "arm",
            "type": "control",
            "locator": "§3",
            "label": "callback",
            "source": "alt-spinnaker"
          },
          {
            "from": "arm",
            "to": "comm",
            "type": "data",
            "locator": "§3",
            "label": "emitted spike",
            "source": "alt-spinnaker"
          },
          {
            "from": "comm",
            "to": "router",
            "type": "data",
            "locator": "§3",
            "label": "",
            "source": "alt-spinnaker"
          },
          {
            "from": "router",
            "to": "peers",
            "type": "data",
            "locator": "§2.1",
            "label": "",
            "source": "alt-spinnaker"
          }
        ]
      },
      "originalCandidate": "SpiNNaker"
    },
    {
      "id": "queue-133",
      "name": "SpiNNaker2",
      "organization": "TU Dresden / University of Manchester / SpiNNcloud",
      "year": 2026,
      "yearLabel": "July 2026 chip paper",
      "kind": "Research many-core processor",
      "status": "dossier",
      "track": "neural",
      "trackName": "Neuromorphic & reservoirs",
      "discoveryParadigms": [
        "neuromorphic"
      ],
      "paradigms": [
        "digital",
        "neuromorphic",
        "parallel"
      ],
      "architectures": [
        "mimd",
        "heterogeneous",
        "spiking"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural",
        "process"
      ],
      "aliases": [],
      "sources": [
        "alt-spinnaker2"
      ],
      "summary": "A GALS many-core chip combines ARM M4F processors, numerical/ML accelerators, and separate data and configuration networks.",
      "config": "152-PE chip in Scholze et al. v1 (2026); usable application PE counts depend on firmware reservations.",
      "gaps": [
        "Hardware PE count differs from firmware-exposed application capacity.",
        "No large-system deployment size or workload speedup is inferred from chip capacity."
      ],
      "insight": "Why separate bulk/event traffic from configuration traffic?",
      "fields": {
        "state": {
          "value": "Software neural state and event packets",
          "locator": "§3.2.1",
          "source": "alt-spinnaker2"
        },
        "compute": {
          "value": "152 ARM M4F processing elements",
          "locator": "§3.1",
          "source": "alt-spinnaker2"
        },
        "memory": {
          "value": "128 kB SRAM per PE; LPDDR4 interface",
          "locator": "§3.2.1; §3.2.5",
          "source": "alt-spinnaker2"
        },
        "control": {
          "value": "Quads; local DVFS; management processor",
          "locator": "§3.2.2; §3.2.6",
          "source": "alt-spinnaker2"
        },
        "io": {
          "value": "Multicast event router and chip links",
          "locator": "§3.2.4–5",
          "source": "alt-spinnaker2"
        },
        "software": {
          "value": "ARM programs and machine-learning acceleration",
          "locator": "§3.2.1; §3.5",
          "source": "alt-spinnaker2"
        },
        "workload": {
          "value": "SNN, DNN, and event-based algorithms",
          "locator": "§4",
          "source": "alt-spinnaker2"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "A PE inside a two-network chip",
        "scope": "Representative PE and Quad; mesh placement and router arbitration omitted.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "arm",
            "label": "ARM M4F",
            "subtitle": "PROGRAM CONTROL",
            "text": "Controls a processing element.",
            "x": 30,
            "y": 50,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker2",
            "locator": "§3.2.1",
            "control": true
          },
          {
            "id": "sram",
            "label": "PE SRAM",
            "subtitle": "128 kB",
            "text": "Stores code and local state.",
            "x": 245,
            "y": 50,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker2",
            "locator": "§3.2.1",
            "control": false
          },
          {
            "id": "mla",
            "label": "ML accelerator",
            "subtitle": "16 × 4 MAC ARRAY",
            "text": "Computes matrix operations.",
            "x": 460,
            "y": 50,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker2",
            "locator": "§3.2.1",
            "control": false
          },
          {
            "id": "num",
            "label": "Numerical units",
            "subtitle": "EXP / LOG / ROUND",
            "text": "Accelerate selected arithmetic.",
            "x": 675,
            "y": 50,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker2",
            "locator": "§3.2.1",
            "control": false
          },
          {
            "id": "dnoc",
            "label": "Data NoC",
            "subtitle": "2D MESH",
            "text": "Moves DMA and spike packets.",
            "x": 245,
            "y": 215,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker2",
            "locator": "§3.2.3",
            "control": false
          },
          {
            "id": "cnoc",
            "label": "Configuration NoC",
            "subtitle": "INDEPENDENT NETWORK",
            "text": "Reaches configuration registers.",
            "x": 30,
            "y": 215,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker2",
            "locator": "§3.2.3",
            "control": false
          },
          {
            "id": "router",
            "label": "Event router",
            "subtitle": "MULTICAST ENGINE",
            "text": "Forwards events to PEs or links.",
            "x": 460,
            "y": 215,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker2",
            "locator": "§3.2.4",
            "control": false
          },
          {
            "id": "links",
            "label": "Chip-to-chip links",
            "subtitle": "SYSTEM EVENTS",
            "text": "Connect neighboring chips.",
            "x": 675,
            "y": 215,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker2",
            "locator": "§3.2.5",
            "control": false
          },
          {
            "id": "dram",
            "label": "LPDDR4",
            "subtitle": "OFF-CHIP MEMORY",
            "text": "Extends chip storage.",
            "x": 245,
            "y": 380,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker2",
            "locator": "§3.2.5",
            "control": false
          },
          {
            "id": "quad",
            "label": "Quad management",
            "subtitle": "4 PEs / QUAD",
            "text": "Controls local clock and power.",
            "x": 30,
            "y": 380,
            "w": 160,
            "h": 62,
            "source": "alt-spinnaker2",
            "locator": "§3.2.2",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "sram",
            "to": "arm",
            "type": "data",
            "locator": "§3.2.1",
            "label": "",
            "source": "alt-spinnaker2"
          },
          {
            "from": "arm",
            "to": "mla",
            "type": "control",
            "locator": "§3.2.1",
            "label": "",
            "source": "alt-spinnaker2"
          },
          {
            "from": "arm",
            "to": "num",
            "type": "control",
            "locator": "§3.2.1",
            "label": "",
            "source": "alt-spinnaker2"
          },
          {
            "from": "sram",
            "to": "mla",
            "type": "data",
            "locator": "§3.2.1",
            "label": "",
            "source": "alt-spinnaker2"
          },
          {
            "from": "mla",
            "to": "dnoc",
            "type": "data",
            "locator": "§3.2.1",
            "label": "",
            "source": "alt-spinnaker2"
          },
          {
            "from": "dnoc",
            "to": "sram",
            "type": "data",
            "locator": "§3.2.3",
            "label": "",
            "source": "alt-spinnaker2"
          },
          {
            "from": "cnoc",
            "to": "dnoc",
            "type": "association",
            "locator": "§3.2.3",
            "label": "bridge",
            "source": "alt-spinnaker2"
          },
          {
            "from": "dnoc",
            "to": "router",
            "type": "data",
            "locator": "§3.2.4",
            "label": "",
            "source": "alt-spinnaker2"
          },
          {
            "from": "router",
            "to": "links",
            "type": "data",
            "locator": "§3.2.5",
            "label": "",
            "source": "alt-spinnaker2"
          },
          {
            "from": "links",
            "to": "router",
            "type": "data",
            "locator": "§3.2.5",
            "label": "",
            "source": "alt-spinnaker2"
          },
          {
            "from": "dnoc",
            "to": "dram",
            "type": "data",
            "locator": "§3.2.5",
            "label": "",
            "source": "alt-spinnaker2"
          },
          {
            "from": "quad",
            "to": "arm",
            "type": "control",
            "locator": "§3.2.2",
            "label": "",
            "source": "alt-spinnaker2"
          }
        ]
      },
      "originalCandidate": "SpiNNaker2"
    },
    {
      "id": "queue-134",
      "name": "BrainScaleS-1 wafer system",
      "organization": "Heidelberg University / FACETS–BrainScaleS",
      "year": 2017,
      "yearLabel": "2017 wafer experiment",
      "kind": "Mixed-signal research system",
      "status": "dossier",
      "track": "neural",
      "trackName": "Neuromorphic & reservoirs",
      "discoveryParadigms": [
        "neuromorphic"
      ],
      "paradigms": [
        "analog",
        "hybrid",
        "neuromorphic",
        "parallel"
      ],
      "architectures": [
        "spiking",
        "wafer-scale",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural",
        "continuous"
      ],
      "aliases": [],
      "sources": [
        "alt-brainscales1"
      ],
      "summary": "Wafer-scale analog neural dynamics are connected by digital spike routing and controlled by a host-side experimental workflow.",
      "config": "The BrainScaleS wafer module and hardware-in-the-loop experiment in Schmitt et al. (2017).",
      "gaps": [
        "Analog mismatch and available routing resources constrain network mapping.",
        "This is not BrainScaleS-2; its embedded plasticity processors are not imported into this record."
      ],
      "insight": "How can measured hardware activity correct an imperfect software model?",
      "fields": {
        "state": {
          "value": "Analog neuron dynamics; digitally configured synapses",
          "locator": "§II-A",
          "source": "alt-brainscales1"
        },
        "compute": {
          "value": "HICANN circuits on a wafer-scale module",
          "locator": "§II-A",
          "source": "alt-brainscales1"
        },
        "memory": {
          "value": "Synaptic weights and calibrated analog parameters",
          "locator": "§II-A–C",
          "source": "alt-brainscales1"
        },
        "control": {
          "value": "Host configuration and experiment scheduling",
          "locator": "§II-B",
          "source": "alt-brainscales1"
        },
        "io": {
          "value": "Digital events through FPGA communication",
          "locator": "§II-A–B",
          "source": "alt-brainscales1"
        },
        "software": {
          "value": "Mapping, calibration, and hardware-in-the-loop updates",
          "locator": "§II-B–C; III-C",
          "source": "alt-brainscales1"
        },
        "workload": {
          "value": "Deep spiking-network training experiment",
          "locator": "§III",
          "source": "alt-brainscales1"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "A measured analog system in a digital training loop",
        "scope": "Module and workflow roles in the 2017 experiment; not a diagram of every wafer routing line.",
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        "height": 490,
        "nodes": [
          {
            "id": "model",
            "label": "Software model",
            "subtitle": "TARGET NETWORK",
            "text": "Defines the intended network.",
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            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales1",
            "locator": "§III-A",
            "control": false
          },
          {
            "id": "mapping",
            "label": "Mapping / calibration",
            "subtitle": "HOST PREPARATION",
            "text": "Compensates hardware variation.",
            "x": 245,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales1",
            "locator": "§II-B–C",
            "control": false
          },
          {
            "id": "fpga",
            "label": "FPGA interface",
            "subtitle": "EVENT EXCHANGE",
            "text": "Schedules and records events.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales1",
            "locator": "§II-B",
            "control": false
          },
          {
            "id": "routing",
            "label": "Wafer event fabric",
            "subtitle": "DIGITAL SPIKES",
            "text": "Connects neural populations.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales1",
            "locator": "§II-A",
            "control": false
          },
          {
            "id": "synapse",
            "label": "Synapse arrays",
            "subtitle": "CONFIGURED WEIGHTS",
            "text": "Drive analog neurons.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales1",
            "locator": "§II-A",
            "control": false
          },
          {
            "id": "neuron",
            "label": "Analog neurons",
            "subtitle": "PHYSICAL DYNAMICS",
            "text": "Evolve faster than biological time.",
            "x": 675,
            "y": 365,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales1",
            "locator": "§II-A",
            "control": false
          },
          {
            "id": "measure",
            "label": "Recorded activity",
            "subtitle": "EXPERIMENT RESULTS",
            "text": "Returns measured neural responses.",
            "x": 460,
            "y": 365,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales1",
            "locator": "§III-C",
            "control": false
          },
          {
            "id": "update",
            "label": "Gradient update",
            "subtitle": "HOST LEARNING",
            "text": "Updates parameters using measured activity.",
            "x": 30,
            "y": 365,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales1",
            "locator": "§III-C",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "model",
            "to": "mapping",
            "type": "control",
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            "label": "",
            "source": "alt-brainscales1"
          },
          {
            "from": "mapping",
            "to": "synapse",
            "type": "control",
            "locator": "§II-B–C",
            "label": "",
            "source": "alt-brainscales1"
          },
          {
            "from": "mapping",
            "to": "fpga",
            "type": "control",
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            "label": "",
            "source": "alt-brainscales1"
          },
          {
            "from": "fpga",
            "to": "routing",
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            "label": "",
            "source": "alt-brainscales1"
          },
          {
            "from": "routing",
            "to": "synapse",
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            "label": "",
            "source": "alt-brainscales1"
          },
          {
            "from": "synapse",
            "to": "neuron",
            "type": "data",
            "locator": "§II-A",
            "label": "",
            "source": "alt-brainscales1"
          },
          {
            "from": "neuron",
            "to": "routing",
            "type": "data",
            "locator": "§II-A",
            "label": "",
            "source": "alt-brainscales1"
          },
          {
            "from": "routing",
            "to": "measure",
            "type": "data",
            "locator": "§III-C",
            "label": "",
            "source": "alt-brainscales1"
          },
          {
            "from": "measure",
            "to": "update",
            "type": "data",
            "locator": "§III-C",
            "label": "",
            "source": "alt-brainscales1"
          },
          {
            "from": "model",
            "to": "update",
            "type": "association",
            "locator": "§III-C",
            "label": "",
            "source": "alt-brainscales1"
          },
          {
            "from": "update",
            "to": "mapping",
            "type": "control",
            "locator": "§III-C",
            "label": "",
            "source": "alt-brainscales1"
          }
        ]
      },
      "originalCandidate": "BrainScaleS-1"
    },
    {
      "id": "queue-135",
      "name": "BrainScaleS-2",
      "organization": "Heidelberg University",
      "year": 2022,
      "yearLabel": "2022 full-scale single-core system",
      "kind": "Mixed-signal neuromorphic system",
      "status": "dossier",
      "track": "neural",
      "trackName": "Neuromorphic & reservoirs",
      "discoveryParadigms": [
        "neuromorphic"
      ],
      "paradigms": [
        "analog",
        "digital",
        "hybrid",
        "neuromorphic"
      ],
      "architectures": [
        "spiking",
        "in-memory",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural",
        "continuous"
      ],
      "aliases": [],
      "sources": [
        "alt-brainscales2"
      ],
      "summary": "Analog neuron/synapse dynamics interact with on-chip digital plasticity processors and parallel analog readout.",
      "config": "Single-core BrainScaleS-2 architecture commissioned and described by Pehle et al. (2022).",
      "gaps": [
        "Analog acceleration is a physical timescale ratio, not an end-to-end speedup for arbitrary applications.",
        "Individual parameter, ADC, and synaptic resource choices depend on the experiment."
      ],
      "insight": "How does parallel observation make local learning programmable?",
      "fields": {
        "state": {
          "value": "Analog membrane/correlation traces and digital weights",
          "locator": "§II.1",
          "source": "alt-brainscales2"
        },
        "compute": {
          "value": "512 neuron circuits; four synaptic quadrants",
          "locator": "§II.1",
          "source": "alt-brainscales2"
        },
        "memory": {
          "value": "Local synaptic SRAM and analog parameter storage",
          "locator": "§II.1",
          "source": "alt-brainscales2"
        },
        "control": {
          "value": "Two programmable digital plasticity processors",
          "locator": "§II.3",
          "source": "alt-brainscales2"
        },
        "io": {
          "value": "Event router, custom link, external FPGA",
          "locator": "§II.1",
          "source": "alt-brainscales2"
        },
        "software": {
          "value": "Experiment configuration and plasticity programs",
          "locator": "§II.3",
          "source": "alt-brainscales2"
        },
        "workload": {
          "value": "Neural dynamics and learning experiments",
          "locator": "§III",
          "source": "alt-brainscales2"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Analog dynamics meet programmable plasticity",
        "scope": "Selected paths in the single-core architecture. Analog traces and event traffic are distinct channels.",
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        "height": 490,
        "nodes": [
          {
            "id": "fpga",
            "label": "FPGA controller",
            "subtitle": "EXTERNAL SYSTEM",
            "text": "Buffers stimulus and output data.",
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            "y": 45,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales2",
            "locator": "§II.1",
            "control": false
          },
          {
            "id": "event",
            "label": "Event router",
            "subtitle": "SPIKE PACKETS",
            "text": "Routes external and internal events.",
            "x": 245,
            "y": 45,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales2",
            "locator": "§II.1",
            "control": false
          },
          {
            "id": "synapse",
            "label": "Synapse arrays",
            "subtitle": "WEIGHTED INPUT",
            "text": "Convert spikes into analog currents.",
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            "y": 45,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales2",
            "locator": "§II.1",
            "control": false
          },
          {
            "id": "neuron",
            "label": "Neuron circuits",
            "subtitle": "512 CIRCUITS",
            "text": "Evolve physical neural state.",
            "x": 675,
            "y": 45,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales2",
            "locator": "§II.2",
            "control": false
          },
          {
            "id": "weight",
            "label": "Synaptic SRAM",
            "subtitle": "DIGITAL WEIGHTS",
            "text": "Stores configurable efficacies.",
            "x": 460,
            "y": 210,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales2",
            "locator": "§II.1",
            "control": false
          },
          {
            "id": "sensor",
            "label": "Correlation sensors",
            "subtitle": "ANALOG TRACES",
            "text": "Measure local spike correlations.",
            "x": 675,
            "y": 210,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales2",
            "locator": "§II.3",
            "control": false
          },
          {
            "id": "cadc",
            "label": "Column ADCs",
            "subtitle": "PARALLEL OBSERVATION",
            "text": "Digitize traces for learning.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales2",
            "locator": "§II.3",
            "control": false
          },
          {
            "id": "ppu",
            "label": "Plasticity processors",
            "subtitle": "SIMD EXTENSIONS",
            "text": "Compute and apply parameter updates.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales2",
            "locator": "§II.3",
            "control": true
          },
          {
            "id": "params",
            "label": "Analog parameters",
            "subtitle": "LOCAL CONFIGURATION",
            "text": "Tune neuron and synapse behavior.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-brainscales2",
            "locator": "§II.1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "fpga",
            "to": "event",
            "type": "data",
            "locator": "§II.1",
            "label": "",
            "source": "alt-brainscales2"
          },
          {
            "from": "event",
            "to": "synapse",
            "type": "data",
            "locator": "§II.1",
            "label": "",
            "source": "alt-brainscales2"
          },
          {
            "from": "weight",
            "to": "synapse",
            "type": "data",
            "locator": "§II.1",
            "label": "",
            "source": "alt-brainscales2"
          },
          {
            "from": "synapse",
            "to": "neuron",
            "type": "data",
            "locator": "§II.2",
            "label": "",
            "source": "alt-brainscales2"
          },
          {
            "from": "neuron",
            "to": "event",
            "type": "data",
            "locator": "§II.1",
            "label": "",
            "source": "alt-brainscales2"
          },
          {
            "from": "neuron",
            "to": "sensor",
            "type": "association",
            "locator": "§II.3",
            "label": "",
            "source": "alt-brainscales2"
          },
          {
            "from": "sensor",
            "to": "cadc",
            "type": "data",
            "locator": "§II.3",
            "label": "",
            "source": "alt-brainscales2"
          },
          {
            "from": "cadc",
            "to": "ppu",
            "type": "data",
            "locator": "§II.3",
            "label": "",
            "source": "alt-brainscales2"
          },
          {
            "from": "ppu",
            "to": "weight",
            "type": "control",
            "locator": "§II.3",
            "label": "",
            "source": "alt-brainscales2"
          },
          {
            "from": "ppu",
            "to": "params",
            "type": "control",
            "locator": "§II.3",
            "label": "",
            "source": "alt-brainscales2"
          },
          {
            "from": "params",
            "to": "neuron",
            "type": "control",
            "locator": "§II.1",
            "label": "",
            "source": "alt-brainscales2"
          },
          {
            "from": "fpga",
            "to": "ppu",
            "type": "association",
            "locator": "§II.1",
            "label": "",
            "source": "alt-brainscales2"
          }
        ]
      },
      "originalCandidate": "BrainScaleS-2"
    },
    {
      "id": "queue-136",
      "name": "Neurogrid",
      "organization": "Stanford University",
      "year": 2014,
      "yearLabel": "2014 multichip system paper",
      "kind": "Mixed-signal research system",
      "status": "dossier",
      "track": "neural",
      "trackName": "Neuromorphic & reservoirs",
      "discoveryParadigms": [
        "neuromorphic"
      ],
      "paradigms": [
        "analog",
        "digital",
        "hybrid",
        "neuromorphic"
      ],
      "architectures": [
        "spiking",
        "distributed"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural",
        "continuous"
      ],
      "aliases": [],
      "sources": [
        "alt-neurogrid"
      ],
      "summary": "Analog neural arrays use digital event communication through a multicast binary-tree network.",
      "config": "Sixteen-Neurocore board described in Benjamin et al. (2014); neuron capacity and connection counts are model-dependent.",
      "gaps": [
        "Shared synapse/dendrite circuits constrain how arbitrary graphs map to the hardware.",
        "No per-edge biological synapse storage is inferred from the paper’s aggregate connection count."
      ],
      "insight": "What connectivity can be shared rather than represented by a separate synapse circuit?",
      "fields": {
        "state": {
          "value": "Analog soma/dendrite dynamics and event addresses",
          "locator": "§IV",
          "source": "alt-neurogrid"
        },
        "compute": {
          "value": "16 Neurocores, each with a 256 × 256 neuron array",
          "locator": "§III",
          "source": "alt-neurogrid"
        },
        "memory": {
          "value": "Routing and bias RAMs; daughterboard SRAM",
          "locator": "§III",
          "source": "alt-neurogrid"
        },
        "control": {
          "value": "Host HAL, driver, and board control",
          "locator": "Fig. 4",
          "source": "alt-neurogrid"
        },
        "io": {
          "value": "USB; binary-tree packet network",
          "locator": "§III; V",
          "source": "alt-neurogrid"
        },
        "software": {
          "value": "NGPython / GUI → HAL → driver",
          "locator": "Fig. 4",
          "source": "alt-neurogrid"
        },
        "workload": {
          "value": "Real-time neural simulation",
          "locator": "§III",
          "source": "alt-neurogrid"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Host mapping, multicast tree, analog populations",
        "scope": "One representative Neurocore is expanded. Daughterboard branching and on-chip analog computation are different stages.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "host",
            "label": "NGPython / GUI",
            "subtitle": "HOST MODEL",
            "text": "Defines and visualizes networks.",
            "x": 30,
            "y": 30,
            "w": 160,
            "h": 62,
            "source": "alt-neurogrid",
            "locator": "Fig. 4",
            "control": false
          },
          {
            "id": "hal",
            "label": "HAL + driver",
            "subtitle": "MAPPING",
            "text": "Programs models and connectivity.",
            "x": 245,
            "y": 30,
            "w": 160,
            "h": 62,
            "source": "alt-neurogrid",
            "locator": "Fig. 4",
            "control": false
          },
          {
            "id": "usb",
            "label": "USB / CPLD",
            "subtitle": "BOARD INTERFACE",
            "text": "Converts host and Neurogrid packets.",
            "x": 460,
            "y": 30,
            "w": 160,
            "h": 62,
            "source": "alt-neurogrid",
            "locator": "Fig. 4",
            "control": false
          },
          {
            "id": "branch",
            "label": "FPGA + SRAM",
            "subtitle": "AXON BRANCHING",
            "text": "Implements primary branching.",
            "x": 675,
            "y": 30,
            "w": 160,
            "h": 62,
            "source": "alt-neurogrid",
            "locator": "§III; Fig. 4",
            "control": false
          },
          {
            "id": "tree",
            "label": "Binary-tree router",
            "subtitle": "MULTICAST",
            "text": "Moves packets among Neurocores.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-neurogrid",
            "locator": "§V",
            "control": false
          },
          {
            "id": "receiver",
            "label": "Event receiver",
            "subtitle": "LOCAL DELIVERY",
            "text": "Delivers spikes to the array.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-neurogrid",
            "locator": "Fig. 4",
            "control": false
          },
          {
            "id": "analog",
            "label": "Neuron array",
            "subtitle": "SOMA / DENDRITE",
            "text": "Evolves analog neural dynamics.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-neurogrid",
            "locator": "§IV",
            "control": false
          },
          {
            "id": "tx",
            "label": "Event transmitter",
            "subtitle": "SPIKE ENCODING",
            "text": "Dispatches array spikes.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-neurogrid",
            "locator": "Fig. 4",
            "control": false
          },
          {
            "id": "ram",
            "label": "Bias / routing RAM",
            "subtitle": "CONFIGURATION",
            "text": "Configures connectivity and biases.",
            "x": 245,
            "y": 380,
            "w": 160,
            "h": 62,
            "source": "alt-neurogrid",
            "locator": "§III",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "hal",
            "type": "control",
            "locator": "Fig. 4",
            "label": "",
            "source": "alt-neurogrid"
          },
          {
            "from": "hal",
            "to": "usb",
            "type": "control",
            "locator": "Fig. 4",
            "label": "",
            "source": "alt-neurogrid"
          },
          {
            "from": "usb",
            "to": "branch",
            "type": "data",
            "locator": "§III",
            "label": "",
            "source": "alt-neurogrid"
          },
          {
            "from": "branch",
            "to": "tree",
            "type": "data",
            "locator": "§III; V",
            "label": "",
            "source": "alt-neurogrid"
          },
          {
            "from": "tree",
            "to": "receiver",
            "type": "data",
            "locator": "Fig. 4",
            "label": "",
            "source": "alt-neurogrid"
          },
          {
            "from": "receiver",
            "to": "analog",
            "type": "data",
            "locator": "Fig. 4",
            "label": "",
            "source": "alt-neurogrid"
          },
          {
            "from": "analog",
            "to": "tx",
            "type": "data",
            "locator": "Fig. 4",
            "label": "",
            "source": "alt-neurogrid"
          },
          {
            "from": "tx",
            "to": "tree",
            "type": "data",
            "locator": "Fig. 4",
            "label": "",
            "source": "alt-neurogrid"
          },
          {
            "from": "tree",
            "to": "usb",
            "type": "data",
            "locator": "Fig. 4",
            "label": "",
            "source": "alt-neurogrid"
          },
          {
            "from": "ram",
            "to": "analog",
            "type": "control",
            "locator": "§III",
            "label": "",
            "source": "alt-neurogrid"
          },
          {
            "from": "ram",
            "to": "tree",
            "type": "control",
            "locator": "§III",
            "label": "",
            "source": "alt-neurogrid"
          }
        ]
      },
      "originalCandidate": "Neurogrid"
    },
    {
      "id": "queue-137",
      "name": "DYNAP-SE / DYNAPs prototype",
      "organization": "University of Zurich / ETH Zurich",
      "year": 2017,
      "yearLabel": "2017 four-core prototype paper",
      "kind": "Mixed-signal research processor",
      "status": "dossier",
      "track": "neural",
      "trackName": "Neuromorphic & reservoirs",
      "discoveryParadigms": [
        "neuromorphic"
      ],
      "paradigms": [
        "analog",
        "digital",
        "hybrid",
        "neuromorphic"
      ],
      "architectures": [
        "spiking"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural",
        "continuous"
      ],
      "aliases": [],
      "sources": [
        "alt-dynapse"
      ],
      "summary": "A four-core mixed-signal processor combines source routing and destination matching with physical synapse/neuron dynamics.",
      "config": "The four-core DYNAPs prototype in Moradi et al. (2017), the architecture underlying first-generation DYNAP-SE; not DYNAP-SE2.",
      "gaps": [
        "A first-generation architecture paper is used as a representative; exact commercial board revision remains to be attached.",
        "Analog mismatch and event-routing limits require per-experiment calibration and mapping."
      ],
      "insight": "Why distribute routing memory between sources and destination neurons?",
      "fields": {
        "state": {
          "value": "Spike addresses and analog neural state",
          "locator": "§I; IV-A",
          "source": "alt-dynapse"
        },
        "compute": {
          "value": "4 cores × 256 analog neurons",
          "locator": "§IV",
          "source": "alt-dynapse"
        },
        "memory": {
          "value": "SRAM source routes and CAM destination tags",
          "locator": "§III; IV-A",
          "source": "alt-dynapse"
        },
        "control": {
          "value": "On-chip bias configuration",
          "locator": "Fig. 8",
          "source": "alt-dynapse"
        },
        "io": {
          "value": "Hierarchical/mesh R1–R3 event routing",
          "locator": "§III-B",
          "source": "alt-dynapse"
        },
        "software": {
          "value": "Network topology and parameter configuration",
          "locator": "§III–V",
          "source": "alt-dynapse"
        },
        "workload": {
          "value": "Event-based neural processing",
          "locator": "§V",
          "source": "alt-dynapse"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "An event traverses routing and mixed-signal synapses",
        "scope": "Representative destination node and routing hierarchy from Figs. 4–9; the graph aggregates repeated local synapse channels.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "r3",
            "label": "R3 router",
            "subtitle": "INTER-CHIP MESH",
            "text": "Selects off-chip destinations.",
            "x": 30,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-dynapse",
            "locator": "§III-B3",
            "control": false
          },
          {
            "id": "r2",
            "label": "R2 router",
            "subtitle": "ON-CHIP HIERARCHY",
            "text": "Connects local core routers.",
            "x": 245,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-dynapse",
            "locator": "§III-B2",
            "control": false
          },
          {
            "id": "r1",
            "label": "R1 + source SRAM",
            "subtitle": "CORE ROUTING",
            "text": "Stores outgoing route entries.",
            "x": 460,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-dynapse",
            "locator": "§III-B1",
            "control": false
          },
          {
            "id": "cam",
            "label": "Destination CAM",
            "subtitle": "TAG MATCH",
            "text": "Recognizes incoming event tags.",
            "x": 675,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-dynapse",
            "locator": "§IV-A; Fig. 9",
            "control": false
          },
          {
            "id": "pulse",
            "label": "Pulse processing",
            "subtitle": "WEIGHT / TYPE",
            "text": "Shapes matched event pulses.",
            "x": 675,
            "y": 210,
            "w": 160,
            "h": 62,
            "source": "alt-dynapse",
            "locator": "Fig. 9",
            "control": false
          },
          {
            "id": "dpi",
            "label": "DPI synapses",
            "subtitle": "ANALOG FILTERS",
            "text": "Convert events into synaptic currents.",
            "x": 460,
            "y": 210,
            "w": 160,
            "h": 62,
            "source": "alt-dynapse",
            "locator": "Fig. 9",
            "control": false
          },
          {
            "id": "neuron",
            "label": "Adaptive I&F",
            "subtitle": "ANALOG DYNAMICS",
            "text": "Integrates currents and generates spikes.",
            "x": 245,
            "y": 210,
            "w": 160,
            "h": 62,
            "source": "alt-dynapse",
            "locator": "Fig. 9",
            "control": false
          },
          {
            "id": "hs",
            "label": "Handshake block",
            "subtitle": "OUTPUT EVENT",
            "text": "Forwards generated events.",
            "x": 30,
            "y": 210,
            "w": 160,
            "h": 62,
            "source": "alt-dynapse",
            "locator": "Fig. 9",
            "control": false
          },
          {
            "id": "bias",
            "label": "Bias generators",
            "subtitle": "CONFIGURATION",
            "text": "Tune neuron and synapse dynamics.",
            "x": 460,
            "y": 380,
            "w": 160,
            "h": 62,
            "source": "alt-dynapse",
            "locator": "Fig. 8",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "r3",
            "to": "r2",
            "type": "data",
            "locator": "§III-B",
            "label": "",
            "source": "alt-dynapse"
          },
          {
            "from": "r2",
            "to": "r1",
            "type": "data",
            "locator": "§III-B",
            "label": "",
            "source": "alt-dynapse"
          },
          {
            "from": "r1",
            "to": "cam",
            "type": "data",
            "locator": "§IV-A",
            "label": "",
            "source": "alt-dynapse"
          },
          {
            "from": "cam",
            "to": "pulse",
            "type": "data",
            "locator": "Fig. 9",
            "label": "",
            "source": "alt-dynapse"
          },
          {
            "from": "pulse",
            "to": "dpi",
            "type": "data",
            "locator": "Fig. 9",
            "label": "",
            "source": "alt-dynapse"
          },
          {
            "from": "dpi",
            "to": "neuron",
            "type": "data",
            "locator": "Fig. 9",
            "label": "",
            "source": "alt-dynapse"
          },
          {
            "from": "neuron",
            "to": "hs",
            "type": "data",
            "locator": "Fig. 9",
            "label": "",
            "source": "alt-dynapse"
          },
          {
            "from": "hs",
            "to": "r1",
            "type": "data",
            "locator": "§III-B1; Fig. 9",
            "label": "",
            "source": "alt-dynapse"
          },
          {
            "from": "r1",
            "to": "r2",
            "type": "data",
            "locator": "§III-B1",
            "label": "",
            "source": "alt-dynapse"
          },
          {
            "from": "r2",
            "to": "r3",
            "type": "data",
            "locator": "§III-B2",
            "label": "",
            "source": "alt-dynapse"
          },
          {
            "from": "bias",
            "to": "dpi",
            "type": "control",
            "locator": "Fig. 8",
            "label": "",
            "source": "alt-dynapse"
          },
          {
            "from": "bias",
            "to": "neuron",
            "type": "control",
            "locator": "Fig. 8",
            "label": "",
            "source": "alt-dynapse"
          }
        ]
      },
      "originalCandidate": "DYNAP-SE"
    },
    {
      "id": "queue-138",
      "name": "Tianjic",
      "organization": "Tsinghua University and collaborators",
      "year": 2019,
      "yearLabel": "2019 chip demonstration",
      "kind": "Research processor",
      "status": "dossier",
      "track": "neural",
      "trackName": "Neuromorphic & reservoirs",
      "discoveryParadigms": [
        "neuromorphic"
      ],
      "paradigms": [
        "digital",
        "neuromorphic",
        "parallel"
      ],
      "architectures": [
        "spiking",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural"
      ],
      "aliases": [],
      "sources": [
        "alt-tianjic"
      ],
      "summary": "Reconfigurable digital functional cores support ANN and SNN encodings on shared arithmetic and routing resources.",
      "config": "Tianjic FCore/chip in Pei et al. (2019); hybrid here means ANN/SNN operation, not analog electronics.",
      "gaps": [
        "Hybrid ANN/SNN coding does not establish artificial general intelligence.",
        "Learning, model mapping, and achieved accuracy remain specific to the reported experiments."
      ],
      "insight": "Which blocks must change when the input and output use different neural codes?",
      "fields": {
        "state": {
          "value": "ANN values or SNN spikes and membrane state",
          "locator": "Fig. 2",
          "source": "alt-tianjic"
        },
        "compute": {
          "value": "Shared dendritic integration engines",
          "locator": "Methods; Extended Data Fig. 1",
          "source": "alt-tianjic"
        },
        "memory": {
          "value": "Local weights, input buffers, and potential memory",
          "locator": "Extended Data Fig. 1",
          "source": "alt-tianjic"
        },
        "control": {
          "value": "Configured axon and soma modes",
          "locator": "Methods",
          "source": "alt-tianjic"
        },
        "io": {
          "value": "Reconfigurable 2D mesh packet routing",
          "locator": "Fig. 2e–f",
          "source": "alt-tianjic"
        },
        "software": {
          "value": "Mapped ANN, SNN, or mixed networks",
          "locator": "Methods",
          "source": "alt-tianjic"
        },
        "workload": {
          "value": "Hybrid neural-network demonstrations",
          "locator": "Main text",
          "source": "alt-tianjic"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "A configurable FCore bridges neural representations",
        "scope": "One functional core and its router. Modes are set before the demonstrated execution; arrows show logical data paths.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "router",
            "label": "Router",
            "subtitle": "UNIFIED PACKETS",
            "text": "Routes ANN values or spike events.",
            "x": 30,
            "y": 200,
            "w": 160,
            "h": 62,
            "source": "alt-tianjic",
            "locator": "Fig. 2f",
            "control": false
          },
          {
            "id": "axon",
            "label": "Axon buffers",
            "subtitle": "INPUT MODE",
            "text": "Parses the configured input code.",
            "x": 245,
            "y": 200,
            "w": 160,
            "h": 62,
            "source": "alt-tianjic",
            "locator": "Extended Data Fig. 1",
            "control": false
          },
          {
            "id": "synapse",
            "label": "Synapse memory",
            "subtitle": "LOCAL WEIGHTS",
            "text": "Keeps weights near arithmetic.",
            "x": 460,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-tianjic",
            "locator": "Extended Data Fig. 1",
            "control": false
          },
          {
            "id": "dendrite",
            "label": "Dendrite",
            "subtitle": "MULTIPLY / ACCUMULATE",
            "text": "Shares integration hardware across modes.",
            "x": 460,
            "y": 200,
            "w": 160,
            "h": 62,
            "source": "alt-tianjic",
            "locator": "Extended Data Fig. 1",
            "control": false
          },
          {
            "id": "potential",
            "label": "Potential memory",
            "subtitle": "TEMPORAL STATE",
            "text": "Retains partial neural state.",
            "x": 460,
            "y": 370,
            "w": 160,
            "h": 62,
            "source": "alt-tianjic",
            "locator": "Extended Data Fig. 1",
            "control": false
          },
          {
            "id": "soma",
            "label": "Soma",
            "subtitle": "ANN / SNN OUTPUT",
            "text": "Applies activation or neural dynamics.",
            "x": 675,
            "y": 200,
            "w": 160,
            "h": 62,
            "source": "alt-tianjic",
            "locator": "Fig. 2d",
            "control": false
          },
          {
            "id": "lut",
            "label": "Activation LUT",
            "subtitle": "ANN FUNCTION",
            "text": "Supplies configurable ANN activation.",
            "x": 675,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-tianjic",
            "locator": "Fig. 2d",
            "control": false
          },
          {
            "id": "controller",
            "label": "FCore configuration",
            "subtitle": "MODE + SEQUENCING",
            "text": "Selects axon and soma behavior.",
            "x": 245,
            "y": 370,
            "w": 160,
            "h": 62,
            "source": "alt-tianjic",
            "locator": "Methods",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "router",
            "to": "axon",
            "type": "data",
            "locator": "Methods",
            "label": "",
            "source": "alt-tianjic"
          },
          {
            "from": "axon",
            "to": "dendrite",
            "type": "data",
            "locator": "Extended Data Fig. 1",
            "label": "",
            "source": "alt-tianjic"
          },
          {
            "from": "synapse",
            "to": "dendrite",
            "type": "data",
            "locator": "Extended Data Fig. 1",
            "label": "",
            "source": "alt-tianjic"
          },
          {
            "from": "dendrite",
            "to": "potential",
            "type": "data",
            "locator": "Extended Data Fig. 1",
            "label": "",
            "source": "alt-tianjic"
          },
          {
            "from": "potential",
            "to": "soma",
            "type": "data",
            "locator": "Extended Data Fig. 1",
            "label": "",
            "source": "alt-tianjic"
          },
          {
            "from": "dendrite",
            "to": "soma",
            "type": "data",
            "locator": "Extended Data Fig. 1",
            "label": "",
            "source": "alt-tianjic"
          },
          {
            "from": "lut",
            "to": "soma",
            "type": "data",
            "locator": "Fig. 2d",
            "label": "",
            "source": "alt-tianjic"
          },
          {
            "from": "soma",
            "to": "router",
            "type": "data",
            "locator": "Methods",
            "label": "",
            "source": "alt-tianjic"
          },
          {
            "from": "controller",
            "to": "axon",
            "type": "control",
            "locator": "Methods",
            "label": "",
            "source": "alt-tianjic"
          },
          {
            "from": "controller",
            "to": "soma",
            "type": "control",
            "locator": "Methods",
            "label": "",
            "source": "alt-tianjic"
          }
        ]
      },
      "originalCandidate": "Tianjic"
    },
    {
      "id": "queue-139",
      "name": "Intel Pohoiki Springs",
      "organization": "Intel Labs",
      "year": 2020,
      "yearLabel": "2020 fully configured chassis",
      "kind": "Neuromorphic research system",
      "status": "dossier",
      "track": "neural",
      "trackName": "Neuromorphic & reservoirs",
      "discoveryParadigms": [
        "neuromorphic"
      ],
      "paradigms": [
        "digital",
        "neuromorphic",
        "parallel"
      ],
      "architectures": [
        "spiking",
        "distributed",
        "heterogeneous"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "neural"
      ],
      "aliases": [],
      "sources": [
        "alt-pohoiki"
      ],
      "summary": "A 768-chip Loihi mesh is orchestrated by ARM/FPGA column hosts and an x86 super host.",
      "config": "Fully configured five-rack-unit chassis in the 2020 nearest-neighbor-search paper; first-generation Loihi, not Loihi 2.",
      "gaps": [
        "No direct mesh-to-Ethernet path is implied by the aggregate result association.",
        "Measured search performance is workload/recall/encoding specific; capacity alone is not an application benchmark."
      ],
      "insight": "Where can conventional host processing become a bottleneck in a sparse event system?",
      "fields": {
        "state": {
          "value": "Distributed synaptic weights and spike timing",
          "locator": "§III–IV",
          "source": "alt-pohoiki"
        },
        "compute": {
          "value": "768 Loihi chips across 24 Nahuku cards",
          "locator": "§II",
          "source": "alt-pohoiki"
        },
        "memory": {
          "value": "Per-chip neural/synaptic storage",
          "locator": "§II",
          "source": "alt-pohoiki"
        },
        "control": {
          "value": "Loihi barriers; x86 super-host orchestration",
          "locator": "§II",
          "source": "alt-pohoiki"
        },
        "io": {
          "value": "12×64 mesh; three ARM/FPGA hosts; Ethernet",
          "locator": "§II",
          "source": "alt-pohoiki"
        },
        "software": {
          "value": "Host encoding and neuromorphic mapping",
          "locator": "§IV; V-C",
          "source": "alt-pohoiki"
        },
        "workload": {
          "value": "Approximate nearest-neighbor search",
          "locator": "§III–V",
          "source": "alt-pohoiki"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Conventional orchestration around a Loihi mesh",
        "scope": "One of three columns and one chip are expanded. Mesh neighbors and barriers are aggregated, not every board wire.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "super",
            "label": "x86 super host",
            "subtitle": "ORCHESTRATION",
            "text": "Configures and coordinates the system.",
            "x": 30,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-pohoiki",
            "locator": "§II",
            "control": true
          },
          {
            "id": "switch",
            "label": "Ethernet switch",
            "subtitle": "HOST NETWORK",
            "text": "Consolidates host communication.",
            "x": 245,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-pohoiki",
            "locator": "§II",
            "control": false
          },
          {
            "id": "arm",
            "label": "ARM column host",
            "subtitle": "DATA ENCODING",
            "text": "Hosts a column of cards.",
            "x": 460,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-pohoiki",
            "locator": "§II",
            "control": false
          },
          {
            "id": "fpga",
            "label": "Arria 10 fabric",
            "subtitle": "PROTOCOL BRIDGE",
            "text": "Bridges AXI and Loihi protocol.",
            "x": 675,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-pohoiki",
            "locator": "§II",
            "control": false
          },
          {
            "id": "mesh",
            "label": "Loihi chip mesh",
            "subtitle": "12 × 64",
            "text": "Communicates spikes and barriers.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-pohoiki",
            "locator": "§II",
            "control": false
          },
          {
            "id": "x86",
            "label": "Embedded x86",
            "subtitle": "CHIP SUPPORT",
            "text": "Converts conventional data and spikes.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-pohoiki",
            "locator": "§II",
            "control": false
          },
          {
            "id": "neural",
            "label": "Neural cores",
            "subtitle": "LOCAL STATE",
            "text": "Compute distributed spike dynamics.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-pohoiki",
            "locator": "§II",
            "control": false
          },
          {
            "id": "weights",
            "label": "Synaptic index",
            "subtitle": "SEARCH DATABASE",
            "text": "Stores database partitions as weights.",
            "x": 245,
            "y": 370,
            "w": 160,
            "h": 62,
            "source": "alt-pohoiki",
            "locator": "§IV",
            "control": false
          },
          {
            "id": "result",
            "label": "Spike result decode",
            "subtitle": "HOST RESULTS",
            "text": "Interprets nearest-neighbor responses.",
            "x": 30,
            "y": 370,
            "w": 160,
            "h": 62,
            "source": "alt-pohoiki",
            "locator": "§IV",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "super",
            "to": "switch",
            "type": "control",
            "locator": "§II",
            "label": "",
            "source": "alt-pohoiki"
          },
          {
            "from": "switch",
            "to": "arm",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-pohoiki"
          },
          {
            "from": "arm",
            "to": "fpga",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-pohoiki"
          },
          {
            "from": "fpga",
            "to": "mesh",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-pohoiki"
          },
          {
            "from": "mesh",
            "to": "x86",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-pohoiki"
          },
          {
            "from": "x86",
            "to": "neural",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-pohoiki"
          },
          {
            "from": "weights",
            "to": "neural",
            "type": "data",
            "locator": "§IV",
            "label": "",
            "source": "alt-pohoiki"
          },
          {
            "from": "neural",
            "to": "mesh",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-pohoiki"
          },
          {
            "from": "mesh",
            "to": "result",
            "type": "association",
            "locator": "§IV",
            "label": "via hosts",
            "source": "alt-pohoiki"
          },
          {
            "from": "result",
            "to": "super",
            "type": "data",
            "locator": "§IV",
            "label": "",
            "source": "alt-pohoiki"
          },
          {
            "from": "super",
            "to": "weights",
            "type": "control",
            "locator": "§V-C",
            "label": "",
            "source": "alt-pohoiki"
          }
        ]
      },
      "originalCandidate": "Intel Pohoiki Springs"
    },
    {
      "id": "queue-140",
      "name": "Prezioso metal-oxide crossbar perceptron",
      "organization": "UC Santa Barbara / Stony Brook University",
      "year": 2014,
      "yearLabel": "December 2014 manuscript",
      "kind": "Laboratory experiment",
      "status": "dossier",
      "track": "neural",
      "trackName": "Neuromorphic & reservoirs",
      "discoveryParadigms": [
        "neuromorphic"
      ],
      "paradigms": [
        "analog",
        "hybrid",
        "neuromorphic"
      ],
      "architectures": [
        "crossbar",
        "in-memory"
      ],
      "substrates": [
        "memristive",
        "integrated"
      ],
      "models": [
        "neural"
      ],
      "aliases": [],
      "sources": [
        "alt-memristor-perceptron"
      ],
      "summary": "A transistor-free memristor crossbar performs weighted current sums; external electronics sense, activate, and train the network.",
      "config": "10-input, 3-output perceptron using a 10×6 crossbar fragment and 60 memristors in Prezioso et al.",
      "gaps": [
        "The small pattern set was used for training and testing; no generalization benchmark is inferred.",
        "Peripheral drive, sensing, activation, and experimental control are external."
      ],
      "insight": "Which costs remain outside the array when multiplication is physical?",
      "fields": {
        "state": {
          "value": "Conductance differences encode 30 weights",
          "locator": "Fig. 3",
          "source": "alt-memristor-perceptron"
        },
        "compute": {
          "value": "Column-current vector–matrix multiplication",
          "locator": "Pattern Classification Experiment",
          "source": "alt-memristor-perceptron"
        },
        "memory": {
          "value": "Two memristors per signed synaptic weight",
          "locator": "Eq. 3",
          "source": "alt-memristor-perceptron"
        },
        "control": {
          "value": "In-situ Manhattan weight updates",
          "locator": "Training description",
          "source": "alt-memristor-perceptron"
        },
        "io": {
          "value": "Input voltages and externally sensed currents",
          "locator": "Fig. 3",
          "source": "alt-memristor-perceptron"
        },
        "software": {
          "value": "Laboratory training procedure",
          "locator": "Fig. 2d",
          "source": "alt-memristor-perceptron"
        },
        "workload": {
          "value": "3×3 binary-pattern classification",
          "locator": "Fig. 2",
          "source": "alt-memristor-perceptron"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "An analog matrix product inside a laboratory learning loop",
        "scope": "Logical experiment flow, not an integrated stand-alone accelerator. Weight programming and inference are separate phases.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "patterns",
            "label": "Pattern / bias",
            "subtitle": "10 INPUTS",
            "text": "Maps pixels and bias to voltages.",
            "x": 30,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-memristor-perceptron",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "rows",
            "label": "Row voltage drive",
            "subtitle": "READ PHASE",
            "text": "Applies encoded voltages.",
            "x": 245,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-memristor-perceptron",
            "locator": "Fig. 3",
            "control": false
          },
          {
            "id": "array",
            "label": "Memristor subarray",
            "subtitle": "10 × 6",
            "text": "Multiplies through conductances.",
            "x": 460,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-memristor-perceptron",
            "locator": "Fig. 3",
            "control": false
          },
          {
            "id": "sense",
            "label": "Column sensing",
            "subtitle": "VIRTUAL GROUND",
            "text": "Measures paired column currents.",
            "x": 675,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-memristor-perceptron",
            "locator": "Fig. 3",
            "control": false
          },
          {
            "id": "subtract",
            "label": "Differential output",
            "subtitle": "SIGNED WEIGHTS",
            "text": "Subtracts paired current sums.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-memristor-perceptron",
            "locator": "Eq. 3",
            "control": false
          },
          {
            "id": "activation",
            "label": "External activation",
            "subtitle": "NONLINEARITY",
            "text": "Applies the output activation.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-memristor-perceptron",
            "locator": "Eq. 1",
            "control": false
          },
          {
            "id": "training",
            "label": "Training procedure",
            "subtitle": "ERROR / UPDATE",
            "text": "Determines weight-update signs.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-memristor-perceptron",
            "locator": "Fig. 2d",
            "control": true
          },
          {
            "id": "program",
            "label": "Programming pulses",
            "subtitle": "WRITE PHASE",
            "text": "Changes memristor conductances.",
            "x": 245,
            "y": 370,
            "w": 160,
            "h": 62,
            "source": "alt-memristor-perceptron",
            "locator": "Fig. 3c",
            "control": false
          },
          {
            "id": "target",
            "label": "Target classes",
            "subtitle": "SUPERVISION",
            "text": "Provides desired outputs.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-memristor-perceptron",
            "locator": "Fig. 2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "patterns",
            "to": "rows",
            "type": "data",
            "locator": "Fig. 3",
            "label": "",
            "source": "alt-memristor-perceptron"
          },
          {
            "from": "rows",
            "to": "array",
            "type": "data",
            "locator": "Fig. 3",
            "label": "",
            "source": "alt-memristor-perceptron"
          },
          {
            "from": "array",
            "to": "sense",
            "type": "data",
            "locator": "Fig. 3",
            "label": "",
            "source": "alt-memristor-perceptron"
          },
          {
            "from": "sense",
            "to": "subtract",
            "type": "data",
            "locator": "Eq. 3",
            "label": "",
            "source": "alt-memristor-perceptron"
          },
          {
            "from": "subtract",
            "to": "activation",
            "type": "data",
            "locator": "Eqs. 1–3",
            "label": "",
            "source": "alt-memristor-perceptron"
          },
          {
            "from": "activation",
            "to": "training",
            "type": "data",
            "locator": "Fig. 2d",
            "label": "",
            "source": "alt-memristor-perceptron"
          },
          {
            "from": "target",
            "to": "training",
            "type": "data",
            "locator": "Fig. 2d",
            "label": "",
            "source": "alt-memristor-perceptron"
          },
          {
            "from": "training",
            "to": "program",
            "type": "control",
            "locator": "Fig. 3c",
            "label": "",
            "source": "alt-memristor-perceptron"
          },
          {
            "from": "program",
            "to": "array",
            "type": "control",
            "locator": "Fig. 3c",
            "label": "",
            "source": "alt-memristor-perceptron"
          },
          {
            "from": "training",
            "to": "patterns",
            "type": "control",
            "locator": "Fig. 2d",
            "label": "next pattern",
            "source": "alt-memristor-perceptron"
          }
        ]
      },
      "originalCandidate": "Memristive neural crossbar experiments"
    },
    {
      "id": "queue-141",
      "name": "Paquot optoelectronic delay reservoir",
      "organization": "Université libre de Bruxelles / Ghent University",
      "year": 2011,
      "yearLabel": "2011 manuscript / 2012 experiment paper",
      "kind": "Laboratory experiment",
      "status": "dossier",
      "track": "neural",
      "trackName": "Neuromorphic & reservoirs",
      "discoveryParadigms": [
        "neuromorphic",
        "reservoir"
      ],
      "paradigms": [
        "analog",
        "optical",
        "reservoir",
        "hybrid"
      ],
      "architectures": [
        "reservoir-arch"
      ],
      "substrates": [
        "photonic",
        "integrated"
      ],
      "models": [
        "continuous",
        "neural"
      ],
      "aliases": [],
      "sources": [
        "alt-photonic-reservoir"
      ],
      "summary": "A single nonlinear optoelectronic feedback loop provides time-multiplexed virtual reservoir nodes.",
      "config": "Paquot et al. experimental loop; output is digitized and reconstructed offline, not an all-optical trained readout.",
      "gaps": [
        "Optical propagation speed does not remove waveform generation or readout overhead.",
        "The hardware uses an electrical feedback path and offline readout; it is not wholly optical."
      ],
      "insight": "How does delayed feedback create a high-dimensional state from one nonlinear element?",
      "fields": {
        "state": {
          "value": "Time samples of loop intensity",
          "locator": "§II.B",
          "source": "alt-photonic-reservoir"
        },
        "compute": {
          "value": "Mach–Zehnder intensity nonlinearity",
          "locator": "§II.C",
          "source": "alt-photonic-reservoir"
        },
        "memory": {
          "value": "Fiber propagation delay and loop dynamics",
          "locator": "§II.C",
          "source": "alt-photonic-reservoir"
        },
        "control": {
          "value": "Input mask, feedback gain, and timing",
          "locator": "§II.B–C",
          "source": "alt-photonic-reservoir"
        },
        "io": {
          "value": "Function generator; photodiode and digitizer",
          "locator": "Fig. 1",
          "source": "alt-photonic-reservoir"
        },
        "software": {
          "value": "Offline linear readout reconstruction",
          "locator": "§II.C",
          "source": "alt-photonic-reservoir"
        },
        "workload": {
          "value": "Channel equalization and speech recognition",
          "locator": "§II.D",
          "source": "alt-photonic-reservoir"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Masked drive, delayed feedback, digital readout",
        "scope": "The physical loop and offline readout of Fig. 1. Virtual nodes are time slots, not separate optical devices.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "input",
            "label": "Input × mask",
            "subtitle": "FUNCTION GENERATOR",
            "text": "Produces the masked input waveform.",
            "x": 30,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-reservoir",
            "locator": "§II.B–C",
            "control": false
          },
          {
            "id": "sum",
            "label": "Electrical mixer",
            "subtitle": "INPUT + FEEDBACK",
            "text": "Combines input and feedback voltage.",
            "x": 245,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-reservoir",
            "locator": "§II.C",
            "control": false
          },
          {
            "id": "mzm",
            "label": "MZ modulator",
            "subtitle": "NONLINEAR NODE",
            "text": "Modulates a continuous light source.",
            "x": 460,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-reservoir",
            "locator": "§II.C",
            "control": false
          },
          {
            "id": "laser",
            "label": "Continuous laser",
            "subtitle": "OPTICAL CARRIER",
            "text": "Illuminates the modulator.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-reservoir",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "fiber",
            "label": "Fiber spool",
            "subtitle": "DELAY MEMORY",
            "text": "Stores a round trip in propagation.",
            "x": 675,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-reservoir",
            "locator": "§II.C",
            "control": false
          },
          {
            "id": "pd",
            "label": "Photodiode",
            "subtitle": "OPTICAL → ELECTRICAL",
            "text": "Converts delayed intensity to voltage.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-reservoir",
            "locator": "§II.C",
            "control": false
          },
          {
            "id": "gain",
            "label": "Gain / attenuation",
            "subtitle": "LOOP SETTINGS",
            "text": "Sets the feedback operating point.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-reservoir",
            "locator": "§II.C",
            "control": false
          },
          {
            "id": "adc",
            "label": "Digitizer",
            "subtitle": "STATE SAMPLES",
            "text": "Records reservoir activity.",
            "x": 675,
            "y": 370,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-reservoir",
            "locator": "§II.C",
            "control": false
          },
          {
            "id": "readout",
            "label": "Offline readout",
            "subtitle": "COMPUTER",
            "text": "Trains and reconstructs the output.",
            "x": 460,
            "y": 370,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-reservoir",
            "locator": "§II.C",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "input",
            "to": "sum",
            "type": "data",
            "locator": "§II.C",
            "label": "",
            "source": "alt-photonic-reservoir"
          },
          {
            "from": "sum",
            "to": "mzm",
            "type": "data",
            "locator": "§II.C",
            "label": "",
            "source": "alt-photonic-reservoir"
          },
          {
            "from": "laser",
            "to": "mzm",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-photonic-reservoir"
          },
          {
            "from": "mzm",
            "to": "fiber",
            "type": "data",
            "locator": "§II.C",
            "label": "",
            "source": "alt-photonic-reservoir"
          },
          {
            "from": "fiber",
            "to": "pd",
            "type": "data",
            "locator": "§II.C",
            "label": "",
            "source": "alt-photonic-reservoir"
          },
          {
            "from": "pd",
            "to": "gain",
            "type": "data",
            "locator": "§II.C",
            "label": "",
            "source": "alt-photonic-reservoir"
          },
          {
            "from": "gain",
            "to": "sum",
            "type": "data",
            "locator": "§II.C",
            "label": "",
            "source": "alt-photonic-reservoir"
          },
          {
            "from": "pd",
            "to": "adc",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-photonic-reservoir"
          },
          {
            "from": "adc",
            "to": "readout",
            "type": "data",
            "locator": "§II.C",
            "label": "",
            "source": "alt-photonic-reservoir"
          },
          {
            "from": "input",
            "to": "readout",
            "type": "association",
            "locator": "§II.C",
            "label": "training alignment",
            "source": "alt-photonic-reservoir"
          }
        ]
      },
      "originalCandidate": "Delay-based photonic reservoir experiments"
    },
    {
      "id": "queue-142",
      "name": "IBM Q System One (2019)",
      "organization": "IBM",
      "year": 2019,
      "yearLabel": "2019 integrated system and experiment",
      "kind": "Integrated quantum computing system",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "hybrid"
      ],
      "architectures": [
        "gate-quantum"
      ],
      "substrates": [
        "superconducting"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-ibm-one",
        "alt-ibm-one-ghz"
      ],
      "summary": "An integrated cryogenic quantum system surrounds a fixed-frequency transmon processor with classical access and control.",
      "config": "2019 System One and its 20-qubit processor used by Wei et al.; later System One installations have different processors.",
      "gaps": [
        "The diagram does not transfer later heavy-hex processor connectivity to the 2019 device.",
        "Noise mitigation and GHZ verification are not universal fault tolerance."
      ],
      "insight": "How do integration and calibration support repeated circuit experiments?",
      "fields": {
        "state": {
          "value": "20 fixed-frequency transmon qubits",
          "locator": "Main text; Fig. 1",
          "source": "alt-ibm-one-ghz"
        },
        "compute": {
          "value": "Single-qubit and cross-resonance entangling gates",
          "locator": "Main text",
          "source": "alt-ibm-one-ghz"
        },
        "memory": {
          "value": "Quantum register; measured classical counts",
          "locator": "Fig. 2",
          "source": "alt-ibm-one-ghz"
        },
        "control": {
          "value": "Precision electronics and health firmware",
          "locator": "Component list",
          "source": "alt-ibm-one"
        },
        "io": {
          "value": "Quantum measurement",
          "locator": "Fig. 2",
          "source": "alt-ibm-one-ghz"
        },
        "software": {
          "value": "Hybrid circuit execution",
          "locator": "Component list",
          "source": "alt-ibm-one"
        },
        "workload": {
          "value": "GHZ-state preparation and verification",
          "locator": "Fig. 2",
          "source": "alt-ibm-one-ghz"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "System integration around a measured quantum circuit",
        "scope": "System services plus the published GHZ verification flow. Links aggregate interfaces, not a qubit wiring layout.",
        "width": 960,
        "height": 490,
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          {
            "id": "cloud",
            "label": "Cloud access",
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            "text": "Submits circuits.",
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            "control": false
          },
          {
            "id": "electronics",
            "label": "Control electronics",
            "subtitle": "PRECISION SIGNALS",
            "text": "Drives quantum operations.",
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            "locator": "Component list",
            "control": false
          },
          {
            "id": "firmware",
            "label": "Health firmware",
            "subtitle": "CALIBRATION",
            "text": "Maintains operating conditions.",
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            "source": "alt-ibm-one",
            "locator": "Component list",
            "control": true
          },
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            "id": "cryo",
            "label": "Cryogenic enclosure",
            "subtitle": "ISOLATION",
            "text": "Supports the quantum register.",
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            "locator": "Designing a First",
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          },
          {
            "id": "register",
            "label": "20 transmons",
            "subtitle": "QUANTUM STATE",
            "text": "Hosts the circuit.",
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            "locator": "Fig. 1",
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          },
          {
            "id": "prepare",
            "label": "GHZ preparation",
            "subtitle": "H + CX SEQUENCE",
            "text": "Entangles selected qubits.",
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            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "reverse",
            "label": "Rotation + inverse",
            "subtitle": "MQC PROTOCOL",
            "text": "Maps coherence to population.",
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            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "counts",
            "label": "Measured counts",
            "subtitle": "CLASSICAL OUTPUT",
            "text": "Estimates return probability.",
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            "locator": "Fig. 2",
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          },
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            "id": "analysis",
            "label": "Readout correction",
            "subtitle": "POSTPROCESSING",
            "text": "Bounds state fidelity.",
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          {
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            "label": "first circuit stage",
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          },
          {
            "from": "register",
            "to": "reverse",
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            "locator": "Fig. 2",
            "label": "logical sequence",
            "source": "alt-ibm-one-ghz"
          },
          {
            "from": "prepare",
            "to": "reverse",
            "type": "control",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-ibm-one-ghz"
          },
          {
            "from": "reverse",
            "to": "counts",
            "type": "data",
            "locator": "Fig. 2",
            "label": "",
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          },
          {
            "from": "counts",
            "to": "analysis",
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            "locator": "Readout Calibration",
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          },
          {
            "from": "analysis",
            "to": "cloud",
            "type": "data",
            "locator": "Component list",
            "label": "classical result",
            "source": "alt-ibm-one"
          }
        ]
      },
      "originalCandidate": "IBM Quantum System One"
    },
    {
      "id": "queue-143",
      "name": "Google Sycamore (2019)",
      "organization": "Google AI Quantum",
      "year": 2019,
      "yearLabel": "2019 sampling experiment",
      "kind": "Quantum research processor",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "hybrid"
      ],
      "architectures": [
        "gate-quantum"
      ],
      "substrates": [
        "superconducting"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-sycamore"
      ],
      "summary": "A tunably coupled transmon lattice executes repeated random circuits with classical calibration and sampling.",
      "config": "The 54-qubit design with one inoperable qubit; the reported sampling experiments used 53 qubits.",
      "gaps": [
        "A benchmark-specific sampling result does not establish practical application speedup.",
        "Historical classical runtime estimates are not presented as current records."
      ],
      "insight": "Why must gate calibration and measurement fidelity be assessed simultaneously?",
      "fields": {
        "state": {
          "value": "53 active transmons in sampling experiment",
          "locator": "pp. 505–506",
          "source": "alt-sycamore"
        },
        "compute": {
          "value": "Microwave rotations and tunable two-qubit interactions",
          "locator": "p. 507",
          "source": "alt-sycamore"
        },
        "memory": {
          "value": "Coherent qubit register within each shot",
          "locator": "Fig. 3",
          "source": "alt-sycamore"
        },
        "control": {
          "value": "Room-temperature DAC signals; pair calibration",
          "locator": "pp. 506–507",
          "source": "alt-sycamore"
        },
        "io": {
          "value": "Frequency-multiplexed dispersive readout",
          "locator": "p. 507",
          "source": "alt-sycamore"
        },
        "software": {
          "value": "Random circuits and cross-entropy benchmarking",
          "locator": "Figs. 3–4",
          "source": "alt-sycamore"
        },
        "workload": {
          "value": "Random circuit sampling",
          "locator": "p. 505",
          "source": "alt-sycamore"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Calibrate → evolve → measure → benchmark",
        "scope": "Functional control/readout chain for the 2019 experiment; nearest-neighbor coupling is aggregated.",
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        "height": 490,
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          {
            "id": "circuits",
            "label": "Random circuits",
            "subtitle": "CLASSICAL INPUT",
            "text": "Specifies gate cycles.",
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            "source": "alt-sycamore",
            "locator": "Fig. 3",
            "control": false
          },
          {
            "id": "dac",
            "label": "DAC electronics",
            "subtitle": "ROOM TEMPERATURE",
            "text": "Synthesizes control signals.",
            "x": 245,
            "y": 35,
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            "h": 62,
            "source": "alt-sycamore",
            "locator": "pp. 506–507",
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          },
          {
            "id": "lines",
            "label": "Filters / attenuators",
            "subtitle": "CRYOGENIC PATH",
            "text": "Carries conditioned signals.",
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            "h": 62,
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          },
          {
            "id": "qubits",
            "label": "Transmon array",
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            "text": "Holds quantum state.",
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            "source": "alt-sycamore",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "coupler",
            "label": "Tunable couplers",
            "subtitle": "NEAREST NEIGHBORS",
            "text": "Enables pair interactions.",
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            "id": "readout",
            "label": "Multiplexed readout",
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          },
          {
            "id": "amp",
            "label": "Cryogenic amplifiers",
            "subtitle": "TWO STAGES",
            "text": "Boosts readout signal.",
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          },
          {
            "id": "adc",
            "label": "ADC / demultiplexer",
            "subtitle": "CLASSICAL SAMPLES",
            "text": "Extracts measurement records.",
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            "source": "alt-sycamore",
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          },
          {
            "id": "xeb",
            "label": "XEB / calibration",
            "subtitle": "CLASSICAL ANALYSIS",
            "text": "Checks fidelity on tractable cases.",
            "x": 30,
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            "h": 62,
            "source": "alt-sycamore",
            "locator": "pp. 506–508",
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        ],
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          {
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            "locator": "pp. 506–507",
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          {
            "from": "lines",
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          {
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          {
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          {
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            "type": "association",
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          {
            "from": "qubits",
            "to": "readout",
            "type": "data",
            "locator": "p. 507",
            "label": "",
            "source": "alt-sycamore"
          },
          {
            "from": "readout",
            "to": "amp",
            "type": "data",
            "locator": "p. 507",
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          {
            "from": "amp",
            "to": "adc",
            "type": "data",
            "locator": "p. 507",
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          {
            "from": "adc",
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            "type": "data",
            "locator": "pp. 507–508",
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          },
          {
            "from": "xeb",
            "to": "dac",
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        ]
      },
      "originalCandidate": "Google Sycamore"
    },
    {
      "id": "queue-144",
      "name": "Google Willow distance-7 memory experiment",
      "organization": "Google Quantum AI",
      "year": 2024,
      "yearLabel": "2024 manuscript and Willow announcement",
      "kind": "Quantum error-correction experiment",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "hybrid"
      ],
      "architectures": [
        "gate-quantum",
        "fault-tolerant"
      ],
      "substrates": [
        "superconducting"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-willow-qec",
        "alt-willow-name"
      ],
      "summary": "Repeated stabilizer extraction protects one encoded memory; decoding remains part of the classical boundary.",
      "config": "105-qubit processor: distance-7 memory using 49 data, 48 measure and four boundary leakage-removal qubits; not the separate 72-qubit real-time-decoding experiment.",
      "gaps": [
        "The 105-qubit distance-7 result used offline high-accuracy decoders in this manuscript.",
        "A protected memory is not a demonstrated universal fault-tolerant application processor."
      ],
      "insight": "Why are syndrome extraction and logical readout separate operations?",
      "fields": {
        "state": {
          "value": "One encoded surface-code memory",
          "locator": "§II",
          "source": "alt-willow-qec"
        },
        "compute": {
          "value": "Square-grid transmons and stabilizer cycles",
          "locator": "§II; Fig. 1",
          "source": "alt-willow-qec"
        },
        "memory": {
          "value": "49 data qubits encode the logical state",
          "locator": "§II",
          "source": "alt-willow-qec"
        },
        "control": {
          "value": "Repeated parity extraction and leakage removal",
          "locator": "§II",
          "source": "alt-willow-qec"
        },
        "io": {
          "value": "Syndrome stream plus terminal data measurement",
          "locator": "§II",
          "source": "alt-willow-qec"
        },
        "software": {
          "value": "Offline neural-network or matching decoders",
          "locator": "§II",
          "source": "alt-willow-qec"
        },
        "workload": {
          "value": "Logical quantum-memory benchmark",
          "locator": "§II",
          "source": "alt-willow-qec"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Distance-7 memory with offline decoding",
        "scope": "Published memory protocol; lines depict parity and classical information dependencies, not direct measurement of stored logical state each cycle.",
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        "height": 490,
        "nodes": [
          {
            "id": "init",
            "label": "Basis preparation",
            "subtitle": "X OR Z BASIS",
            "text": "Initializes data qubits.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-willow-qec",
            "locator": "§II",
            "control": false
          },
          {
            "id": "data",
            "label": "Data qubits",
            "subtitle": "49 QUBITS",
            "text": "Store encoded information.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-willow-qec",
            "locator": "§II",
            "control": false
          },
          {
            "id": "parity",
            "label": "Entangling cycles",
            "subtitle": "STABILIZERS",
            "text": "Couples neighboring code qubits.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-willow-qec",
            "locator": "§II; Fig. 1",
            "control": false
          },
          {
            "id": "measure",
            "label": "Measure qubits",
            "subtitle": "48 QUBITS",
            "text": "Extract parity information.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-willow-qec",
            "locator": "§II",
            "control": false
          },
          {
            "id": "syndrome",
            "label": "Syndrome record",
            "subtitle": "CLASSICAL",
            "text": "Accumulates cycle outcomes.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-willow-qec",
            "locator": "§II",
            "control": false
          },
          {
            "id": "leak",
            "label": "Leakage removal",
            "subtitle": "DQLR",
            "text": "Removes higher-state population.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-willow-qec",
            "locator": "§II; Fig. 1",
            "control": false
          },
          {
            "id": "terminal",
            "label": "Data measurement",
            "subtitle": "FINAL READOUT",
            "text": "Measures physical data qubits.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-willow-qec",
            "locator": "§II",
            "control": false
          },
          {
            "id": "decode",
            "label": "Offline decoder",
            "subtitle": "CLASSICAL",
            "text": "Infers corrected logical outcome.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-willow-qec",
            "locator": "§II",
            "control": false
          },
          {
            "id": "compare",
            "label": "Logical comparison",
            "subtitle": "MEMORY RESULT",
            "text": "Compares output with preparation.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-willow-qec",
            "locator": "§II",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "init",
            "to": "data",
            "type": "control",
            "locator": "§II",
            "label": "",
            "source": "alt-willow-qec"
          },
          {
            "from": "data",
            "to": "parity",
            "type": "association",
            "locator": "Fig. 1",
            "label": "",
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          },
          {
            "from": "parity",
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            "type": "association",
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            "label": "",
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          },
          {
            "from": "measure",
            "to": "syndrome",
            "type": "data",
            "locator": "§II",
            "label": "",
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          },
          {
            "from": "parity",
            "to": "leak",
            "type": "control",
            "locator": "§II",
            "label": "after extraction",
            "source": "alt-willow-qec"
          },
          {
            "from": "leak",
            "to": "data",
            "type": "control",
            "locator": "§II",
            "label": "",
            "source": "alt-willow-qec"
          },
          {
            "from": "leak",
            "to": "parity",
            "type": "control",
            "locator": "§II",
            "label": "next cycle",
            "source": "alt-willow-qec"
          },
          {
            "from": "data",
            "to": "terminal",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-willow-qec"
          },
          {
            "from": "terminal",
            "to": "decode",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-willow-qec"
          },
          {
            "from": "syndrome",
            "to": "decode",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-willow-qec"
          },
          {
            "from": "decode",
            "to": "compare",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-willow-qec"
          },
          {
            "from": "init",
            "to": "compare",
            "type": "association",
            "locator": "§II",
            "label": "known initial state",
            "source": "alt-willow-qec"
          }
        ]
      },
      "originalCandidate": "Google Willow"
    },
    {
      "id": "queue-145",
      "name": "Rigetti Aspen-M-1",
      "organization": "Rigetti",
      "year": 2022,
      "yearLabel": "February 2022 commercial deployment",
      "kind": "Superconducting quantum computer",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "hybrid"
      ],
      "architectures": [
        "gate-quantum",
        "heterogeneous"
      ],
      "substrates": [
        "superconducting",
        "integrated"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-aspen-announcement",
        "alt-rigetti-stack"
      ],
      "summary": "Two superconducting dies form an 80-qubit processor controlled through a classical quantum-cloud stack.",
      "config": "Aspen-M-1 deployed 15 February 2022, not the later M-2/M-3 or Ankaa processors.",
      "gaps": [
        "The source supports chip hierarchy, not an exhaustive Aspen-M-1 coupling graph.",
        "Manufacturer gate and speed metrics are not evidence of universal fault tolerance."
      ],
      "insight": "Where does modular chip integration meet classical control?",
      "fields": {
        "state": {
          "value": "80 superconducting qubits",
          "locator": "Aspen-M-1 historical table",
          "source": "alt-rigetti-stack"
        },
        "compute": {
          "value": "Single-qubit and CZ / XY pair operations",
          "locator": "Aspen-M-1 historical table",
          "source": "alt-rigetti-stack"
        },
        "memory": {
          "value": "Coherent QPU register; classical controller memory",
          "locator": "Control Systems",
          "source": "alt-rigetti-stack"
        },
        "control": {
          "value": "FPGA-based pulse and readout hardware",
          "locator": "Control Systems",
          "source": "alt-rigetti-stack"
        },
        "io": {
          "value": "QCS access",
          "locator": "Release",
          "source": "alt-aspen-announcement"
        },
        "software": {
          "value": "Hybrid quantum/classical execution",
          "locator": "Release",
          "source": "alt-aspen-announcement"
        },
        "workload": {
          "value": "Programmable quantum circuits",
          "locator": "Release",
          "source": "alt-aspen-announcement"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Two dies within the quantum-control boundary",
        "scope": "Public system hierarchy and generic Rigetti control stack; no undocumented die-to-die pin topology or exact cable assembly is asserted.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "qcs",
            "label": "QCS client",
            "subtitle": "CLASSICAL",
            "text": "Submits quantum programs.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-aspen-announcement",
            "locator": "Release",
            "control": false
          },
          {
            "id": "controller",
            "label": "CPU / FPGA control",
            "subtitle": "ROOM TEMPERATURE",
            "text": "Sequences pulses and readout.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-rigetti-stack",
            "locator": "Control Systems",
            "control": false
          },
          {
            "id": "signals",
            "label": "Cryogenic signal path",
            "subtitle": "INTERFACE",
            "text": "Connects controller to package.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-rigetti-stack",
            "locator": "Control Systems",
            "control": false
          },
          {
            "id": "package",
            "label": "Multi-chip package",
            "subtitle": "ASPEN-M",
            "text": "Integrates two 40-qubit dies.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-aspen-announcement",
            "locator": "Release",
            "control": false
          },
          {
            "id": "diea",
            "label": "40-qubit die A",
            "subtitle": "QUANTUM REGISTER",
            "text": "One processor module.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-aspen-announcement",
            "locator": "Release",
            "control": false
          },
          {
            "id": "dieb",
            "label": "40-qubit die B",
            "subtitle": "QUANTUM REGISTER",
            "text": "Second processor module.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-aspen-announcement",
            "locator": "Release",
            "control": false
          },
          {
            "id": "resonator",
            "label": "Readout resonators",
            "subtitle": "MEASUREMENT",
            "text": "Transduces qubit state.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-rigetti-stack",
            "locator": "Superconducting Quantum Processors",
            "control": false
          },
          {
            "id": "results",
            "label": "Classical results",
            "subtitle": "QCS OUTPUT",
            "text": "Returns sampled outcomes.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-aspen-announcement",
            "locator": "Release",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "qcs",
            "to": "controller",
            "type": "control",
            "locator": "Release",
            "label": "",
            "source": "alt-aspen-announcement"
          },
          {
            "from": "controller",
            "to": "signals",
            "type": "control",
            "locator": "Control Systems",
            "label": "",
            "source": "alt-rigetti-stack"
          },
          {
            "from": "signals",
            "to": "package",
            "type": "control",
            "locator": "Control Systems",
            "label": "",
            "source": "alt-rigetti-stack"
          },
          {
            "from": "package",
            "to": "diea",
            "type": "association",
            "locator": "Release",
            "label": "",
            "source": "alt-aspen-announcement"
          },
          {
            "from": "package",
            "to": "dieb",
            "type": "association",
            "locator": "Release",
            "label": "",
            "source": "alt-aspen-announcement"
          },
          {
            "from": "diea",
            "to": "dieb",
            "type": "association",
            "locator": "Release",
            "label": "inter-chip coupling",
            "source": "alt-aspen-announcement"
          },
          {
            "from": "diea",
            "to": "resonator",
            "type": "data",
            "locator": "Superconducting Quantum Processors",
            "label": "",
            "source": "alt-rigetti-stack"
          },
          {
            "from": "dieb",
            "to": "resonator",
            "type": "data",
            "locator": "Superconducting Quantum Processors",
            "label": "",
            "source": "alt-rigetti-stack"
          },
          {
            "from": "resonator",
            "to": "controller",
            "type": "data",
            "locator": "Control Systems",
            "label": "",
            "source": "alt-rigetti-stack"
          },
          {
            "from": "controller",
            "to": "results",
            "type": "data",
            "locator": "Release",
            "label": "",
            "source": "alt-aspen-announcement"
          }
        ]
      },
      "originalCandidate": "Rigetti Aspen-M"
    },
    {
      "id": "queue-146",
      "name": "IonQ Forte initial 31-qubit configuration",
      "organization": "IonQ",
      "year": 2023,
      "yearLabel": "2023 initial-configuration report",
      "kind": "Trapped-ion quantum computer",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "hybrid"
      ],
      "architectures": [
        "gate-quantum"
      ],
      "substrates": [
        "atomic",
        "photonic"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-ionq-forte"
      ],
      "summary": "Software-steered laser beams address a linear ion register with any-pair entangling operations.",
      "config": "35-ion chain, central 31 computational qubits, 32 detection channels, as described in the initial Forte report.",
      "gaps": [
        "Ion count, computational qubit count and IonQ’s algorithmic-qubit metric are distinct.",
        "The early configuration does not assert quantum error correction merely because the architecture roadmap mentions it."
      ],
      "insight": "How does configurable optical addressing differ from fixed qubit wiring?",
      "fields": {
        "state": {
          "value": "Ytterbium-ion qubits",
          "locator": "Introducing IonQ Forte",
          "source": "alt-ionq-forte"
        },
        "compute": {
          "value": "Laser gates; any-pair interaction within chain",
          "locator": "Software-Configurable section",
          "source": "alt-ionq-forte"
        },
        "memory": {
          "value": "Central 31 ions of a 35-ion chain",
          "locator": "First Configuration",
          "source": "alt-ionq-forte"
        },
        "control": {
          "value": "RF-controlled acousto-optic deflectors",
          "locator": "AOD Technology",
          "source": "alt-ionq-forte"
        },
        "io": {
          "value": "Individual detection channels",
          "locator": "First Configuration",
          "source": "alt-ionq-forte"
        },
        "software": {
          "value": "Software-defined addressing and pulse sequences",
          "locator": "AOD Technology",
          "source": "alt-ionq-forte"
        },
        "workload": {
          "value": "Gate characterization and quantum circuits",
          "locator": "Early Performance",
          "source": "alt-ionq-forte"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Software steering around a stationary ion chain",
        "scope": "Optical addressing and measurement boundary. Any-pair gates are mediated by ion interactions, not 465 physical wires.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "software",
            "label": "Software settings",
            "subtitle": "CLASSICAL",
            "text": "Selects ions and pulses.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-ionq-forte",
            "locator": "Software-Configurable section",
            "control": false
          },
          {
            "id": "rf",
            "label": "RF drive",
            "subtitle": "BEAM ANGLE",
            "text": "Controls deflection.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-ionq-forte",
            "locator": "AOD Technology",
            "control": false
          },
          {
            "id": "aod",
            "label": "Acousto-optic deflector",
            "subtitle": "STEERABLE OPTICS",
            "text": "Positions addressing beams.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-ionq-forte",
            "locator": "AOD Technology",
            "control": false
          },
          {
            "id": "laser",
            "label": "Laser beams",
            "subtitle": "GATE CONTROL",
            "text": "Illuminates selected ions.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-ionq-forte",
            "locator": "Introducing IonQ Forte",
            "control": false
          },
          {
            "id": "chain",
            "label": "35-ion chain",
            "subtitle": "31 COMPUTATIONAL",
            "text": "Carries qubit states.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-ionq-forte",
            "locator": "First Configuration",
            "control": false
          },
          {
            "id": "interaction",
            "label": "Coulomb interaction",
            "subtitle": "ANY-PAIR GATES",
            "text": "Enables entanglement.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-ionq-forte",
            "locator": "Software-Configurable section",
            "control": false
          },
          {
            "id": "detect",
            "label": "Detection channels",
            "subtitle": "32 AVAILABLE",
            "text": "Measures individual qubits.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-ionq-forte",
            "locator": "First Configuration",
            "control": false
          },
          {
            "id": "benchmark",
            "label": "Gate characterization",
            "subtitle": "CLASSICAL ANALYSIS",
            "text": "Assesses selected operations.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-ionq-forte",
            "locator": "Early Performance",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "software",
            "to": "rf",
            "type": "control",
            "locator": "AOD Technology",
            "label": "",
            "source": "alt-ionq-forte"
          },
          {
            "from": "rf",
            "to": "aod",
            "type": "control",
            "locator": "AOD Technology",
            "label": "",
            "source": "alt-ionq-forte"
          },
          {
            "from": "aod",
            "to": "laser",
            "type": "control",
            "locator": "AOD Technology",
            "label": "",
            "source": "alt-ionq-forte"
          },
          {
            "from": "laser",
            "to": "chain",
            "type": "control",
            "locator": "Introducing IonQ Forte",
            "label": "",
            "source": "alt-ionq-forte"
          },
          {
            "from": "chain",
            "to": "interaction",
            "type": "association",
            "locator": "Software-Configurable section",
            "label": "",
            "source": "alt-ionq-forte"
          },
          {
            "from": "interaction",
            "to": "chain",
            "type": "association",
            "locator": "Software-Configurable section",
            "label": "",
            "source": "alt-ionq-forte"
          },
          {
            "from": "chain",
            "to": "detect",
            "type": "data",
            "locator": "First Configuration",
            "label": "",
            "source": "alt-ionq-forte"
          },
          {
            "from": "detect",
            "to": "benchmark",
            "type": "data",
            "locator": "Early Performance",
            "label": "",
            "source": "alt-ionq-forte"
          },
          {
            "from": "software",
            "to": "laser",
            "type": "control",
            "locator": "Software-Configurable section",
            "label": "pulse design",
            "source": "alt-ionq-forte"
          },
          {
            "from": "benchmark",
            "to": "software",
            "type": "association",
            "locator": "Early Performance",
            "label": "characterization feedback",
            "source": "alt-ionq-forte"
          }
        ]
      },
      "originalCandidate": "IonQ Forte"
    },
    {
      "id": "queue-147",
      "name": "Quantinuum H2 original 32-qubit configuration",
      "organization": "Quantinuum",
      "year": 2023,
      "yearLabel": "2023 race-track processor paper",
      "kind": "Trapped-ion quantum computer",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "hybrid"
      ],
      "architectures": [
        "gate-quantum"
      ],
      "substrates": [
        "atomic",
        "photonic"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-quantinuum-h2"
      ],
      "summary": "Ions circulate through a race-track trap so arbitrary pairs can meet in laser-operated gate zones.",
      "config": "Original 32-qubit H2 with 32 Yb–Ba pairs; DG01–DG04 perform gates, preparation and measurement. Upper zones support rearrangement.",
      "gaps": [
        "Arbitrary circuit connectivity requires transport, cooling and scheduling time.",
        "The reported repetition-code analysis does not imply general logical gate fault tolerance."
      ],
      "insight": "How does physical transport provide circuit connectivity without logical SWAP gates?",
      "fields": {
        "state": {
          "value": "171Yb+ hyperfine qubits",
          "locator": "§II.2",
          "source": "alt-quantinuum-h2"
        },
        "compute": {
          "value": "Raman single-qubit and parameterized ZZ gates",
          "locator": "§II.3",
          "source": "alt-quantinuum-h2"
        },
        "memory": {
          "value": "32 qubit ions with Ba cooling partners",
          "locator": "§II.2",
          "source": "alt-quantinuum-h2"
        },
        "control": {
          "value": "Electrode waveforms and batch scheduling",
          "locator": "§II.1; II.5",
          "source": "alt-quantinuum-h2"
        },
        "io": {
          "value": "State-dependent fluorescence / PMT array",
          "locator": "§II.4",
          "source": "alt-quantinuum-h2"
        },
        "software": {
          "value": "OpenQASM, QIR and Wasm classical interaction",
          "locator": "§II.6",
          "source": "alt-quantinuum-h2"
        },
        "workload": {
          "value": "Circuits, simulation and repetition-code benchmarks",
          "locator": "§§IV–V",
          "source": "alt-quantinuum-h2"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Transport, cool, gate, measure, branch",
        "scope": "One processing batch is expanded; the trap has eight physical gate-zone regions but only four quantum-operational DG zones here.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "program",
            "label": "QASM / QIR program",
            "subtitle": "CLASSICAL",
            "text": "Supplies circuit layers.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-quantinuum-h2",
            "locator": "§II.6",
            "control": false
          },
          {
            "id": "schedule",
            "label": "Batch / transport plan",
            "subtitle": "CONTROL",
            "text": "Pairs ions for each layer.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-quantinuum-h2",
            "locator": "§II.5",
            "control": false
          },
          {
            "id": "electrode",
            "label": "Electrode waveforms",
            "subtitle": "RACE-TRACK CONTROL",
            "text": "Rearranges ion pairs.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-quantinuum-h2",
            "locator": "§II.1; II.5",
            "control": false
          },
          {
            "id": "storage",
            "label": "Conveyor regions",
            "subtitle": "ION STORAGE",
            "text": "Holds circulating pairs.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-quantinuum-h2",
            "locator": "§II.1",
            "control": false
          },
          {
            "id": "gate",
            "label": "Four DG zones",
            "subtitle": "QUANTUM OPERATIONS",
            "text": "Hosts selected ion pairs.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-quantinuum-h2",
            "locator": "§II.1",
            "control": false
          },
          {
            "id": "cool",
            "label": "Ba sympathetic cooling",
            "subtitle": "MOTIONAL RESET",
            "text": "Cools before entangling gates.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-quantinuum-h2",
            "locator": "§II.5",
            "control": false
          },
          {
            "id": "raman",
            "label": "Raman beams",
            "subtitle": "GATE PULSES",
            "text": "Drives rotations and ZZ gates.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-quantinuum-h2",
            "locator": "§II.3",
            "control": false
          },
          {
            "id": "pmt",
            "label": "Fluorescence / PMT",
            "subtitle": "CLASSICAL READOUT",
            "text": "Reads selected qubits.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-quantinuum-h2",
            "locator": "§II.4",
            "control": false
          },
          {
            "id": "wasm",
            "label": "Classical environment",
            "subtitle": "FEED-FORWARD",
            "text": "Processes mid-circuit outcomes.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-quantinuum-h2",
            "locator": "§II.6",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "program",
            "to": "schedule",
            "type": "control",
            "locator": "§II.5–6",
            "label": "",
            "source": "alt-quantinuum-h2"
          },
          {
            "from": "schedule",
            "to": "electrode",
            "type": "control",
            "locator": "§II.5",
            "label": "",
            "source": "alt-quantinuum-h2"
          },
          {
            "from": "electrode",
            "to": "storage",
            "type": "control",
            "locator": "§II.1",
            "label": "",
            "source": "alt-quantinuum-h2"
          },
          {
            "from": "storage",
            "to": "gate",
            "type": "data",
            "locator": "§II.5",
            "label": "ion transport",
            "source": "alt-quantinuum-h2"
          },
          {
            "from": "gate",
            "to": "storage",
            "type": "data",
            "locator": "§II.5",
            "label": "batch shift",
            "source": "alt-quantinuum-h2"
          },
          {
            "from": "cool",
            "to": "gate",
            "type": "control",
            "locator": "§II.5",
            "label": "",
            "source": "alt-quantinuum-h2"
          },
          {
            "from": "raman",
            "to": "gate",
            "type": "control",
            "locator": "§II.3",
            "label": "",
            "source": "alt-quantinuum-h2"
          },
          {
            "from": "schedule",
            "to": "raman",
            "type": "control",
            "locator": "§II.5",
            "label": "",
            "source": "alt-quantinuum-h2"
          },
          {
            "from": "gate",
            "to": "pmt",
            "type": "data",
            "locator": "§II.4",
            "label": "",
            "source": "alt-quantinuum-h2"
          },
          {
            "from": "pmt",
            "to": "wasm",
            "type": "data",
            "locator": "§II.6",
            "label": "",
            "source": "alt-quantinuum-h2"
          },
          {
            "from": "wasm",
            "to": "schedule",
            "type": "control",
            "locator": "§II.6",
            "label": "",
            "source": "alt-quantinuum-h2"
          }
        ]
      },
      "originalCandidate": "Quantinuum H2"
    },
    {
      "id": "queue-148",
      "name": "Quantinuum H1-1 20-qubit upgrade",
      "organization": "Quantinuum",
      "year": 2022,
      "yearLabel": "June 2022 upgrade",
      "kind": "Trapped-ion quantum computer",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "hybrid"
      ],
      "architectures": [
        "gate-quantum"
      ],
      "substrates": [
        "atomic",
        "photonic"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-quantinuum-h1"
      ],
      "summary": "Electrode-controlled ion rearrangement feeds five optically addressed gate zones in a linear trap.",
      "config": "H1-1 after the June 2022 upgrade: 20 computational qubits and five simultaneously addressed gate zones.",
      "gaps": [
        "The four-qubit 2020 QCCD prototype is not substituted for this commercial 20-qubit configuration.",
        "The institutional overview does not specify detector wiring or all classical latencies."
      ],
      "insight": "Why does increasing gate zones matter as much as increasing ion count?",
      "fields": {
        "state": {
          "value": "20 fully connected computational qubits",
          "locator": "Key upgrades",
          "source": "alt-quantinuum-h1"
        },
        "compute": {
          "value": "Laser gates in five parallel zones",
          "locator": "Key upgrades",
          "source": "alt-quantinuum-h1"
        },
        "memory": {
          "value": "Ion chain in unchanged trap",
          "locator": "Upgrade comparison",
          "source": "alt-quantinuum-h1"
        },
        "control": {
          "value": "Electrode voltages rearrange ion pairs",
          "locator": "Ion dance",
          "source": "alt-quantinuum-h1"
        },
        "io": {
          "value": "Circuit input and mid-circuit measurements",
          "locator": "Key upgrades; Ion dance",
          "source": "alt-quantinuum-h1"
        },
        "software": {
          "value": "Compiler schedules pairing and gates",
          "locator": "Ion dance",
          "source": "alt-quantinuum-h1"
        },
        "workload": {
          "value": "User-submitted quantum circuits",
          "locator": "Ion dance",
          "source": "alt-quantinuum-h1"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Compile each circuit layer into an ion dance",
        "scope": "The 2022 five-zone H1-1 arrangement; arbitrary pair connectivity is realized through transport, not simultaneous gates between every pair.",
        "width": 960,
        "height": 490,
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          {
            "id": "circuit",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-quantinuum-h1",
            "locator": "Ion dance",
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            "id": "compile",
            "label": "Pairing compiler",
            "subtitle": "CLASSICAL",
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            "locator": "Ion dance",
            "control": false
          },
          {
            "id": "volt",
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            "subtitle": "TRANSPORT CONTROL",
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            "w": 160,
            "h": 62,
            "source": "alt-quantinuum-h1",
            "locator": "Ion dance",
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          },
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            "id": "chain",
            "label": "20-qubit chain",
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            "locator": "Key upgrades; Ion dance",
            "control": false
          },
          {
            "id": "zones",
            "label": "Five gate zones",
            "subtitle": "PARALLEL OPERATIONS",
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            "locator": "Key upgrades",
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            "id": "optics",
            "label": "Optical delivery",
            "subtitle": "REDESIGNED IN 2022",
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            "source": "alt-quantinuum-h1",
            "locator": "Upgrade comparison",
            "control": false
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            "id": "measure",
            "label": "Mid-circuit readout",
            "subtitle": "CLASSICAL OUTCOME",
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            "w": 160,
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            "source": "alt-quantinuum-h1",
            "locator": "Key upgrades",
            "control": false
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          {
            "id": "next",
            "label": "Next circuit layer",
            "subtitle": "SEQUENCING",
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            "source": "alt-quantinuum-h1",
            "locator": "Ion dance",
            "control": false
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        ],
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          },
          {
            "from": "chain",
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            "locator": "Ion dance",
            "label": "ion movement",
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          },
          {
            "from": "optics",
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            "locator": "Key upgrades",
            "label": "",
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          },
          {
            "from": "zones",
            "to": "chain",
            "type": "data",
            "locator": "Ion dance",
            "label": "rearrange again",
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          },
          {
            "from": "zones",
            "to": "measure",
            "type": "data",
            "locator": "Key upgrades",
            "label": "",
            "source": "alt-quantinuum-h1"
          },
          {
            "from": "measure",
            "to": "next",
            "type": "control",
            "locator": "Key upgrades",
            "label": "",
            "source": "alt-quantinuum-h1"
          },
          {
            "from": "zones",
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            "type": "control",
            "locator": "Ion dance",
            "label": "",
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          },
          {
            "from": "next",
            "to": "compile",
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            "locator": "Ion dance",
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        ]
      },
      "originalCandidate": "Quantinuum H1"
    },
    {
      "id": "queue-149",
      "name": "Atom Computing Phoenix nuclear-spin register",
      "organization": "Atom Computing",
      "year": 2021,
      "yearLabel": "2021 manuscript / 2022 publication",
      "kind": "Neutral-atom register experiment",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
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        "quantum",
        "hybrid"
      ],
      "architectures": [
        "gate-quantum"
      ],
      "substrates": [
        "atomic",
        "photonic"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-atom-phoenix"
      ],
      "summary": "Rearranged strontium atoms form an individually controlled nuclear-spin register with optical state readout.",
      "config": "21-qubit 7 × 3 computational subarray inside 110 optical tweezer sites; no entangling-gate network is claimed by this paper.",
      "gaps": [
        "Single-qubit coherence does not establish a two-qubit gate fidelity.",
        "Loaded atom images and 110 potential sites must not be reported as 110 computational qubits."
      ],
      "insight": "Why does atom occupancy imaging require a separate nuclear-spin readout protocol?",
      "fields": {
        "state": {
          "value": "87Sr ground-manifold nuclear spins",
          "locator": "Main text",
          "source": "alt-atom-phoenix"
        },
        "compute": {
          "value": "Site-selective coherent spin rotations",
          "locator": "Fig. 2",
          "source": "alt-atom-phoenix"
        },
        "memory": {
          "value": "21 individually controlled spin qubits",
          "locator": "Register assembly",
          "source": "alt-atom-phoenix"
        },
        "control": {
          "value": "SLM traps and AOD-steered rearrangement",
          "locator": "Fig. 1",
          "source": "alt-atom-phoenix"
        },
        "io": {
          "value": "Shelving plus fluorescence camera images",
          "locator": "Fig. 1",
          "source": "alt-atom-phoenix"
        },
        "software": {
          "value": "Programmable trap geometry and experiment timing",
          "locator": "Fig. 1",
          "source": "alt-atom-phoenix"
        },
        "workload": {
          "value": "Coherent control and memory characterization",
          "locator": "Figs. 2–4",
          "source": "alt-atom-phoenix"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Assemble atoms, manipulate spins, reveal states",
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        "height": 490,
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            "id": "load",
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            "subtitle": "110 SITES",
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            "id": "register",
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          {
            "id": "drive",
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            "id": "shelve",
            "label": "Clock-state shelving",
            "subtitle": "STATE SELECTION",
            "text": "Hides one spin population.",
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            "control": false
          },
          {
            "id": "camera",
            "label": "sCMOS camera",
            "subtitle": "FLUORESCENCE",
            "text": "Resolves individual trap signals.",
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          {
            "id": "analysis",
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            "text": "Uses images and corrections.",
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        ],
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            "label": "",
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            "label": "",
            "source": "alt-atom-phoenix"
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          {
            "from": "register",
            "to": "objective",
            "type": "data",
            "locator": "Fig. 1",
            "label": "fluorescence",
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          {
            "from": "objective",
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            "label": "",
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            "from": "camera",
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            "locator": "Readout discussion",
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          {
            "from": "analysis",
            "to": "aod",
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      "originalCandidate": "Atom Computing neutral-atom systems"
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    {
      "id": "queue-150",
      "name": "QuEra Aquila 1.0",
      "organization": "QuEra",
      "year": 2023,
      "yearLabel": "June 2023 configuration white paper",
      "kind": "Analog quantum simulator",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
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        "quantum"
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        "quantum",
        "analog",
        "hybrid"
      ],
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        "analog-quantum"
      ],
      "substrates": [
        "atomic",
        "photonic"
      ],
      "models": [
        "quantum-simulation",
        "ising"
      ],
      "aliases": [],
      "sources": [
        "alt-aquila"
      ],
      "summary": "Configurable rubidium positions set interactions while global laser waveforms drive a ground–Rydberg analog Hamiltonian.",
      "config": "Aquila public analog-mode configuration documented in white paper v1.0, supporting up to 256 atoms.",
      "gaps": [
        "Analog Rydberg qubits are not the long-lived hyperfine gate-mode qubits discussed as future capabilities.",
        "No arbitrary-graph connectivity or error-corrected logical qubit count is inferred from atom capacity."
      ],
      "insight": "How do geometry, drive and destructive readout jointly define a computation?",
      "fields": {
        "state": {
          "value": "87Rb ground / 70S Rydberg states",
          "locator": "§1.2",
          "source": "alt-aquila"
        },
        "compute": {
          "value": "Coherent interacting Hamiltonian evolution",
          "locator": "§1.3",
          "source": "alt-aquila"
        },
        "memory": {
          "value": "Atomic state during each analog shot",
          "locator": "§1.2",
          "source": "alt-aquila"
        },
        "control": {
          "value": "Trap geometry and global drive waveforms",
          "locator": "Figs. 1.2–1.5",
          "source": "alt-aquila"
        },
        "io": {
          "value": "Recapture and fluorescence occupancy imaging",
          "locator": "§1.2",
          "source": "alt-aquila"
        },
        "software": {
          "value": "Amazon Braket SDK / notebooks",
          "locator": "Introduction",
          "source": "alt-aquila"
        },
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          "value": "Quantum dynamics and independent-set experiments",
          "locator": "§§2–6",
          "source": "alt-aquila"
        }
      },
      "researchDepth": "architecture-dossier",
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        "title": "Geometry and pulses program a quantum evolution",
        "scope": "Optical preparation and terminal readout from the white paper. Presence/absence records require interpretation and are affected by loss.",
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        "height": 490,
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          {
            "id": "geometry",
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            "subtitle": "CLASSICAL INPUT",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-aquila",
            "locator": "§1.2",
            "control": false
          },
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            "id": "slm",
            "label": "SLM trap light",
            "subtitle": "STATIC ARRAY",
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            "y": 35,
            "w": 160,
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          },
          {
            "id": "aod",
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            "w": 160,
            "h": 62,
            "source": "alt-aquila",
            "locator": "Fig. 1.2",
            "control": false
          },
          {
            "id": "atoms",
            "label": "Rubidium array",
            "subtitle": "UP TO 256",
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            "y": 35,
            "w": 160,
            "h": 62,
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            "locator": "§1.2",
            "control": false
          },
          {
            "id": "pulse",
            "label": "Two-photon laser drive",
            "subtitle": "GLOBAL WAVEFORMS",
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            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
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            "locator": "§1.3",
            "control": false
          },
          {
            "id": "interact",
            "label": "Rydberg interactions",
            "subtitle": "DISTANCE DEPENDENT",
            "text": "Couples excited atoms.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-aquila",
            "locator": "§1.3",
            "control": false
          },
          {
            "id": "recapture",
            "label": "Trap restoration",
            "subtitle": "TERMINAL MEASUREMENT",
            "text": "Retains ground-state atoms.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-aquila",
            "locator": "§1.2",
            "control": false
          },
          {
            "id": "camera",
            "label": "Fluorescence camera",
            "subtitle": "OCCUPANCY IMAGE",
            "text": "Records retained atoms.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-aquila",
            "locator": "§1.2",
            "control": false
          },
          {
            "id": "host",
            "label": "Braket / analysis",
            "subtitle": "CLASSICAL",
            "text": "Collects shot outcomes.",
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            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-aquila",
            "locator": "Introduction; §6",
            "control": false
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            "from": "slm",
            "to": "atoms",
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          {
            "from": "host",
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            "label": "",
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          {
            "from": "pulse",
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            "label": "",
            "source": "alt-aquila"
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          {
            "from": "atoms",
            "to": "interact",
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            "label": "",
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          {
            "from": "interact",
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          {
            "from": "atoms",
            "to": "recapture",
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          {
            "from": "recapture",
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            "source": "alt-aquila"
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          {
            "from": "camera",
            "to": "host",
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            "label": "",
            "source": "alt-aquila"
          },
          {
            "from": "host",
            "to": "geometry",
            "type": "control",
            "locator": "Introduction",
            "label": "",
            "source": "alt-aquila"
          }
        ]
      },
      "originalCandidate": "QuEra Aquila"
    },
    {
      "id": "queue-151",
      "name": "Pasqal Orion Alpha cloud configuration",
      "organization": "Pasqal",
      "year": 2025,
      "yearLabel": "2025 cloud brochure configuration",
      "kind": "Analog quantum simulator",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "analog",
        "hybrid"
      ],
      "architectures": [
        "analog-quantum"
      ],
      "substrates": [
        "atomic",
        "photonic"
      ],
      "models": [
        "quantum-simulation"
      ],
      "aliases": [],
      "sources": [
        "alt-pasqal-orion",
        "alt-pulser"
      ],
      "summary": "An analog rubidium QPU accepts constrained two-dimensional atom layouts and pulse sequences through a cloud interface.",
      "config": "Orion Alpha (formerly Fresnel), up to 100 cloud-accessible qubits; 2D layouts and 6 µs maximum sequence in the cited brochure.",
      "gaps": [
        "A general Pulser digital-gate example is not proof that this analog cloud configuration exposes digital gates.",
        "Maximum traps, maximum loaded computational atoms and geometry filling limits are different quantities."
      ],
      "insight": "Which program choices must be validated against physical device constraints?",
      "fields": {
        "state": {
          "value": "87Rb ground–Rydberg basis",
          "locator": "p. 25",
          "source": "alt-pasqal-orion"
        },
        "compute": {
          "value": "Analog driven interacting atoms",
          "locator": "§2.2",
          "source": "alt-pulser"
        },
        "memory": {
          "value": "Atomic register during a pulse sequence",
          "locator": "§2",
          "source": "alt-pulser"
        },
        "control": {
          "value": "Amplitude, detuning and phase pulses",
          "locator": "§2.1",
          "source": "alt-pulser"
        },
        "io": {
          "value": "Cloud submission",
          "locator": "p. 4",
          "source": "alt-pasqal-orion"
        },
        "software": {
          "value": "Pulser register, device and sequence objects",
          "locator": "§3.1; Fig. 5",
          "source": "alt-pulser"
        },
        "workload": {
          "value": "Analog quantum simulation / optimization",
          "locator": "pp. 8–9",
          "source": "alt-pasqal-orion"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "A constrained register plus a pulse schedule",
        "scope": "Program-to-hardware boundary. Software simulation is a separate execution target and does not establish hardware capability.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "reg",
            "label": "Register coordinates",
            "subtitle": "2D LAYOUT",
            "text": "Defines atom positions.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-pulser",
            "locator": "§3.1",
            "control": false
          },
          {
            "id": "device",
            "label": "Device constraints",
            "subtitle": "ORION ALPHA",
            "text": "Checks geometry and pulse limits.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-pasqal-orion",
            "locator": "p. 25",
            "control": false
          },
          {
            "id": "pulse",
            "label": "Pulse waveforms",
            "subtitle": "AMPLITUDE / DETUNING",
            "text": "Defines laser controls.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-pulser",
            "locator": "§3.1",
            "control": false
          },
          {
            "id": "seq",
            "label": "Pulser sequence",
            "subtitle": "SCHEDULE",
            "text": "Combines register and pulses.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-pulser",
            "locator": "Fig. 5",
            "control": false
          },
          {
            "id": "cloud",
            "label": "Cloud execution",
            "subtitle": "HARDWARE TARGET",
            "text": "Submits to the QPU.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-pasqal-orion",
            "locator": "p. 4",
            "control": false
          },
          {
            "id": "traps",
            "label": "Optical trap array",
            "subtitle": "RUBIDIUM ATOMS",
            "text": "Holds the atomic register.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-pasqal-orion",
            "locator": "p. 25",
            "control": false
          },
          {
            "id": "evolve",
            "label": "Rydberg evolution",
            "subtitle": "ANALOG DYNAMICS",
            "text": "Applies driven interactions.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-pulser",
            "locator": "§2.2",
            "control": false
          },
          {
            "id": "measure",
            "label": "Terminal imaging",
            "subtitle": "READOUT",
            "text": "Maps atomic states to outcomes.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-pulser",
            "locator": "§2.4",
            "control": false
          },
          {
            "id": "result",
            "label": "Classical samples",
            "subtitle": "OUTPUT",
            "text": "Collects measurement records.",
            "x": 30,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-pasqal-orion",
            "locator": "p. 4",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "reg",
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            "locator": "Fig. 5",
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            "source": "alt-pulser"
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          {
            "from": "pulse",
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            "label": "",
            "source": "alt-pulser"
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            "from": "device",
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          },
          {
            "from": "seq",
            "to": "cloud",
            "type": "control",
            "locator": "p. 4",
            "label": "",
            "source": "alt-pasqal-orion"
          },
          {
            "from": "cloud",
            "to": "traps",
            "type": "control",
            "locator": "p. 25",
            "label": "",
            "source": "alt-pasqal-orion"
          },
          {
            "from": "traps",
            "to": "evolve",
            "type": "association",
            "locator": "§2.2",
            "label": "",
            "source": "alt-pulser"
          },
          {
            "from": "seq",
            "to": "evolve",
            "type": "control",
            "locator": "§2.1",
            "label": "",
            "source": "alt-pulser"
          },
          {
            "from": "evolve",
            "to": "measure",
            "type": "data",
            "locator": "§2.4",
            "label": "",
            "source": "alt-pulser"
          },
          {
            "from": "measure",
            "to": "result",
            "type": "data",
            "locator": "§2.4",
            "label": "",
            "source": "alt-pulser"
          }
        ]
      },
      "originalCandidate": "Pasqal neutral-atom simulators"
    },
    {
      "id": "queue-152",
      "name": "D-Wave 2000Q LN study configuration",
      "organization": "D-Wave",
      "year": 2021,
      "yearLabel": "2021 comparative study configuration",
      "kind": "Quantum annealing system",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
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        "quantum",
        "analog",
        "hybrid"
      ],
      "architectures": [
        "annealer"
      ],
      "substrates": [
        "superconducting"
      ],
      "models": [
        "quantum-annealing",
        "ising"
      ],
      "aliases": [],
      "sources": [
        "alt-dwave-2021",
        "alt-dwave-topology",
        "alt-dwave-workflow",
        "alt-dwave-anneal"
      ],
      "summary": "A Chimera-connected superconducting annealer receives an embedded Ising objective and returns sampled spin assignments.",
      "config": "The lower-noise 2000Q used in the 2021 report’s 3D-lattice study; footnote 3 reports 2,041 operable qubits. Other study embeddings use different subgraphs.",
      "gaps": [
        "Chimera C16 ideal capacity and the study’s usable qubit/subgraph counts must remain distinct.",
        "A low-energy sample is not a guarantee of a global optimum."
      ],
      "insight": "Why do physical qubits outnumber logical problem variables?",
      "fields": {
        "state": {
          "value": "Flux-qubit spin variables",
          "locator": "QA Implementation",
          "source": "alt-dwave-anneal"
        },
        "compute": {
          "value": "Transverse-field annealing",
          "locator": "QA Implementation",
          "source": "alt-dwave-anneal"
        },
        "memory": {
          "value": "Qubit configuration within each anneal",
          "locator": "§2.1",
          "source": "alt-dwave-workflow"
        },
        "control": {
          "value": "h/J programming plus anneal schedule",
          "locator": "§2.2",
          "source": "alt-dwave-workflow"
        },
        "io": {
          "value": "Repeated spin samples",
          "locator": "§2.3",
          "source": "alt-dwave-workflow"
        },
        "software": {
          "value": "Ising/QUBO translation and minor embedding",
          "locator": "§2.3",
          "source": "alt-dwave-workflow"
        },
        "workload": {
          "value": "Embedded optimization / spin-glass studies",
          "locator": "§3.2",
          "source": "alt-dwave-2021"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Embedding into Chimera, then reading spin samples",
        "scope": "One K4,4 unit-cell motif and external couplings are aggregated; not every ideal cell qubit is operational.",
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        "height": 490,
        "nodes": [
          {
            "id": "logical",
            "label": "Logical Ising graph",
            "subtitle": "CLASSICAL OBJECTIVE",
            "text": "Defines h and J.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-workflow",
            "locator": "§2.3",
            "control": false
          },
          {
            "id": "embed",
            "label": "Minor embedding",
            "subtitle": "CHAINS",
            "text": "Maps variables to physical qubits.",
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            "source": "alt-dwave-2021",
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          },
          {
            "id": "qmi",
            "label": "QMI programming",
            "subtitle": "CONTROL",
            "text": "Loads coefficients and schedule.",
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            "source": "alt-dwave-workflow",
            "locator": "§2.2",
            "control": false
          },
          {
            "id": "horizontal",
            "label": "Horizontal group",
            "subtitle": "4 QUBITS / CELL",
            "text": "One partition of K4,4.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-topology",
            "locator": "Unit Cells",
            "control": false
          },
          {
            "id": "vertical",
            "label": "Vertical group",
            "subtitle": "4 QUBITS / CELL",
            "text": "Other partition of K4,4.",
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            "h": 62,
            "source": "alt-dwave-topology",
            "locator": "Unit Cells",
            "control": false
          },
          {
            "id": "external",
            "label": "Adjacent cells",
            "subtitle": "COLINEAR LINKS",
            "text": "Extends the Chimera lattice.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-topology",
            "locator": "External couplers",
            "control": false
          },
          {
            "id": "anneal",
            "label": "Annealing evolution",
            "subtitle": "QUANTUM DYNAMICS",
            "text": "Changes transverse/problem weights.",
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            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-anneal",
            "locator": "QA Implementation",
            "control": false
          },
          {
            "id": "samples",
            "label": "Spin samples",
            "subtitle": "READOUT",
            "text": "Returns physical assignments.",
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            "y": 375,
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            "h": 62,
            "source": "alt-dwave-workflow",
            "locator": "§2.3",
            "control": false
          },
          {
            "id": "unembed",
            "label": "Chain resolution",
            "subtitle": "CLASSICAL",
            "text": "Interprets logical solutions.",
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            "source": "alt-dwave-workflow",
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            "control": false
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        ],
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          {
            "from": "logical",
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          {
            "from": "embed",
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          },
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            "from": "qmi",
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          {
            "from": "qmi",
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            "locator": "§2.2",
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            "source": "alt-dwave-workflow"
          },
          {
            "from": "horizontal",
            "to": "vertical",
            "type": "association",
            "locator": "Internal couplers",
            "label": "K4,4",
            "source": "alt-dwave-topology"
          },
          {
            "from": "horizontal",
            "to": "external",
            "type": "association",
            "locator": "External couplers",
            "label": "",
            "source": "alt-dwave-topology"
          },
          {
            "from": "vertical",
            "to": "external",
            "type": "association",
            "locator": "External couplers",
            "label": "",
            "source": "alt-dwave-topology"
          },
          {
            "from": "qmi",
            "to": "anneal",
            "type": "control",
            "locator": "QA Implementation",
            "label": "",
            "source": "alt-dwave-anneal"
          },
          {
            "from": "anneal",
            "to": "samples",
            "type": "data",
            "locator": "§2.3",
            "label": "",
            "source": "alt-dwave-workflow"
          },
          {
            "from": "samples",
            "to": "unembed",
            "type": "data",
            "locator": "§2.3",
            "label": "",
            "source": "alt-dwave-workflow"
          }
        ]
      },
      "originalCandidate": "D-Wave 2000Q"
    },
    {
      "id": "queue-153",
      "name": "D-Wave Advantage 4.1",
      "organization": "D-Wave",
      "year": 2021,
      "yearLabel": "October 2021 performance update",
      "kind": "Quantum annealing system",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "analog",
        "hybrid"
      ],
      "architectures": [
        "annealer"
      ],
      "substrates": [
        "superconducting"
      ],
      "models": [
        "quantum-annealing",
        "ising"
      ],
      "aliases": [],
      "sources": [
        "alt-dwave-2021",
        "alt-dwave-topology",
        "alt-dwave-workflow",
        "alt-dwave-anneal"
      ],
      "summary": "Pegasus adds coupling choices that can reduce embedding-chain overhead in an annealing workflow.",
      "config": "Advantage 4.1 in the October 2021 report; its 3D-lattice study reports 5,627 operable qubits. This is not Advantage2.",
      "gaps": [
        "The degree-15 Pegasus pattern does not mean all physical qubits have 15 usable neighbors.",
        "The reported experiments do not establish a general speedup for all optimization problems."
      ],
      "insight": "How does additional connectivity change chain length and coefficient scaling?",
      "fields": {
        "state": {
          "value": "Superconducting flux-qubit variables",
          "locator": "QA Implementation",
          "source": "alt-dwave-anneal"
        },
        "compute": {
          "value": "Programmable quantum annealing",
          "locator": "QA Implementation",
          "source": "alt-dwave-anneal"
        },
        "memory": {
          "value": "Embedded physical spin state",
          "locator": "§2.1",
          "source": "alt-dwave-2021"
        },
        "control": {
          "value": "Local h/J DAC settings and global schedule",
          "locator": "QA Implementation",
          "source": "alt-dwave-anneal"
        },
        "io": {
          "value": "Physical-qubit sample batches",
          "locator": "§3.2",
          "source": "alt-dwave-2021"
        },
        "software": {
          "value": "Ocean embedding and chain postprocessing",
          "locator": "§§2.1–3.1",
          "source": "alt-dwave-2021"
        },
        "workload": {
          "value": "Clique, NAE3SAT and 3D-lattice studies",
          "locator": "§3.2",
          "source": "alt-dwave-2021"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Pegasus couplers within the annealing workflow",
        "scope": "Coupler categories are a topology motif, not an exhaustive live solver graph. Analog controls and classical unembedding are outside the quantum evolution.",
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        "height": 490,
        "nodes": [
          {
            "id": "input",
            "label": "Logical objective",
            "subtitle": "CLASSICAL",
            "text": "Provides problem weights.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-2021",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "embed",
            "label": "Ocean embedding",
            "subtitle": "CHAIN STRENGTH",
            "text": "Fits the active graph.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-2021",
            "locator": "§2.1–2.3",
            "control": false
          },
          {
            "id": "dac",
            "label": "Qubit / coupler DACs",
            "subtitle": "COEFFICIENT CONTROL",
            "text": "Programs h and J.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-anneal",
            "locator": "QA Implementation",
            "control": false
          },
          {
            "id": "q",
            "label": "Pegasus qubit",
            "subtitle": "PHYSICAL SPIN",
            "text": "Participates in the anneal.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-topology",
            "locator": "Pegasus Graph",
            "control": false
          },
          {
            "id": "internal",
            "label": "Internal couplers",
            "subtitle": "ORTHOGONAL",
            "text": "Connects up to 12 neighbors.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-topology",
            "locator": "Pegasus: Internal couplers",
            "control": false
          },
          {
            "id": "odd",
            "label": "Odd coupler",
            "subtitle": "PARALLEL PAIR",
            "text": "Adds same-orientation coupling.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-topology",
            "locator": "Pegasus: Odd couplers",
            "control": false
          },
          {
            "id": "external",
            "label": "External couplers",
            "subtitle": "ADJACENT",
            "text": "Extends parallel connections.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-topology",
            "locator": "Pegasus: External couplers",
            "control": false
          },
          {
            "id": "schedule",
            "label": "Anneal waveform",
            "subtitle": "A(s), B(s)",
            "text": "Controls Hamiltonian evolution.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-anneal",
            "locator": "QA Implementation",
            "control": false
          },
          {
            "id": "read",
            "label": "Samples / chain repair",
            "subtitle": "CLASSICAL OUTPUT",
            "text": "Resolves physical assignments.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-dwave-2021",
            "locator": "§3.1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "input",
            "to": "embed",
            "type": "data",
            "locator": "§2.1",
            "label": "",
            "source": "alt-dwave-2021"
          },
          {
            "from": "embed",
            "to": "dac",
            "type": "control",
            "locator": "§2.3",
            "label": "",
            "source": "alt-dwave-2021"
          },
          {
            "from": "dac",
            "to": "q",
            "type": "control",
            "locator": "QA Implementation",
            "label": "",
            "source": "alt-dwave-anneal"
          },
          {
            "from": "dac",
            "to": "internal",
            "type": "control",
            "locator": "QA Implementation",
            "label": "",
            "source": "alt-dwave-anneal"
          },
          {
            "from": "q",
            "to": "internal",
            "type": "association",
            "locator": "Pegasus: Internal couplers",
            "label": "",
            "source": "alt-dwave-topology"
          },
          {
            "from": "q",
            "to": "odd",
            "type": "association",
            "locator": "Pegasus: Odd couplers",
            "label": "",
            "source": "alt-dwave-topology"
          },
          {
            "from": "q",
            "to": "external",
            "type": "association",
            "locator": "Pegasus: External couplers",
            "label": "",
            "source": "alt-dwave-topology"
          },
          {
            "from": "schedule",
            "to": "q",
            "type": "control",
            "locator": "QA Implementation",
            "label": "",
            "source": "alt-dwave-anneal"
          },
          {
            "from": "q",
            "to": "read",
            "type": "data",
            "locator": "§3.1",
            "label": "",
            "source": "alt-dwave-2021"
          },
          {
            "from": "embed",
            "to": "read",
            "type": "association",
            "locator": "§2.3",
            "label": "chain interpretation",
            "source": "alt-dwave-2021"
          }
        ]
      },
      "originalCandidate": "D-Wave Advantage"
    },
    {
      "id": "queue-154",
      "name": "Xanadu Borealis (216-mode experiment)",
      "organization": "Xanadu / NIST",
      "year": 2022,
      "yearLabel": "2022 sampling experiment",
      "kind": "Photonic quantum sampling experiment",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "optical",
        "hybrid"
      ],
      "architectures": [
        "optical-linear"
      ],
      "substrates": [
        "photonic"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-borealis"
      ],
      "summary": "A pulse train traverses three programmable delay-loop interferometers before photon-number-resolving detection.",
      "config": "216-mode Gaussian boson sampling experiment in Madsen et al.; not a universal fault-tolerant quantum computer.",
      "gaps": [
        "Programmable implemented gates do not make this interferometer universal over every possible mode transformation.",
        "Sampling validation and historical classical-runtime estimates have explicit model and loss assumptions."
      ],
      "insight": "How can three fiber delays connect a much larger set of temporal modes?",
      "fields": {
        "state": {
          "value": "216 squeezed temporal modes",
          "locator": "Abstract; Fig. 1",
          "source": "alt-borealis"
        },
        "compute": {
          "value": "Three variable-beamsplitter interferometers",
          "locator": "Experiment",
          "source": "alt-borealis"
        },
        "memory": {
          "value": "Fiber delays buffer optical modes",
          "locator": "Experiment",
          "source": "alt-borealis"
        },
        "control": {
          "value": "Programmable phase and beamsplitter settings",
          "locator": "Fig. 1",
          "source": "alt-borealis"
        },
        "io": {
          "value": "1-to-16 demultiplexing and PNR detectors",
          "locator": "Fig. 1",
          "source": "alt-borealis"
        },
        "software": {
          "value": "Classical quantum-program parameters and validation",
          "locator": "Experiment",
          "source": "alt-borealis"
        },
        "workload": {
          "value": "Gaussian boson sampling",
          "locator": "Abstract",
          "source": "alt-borealis"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Three loop stages create temporal-mode connectivity",
        "scope": "Each loop block includes its VBS, phase shifter and fiber delay; τ, 6τ and 36τ identify mode separations.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "program",
            "label": "Gate parameters",
            "subtitle": "CLASSICAL CONTROL",
            "text": "Sets phases and splitting.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-borealis",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "opo",
            "label": "Pulsed OPO",
            "subtitle": "SQUEEZED LIGHT",
            "text": "Generates a pulse train.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-borealis",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "loop1",
            "label": "Loop τ",
            "subtitle": "ADJACENT MODES",
            "text": "Mixes neighboring bins.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-borealis",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "loop6",
            "label": "Loop 6τ",
            "subtitle": "SEPARATED MODES",
            "text": "Adds longer-range mixing.",
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            "y": 35,
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            "h": 62,
            "source": "alt-borealis",
            "locator": "Fig. 1",
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          },
          {
            "id": "loop36",
            "label": "Loop 36τ",
            "subtitle": "SEPARATED MODES",
            "text": "Adds third connectivity scale.",
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            "source": "alt-borealis",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "demux",
            "label": "1-to-16 switch tree",
            "subtitle": "DEMULTIPLEXING",
            "text": "Spreads output for detection.",
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            "y": 205,
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            "h": 62,
            "source": "alt-borealis",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "pnr",
            "label": "PNR detectors",
            "subtitle": "PHOTON COUNTS",
            "text": "Resolves photon numbers.",
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            "y": 205,
            "w": 160,
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            "source": "alt-borealis",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "sample",
            "label": "216-number record",
            "subtitle": "CLASSICAL SAMPLE",
            "text": "Collects one sampled pattern.",
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            "from": "loop1",
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          {
            "from": "loop36",
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          },
          {
            "from": "demux",
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            "label": "",
            "source": "alt-borealis"
          },
          {
            "from": "pnr",
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            "source": "alt-borealis"
          },
          {
            "from": "program",
            "to": "loop1",
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            "locator": "Fig. 1",
            "label": "",
            "source": "alt-borealis"
          },
          {
            "from": "program",
            "to": "loop6",
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            "locator": "Fig. 1",
            "label": "",
            "source": "alt-borealis"
          },
          {
            "from": "program",
            "to": "loop36",
            "type": "control",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-borealis"
          },
          {
            "from": "program",
            "to": "opo",
            "type": "control",
            "locator": "Experiment",
            "label": "squeezing",
            "source": "alt-borealis"
          }
        ]
      },
      "originalCandidate": "Xanadu Borealis"
    },
    {
      "id": "queue-155",
      "name": "USTC Jiuzhang original GBS experiment",
      "organization": "USTC / CAS / Tsinghua",
      "year": 2020,
      "yearLabel": "2020 sampling experiment",
      "kind": "Photonic quantum sampling experiment",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "optical",
        "hybrid"
      ],
      "architectures": [
        "optical-linear"
      ],
      "substrates": [
        "photonic"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-jiuzhang"
      ],
      "summary": "Squeezed-state sources feed a fixed random interferometer whose outputs are threshold-detected.",
      "config": "Original 2020 100-mode experiment: 25 two-mode sources equivalent to 50 squeezed inputs, with 100 single-photon detectors.",
      "gaps": [
        "A 76-click event is not a 76-qubit universal quantum computation.",
        "The fixed interferometer and sampling task are distinct from general programmable fault-tolerant photonic computing."
      ],
      "insight": "Why are optical phase locking and photon indistinguishability computational requirements?",
      "fields": {
        "state": {
          "value": "Squeezed optical states",
          "locator": "Fig. 1",
          "source": "alt-jiuzhang"
        },
        "compute": {
          "value": "Fixed random 100-mode interference",
          "locator": "Fig. 1",
          "source": "alt-jiuzhang"
        },
        "memory": {
          "value": "Propagating optical quantum state",
          "locator": "Main text",
          "source": "alt-jiuzhang"
        },
        "control": {
          "value": "Active source-path locking; passive interferometer stability",
          "locator": "Fig. 3",
          "source": "alt-jiuzhang"
        },
        "io": {
          "value": "100 threshold detector channels",
          "locator": "Fig. 1",
          "source": "alt-jiuzhang"
        },
        "software": {
          "value": "Transfer-matrix characterization and sample validation",
          "locator": "Figs. 4–5",
          "source": "alt-jiuzhang"
        },
        "workload": {
          "value": "Gaussian boson sampling",
          "locator": "Abstract",
          "source": "alt-jiuzhang"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Source coherence through fixed interference to clicks",
        "scope": "The phase-monitoring branch is classical feedback; threshold clicks do not measure exact photon number.",
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        "height": 490,
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          {
            "id": "pump",
            "label": "Shaped pump laser",
            "subtitle": "250 kHz",
            "text": "Drives nonlinear sources.",
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            "w": 160,
            "h": 62,
            "source": "alt-jiuzhang",
            "locator": "Source-design paragraphs",
            "control": false
          },
          {
            "id": "ppktp",
            "label": "25 PPKTP sources",
            "subtitle": "TWO-MODE SQUEEZING",
            "text": "Generates quantum light.",
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            "control": false
          },
          {
            "id": "collect",
            "label": "Filtering / fibers",
            "subtitle": "MODE MATCHING",
            "text": "Collects indistinguishable inputs.",
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            "control": false
          },
          {
            "id": "interf",
            "label": "100-mode interferometer",
            "subtitle": "FIXED RANDOM MATRIX",
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            "control": false
          },
          {
            "id": "detector",
            "label": "100 photon detectors",
            "subtitle": "THRESHOLD OUTPUT",
            "text": "Records clicks.",
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          {
            "id": "record",
            "label": "Click patterns",
            "subtitle": "CLASSICAL DATA",
            "text": "Collects output samples.",
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          },
          {
            "id": "monitor",
            "label": "Balanced phase monitor",
            "subtitle": "REFERENCE BRANCH",
            "text": "Senses path-phase drift.",
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            "source": "alt-jiuzhang",
            "locator": "Fig. 3A",
            "control": false
          },
          {
            "id": "piezo",
            "label": "Fiber piezo actuator",
            "subtitle": "PHASE FEEDBACK",
            "text": "Corrects optical path length.",
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            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-jiuzhang",
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            "control": false
          },
          {
            "id": "validate",
            "label": "Sample validation",
            "subtitle": "CLASSICAL ANALYSIS",
            "text": "Tests alternative hypotheses.",
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            "y": 375,
            "w": 160,
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            "source": "alt-jiuzhang",
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        ],
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          {
            "from": "ppktp",
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          {
            "from": "collect",
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          {
            "from": "interf",
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          {
            "from": "detector",
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            "source": "alt-jiuzhang"
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          {
            "from": "record",
            "to": "validate",
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            "locator": "Figs. 4–5",
            "label": "",
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          },
          {
            "from": "pump",
            "to": "monitor",
            "type": "data",
            "locator": "Fig. 3A",
            "label": "phase reference",
            "source": "alt-jiuzhang"
          },
          {
            "from": "collect",
            "to": "monitor",
            "type": "data",
            "locator": "Fig. 3A",
            "label": "shared-path reference",
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          },
          {
            "from": "monitor",
            "to": "piezo",
            "type": "control",
            "locator": "Fig. 3A",
            "label": "",
            "source": "alt-jiuzhang"
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          {
            "from": "piezo",
            "to": "collect",
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          }
        ]
      },
      "originalCandidate": "USTC Jiuzhang"
    },
    {
      "id": "queue-156",
      "name": "USTC Zuchongzhi 2021 processor",
      "organization": "USTC and collaborators",
      "year": 2021,
      "yearLabel": "June 2021 sampling manuscript",
      "kind": "Quantum research processor",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "hybrid"
      ],
      "architectures": [
        "gate-quantum"
      ],
      "substrates": [
        "superconducting"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-zuchongzhi"
      ],
      "summary": "A flip-chip transmon processor separates the qubit/coupler die from control and readout wiring.",
      "config": "Original 66-qubit, 110-coupler processor; random circuits used a selected 56-qubit subset and up to 20 cycles.",
      "gaps": [
        "This record does not import the later Zuchongzhi 2.1 60-qubit sampling configuration.",
        "Historical estimated classical runtimes are not current benchmark rankings."
      ],
      "insight": "How do tunable couplers and multiplexed measurement support parallel circuit layers?",
      "fields": {
        "state": {
          "value": "Transmon ground/excited states",
          "locator": "§II",
          "source": "alt-zuchongzhi"
        },
        "compute": {
          "value": "Microwave rotations and iSWAP-like gates",
          "locator": "§II",
          "source": "alt-zuchongzhi"
        },
        "memory": {
          "value": "Selected coherent qubit register",
          "locator": "§II",
          "source": "alt-zuchongzhi"
        },
        "control": {
          "value": "Microwave drive plus qubit/coupler flux lines",
          "locator": "§II",
          "source": "alt-zuchongzhi"
        },
        "io": {
          "value": "Resonators with six-qubit Purcell-filter groups",
          "locator": "§II",
          "source": "alt-zuchongzhi"
        },
        "software": {
          "value": "Frequency optimization and parallel XEB",
          "locator": "§II",
          "source": "alt-zuchongzhi"
        },
        "workload": {
          "value": "Random circuit sampling",
          "locator": "Abstract",
          "source": "alt-zuchongzhi"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Two bonded sapphire dies and their signal paths",
        "scope": "Functional hierarchy of Fig. 1, not a complete 66-site layout; 56 sampled qubits are a subset, not failed-qubit yield.",
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        "height": 490,
        "nodes": [
          {
            "id": "room",
            "label": "Room-temperature control",
            "subtitle": "CLASSICAL",
            "text": "Generates drive and bias signals.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-zuchongzhi",
            "locator": "§II",
            "control": false
          },
          {
            "id": "wire",
            "label": "Cryogenic wiring",
            "subtitle": "SIGNAL CONDITIONING",
            "text": "Connects the package.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-zuchongzhi",
            "locator": "§II",
            "control": false
          },
          {
            "id": "interface",
            "label": "Control / readout die",
            "subtitle": "SAPPHIRE",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-zuchongzhi",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "bumps",
            "label": "Indium bonds",
            "subtitle": "FLIP-CHIP",
            "text": "Joins the two dies.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-zuchongzhi",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "qubits",
            "label": "66 transmons",
            "subtitle": "QUANTUM DIE",
            "text": "Stores qubit states.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-zuchongzhi",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "couple",
            "label": "110 tunable couplers",
            "subtitle": "NEAREST NEIGHBORS",
            "text": "Controls pair interactions.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-zuchongzhi",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "res",
            "label": "Readout resonators",
            "subtitle": "DISPERSIVE",
            "text": "Maps state to microwave signals.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-zuchongzhi",
            "locator": "§II",
            "control": false
          },
          {
            "id": "purcell",
            "label": "Shared Purcell filters",
            "subtitle": "SIX-QUBIT GROUPS",
            "text": "Enables multiplexed readout.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-zuchongzhi",
            "locator": "§II",
            "control": false
          },
          {
            "id": "xeb",
            "label": "Sampling / XEB analysis",
            "subtitle": "CLASSICAL",
            "text": "Collects and checks circuit data.",
            "x": 30,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-zuchongzhi",
            "locator": "§II",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "room",
            "to": "wire",
            "type": "control",
            "locator": "§II",
            "label": "",
            "source": "alt-zuchongzhi"
          },
          {
            "from": "wire",
            "to": "interface",
            "type": "control",
            "locator": "§II",
            "label": "",
            "source": "alt-zuchongzhi"
          },
          {
            "from": "interface",
            "to": "bumps",
            "type": "association",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-zuchongzhi"
          },
          {
            "from": "bumps",
            "to": "qubits",
            "type": "control",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-zuchongzhi"
          },
          {
            "from": "bumps",
            "to": "couple",
            "type": "control",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-zuchongzhi"
          },
          {
            "from": "qubits",
            "to": "couple",
            "type": "association",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-zuchongzhi"
          },
          {
            "from": "couple",
            "to": "qubits",
            "type": "association",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-zuchongzhi"
          },
          {
            "from": "qubits",
            "to": "res",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-zuchongzhi"
          },
          {
            "from": "res",
            "to": "purcell",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-zuchongzhi"
          },
          {
            "from": "purcell",
            "to": "xeb",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-zuchongzhi"
          },
          {
            "from": "xeb",
            "to": "room",
            "type": "control",
            "locator": "§II",
            "label": "calibration",
            "source": "alt-zuchongzhi"
          }
        ]
      },
      "originalCandidate": "USTC Zuchongzhi"
    },
    {
      "id": "queue-157",
      "name": "Philips six-spin silicon quantum processor",
      "organization": "QuTech / TU Delft / Wisconsin and collaborators",
      "year": 2022,
      "yearLabel": "2022 experimental processor paper",
      "kind": "Semiconductor-spin quantum experiment",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum",
        "hybrid"
      ],
      "architectures": [
        "gate-quantum"
      ],
      "substrates": [
        "integrated",
        "magnetic"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-silicon-six"
      ],
      "summary": "Electrical microwave control rotates spins while barrier pulses enable exchange and spin-to-charge measurement.",
      "config": "Six computational spins in a linear 28Si/SiGe quantum-dot array; middle-spin readout is mapped to outer neighbors.",
      "gaps": [
        "Universal control of six physical spins is not a fault-tolerant logical processor.",
        "Some entangled-state fidelities use readout correction; uncorrected results remain a separate quantity."
      ],
      "insight": "Why are charge sensing and conditional rotations part of the computation boundary?",
      "fields": {
        "state": {
          "value": "Six confined electron-spin qubits",
          "locator": "Main text",
          "source": "alt-silicon-six"
        },
        "compute": {
          "value": "EDSR rotations and neighbor exchange CZ",
          "locator": "Figs. 2–3",
          "source": "alt-silicon-six"
        },
        "memory": {
          "value": "Linear dot spin register",
          "locator": "Fig. 1",
          "source": "alt-silicon-six"
        },
        "control": {
          "value": "AWG gate pulses and IQ-modulated microwaves",
          "locator": "Methods: control setup",
          "source": "alt-silicon-six"
        },
        "io": {
          "value": "PSB parity and QND-mapped inner-spin readout",
          "locator": "Fig. 1",
          "source": "alt-silicon-six"
        },
        "software": {
          "value": "Calibration, pulse library and real-time feedback",
          "locator": "Methods",
          "source": "alt-silicon-six"
        },
        "workload": {
          "value": "Bell / three-spin entanglement and control tests",
          "locator": "Figs. 4–5",
          "source": "alt-silicon-six"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Electrical gates, spin evolution, charge readout",
        "scope": "Functional control/readout dependencies for the six-spin device; no all-to-all exchange graph is implied.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "awg",
            "label": "AWG / IQ control",
            "subtitle": "CLASSICAL PULSES",
            "text": "Shapes electrical drives.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-silicon-six",
            "locator": "Methods: control setup",
            "control": false
          },
          {
            "id": "gate",
            "label": "Plunger / barrier gates",
            "subtitle": "DOT CONTROL",
            "text": "Defines dots and exchange.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-silicon-six",
            "locator": "Fig. 1; Fig. 3",
            "control": false
          },
          {
            "id": "mag",
            "label": "Cobalt micromagnets",
            "subtitle": "FIELD GRADIENT",
            "text": "Enables spin addressing.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-silicon-six",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "spins",
            "label": "Six-spin chain",
            "subtitle": "QUANTUM REGISTER",
            "text": "Hosts coherent spin states.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-silicon-six",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "exchange",
            "label": "Neighbor exchange",
            "subtitle": "BARRIER PULSES",
            "text": "Implements CZ interactions.",
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            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-silicon-six",
            "locator": "Fig. 3",
            "control": false
          },
          {
            "id": "qnd",
            "label": "Conditional mapping",
            "subtitle": "INNER SPINS",
            "text": "Maps middle states outward.",
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            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-silicon-six",
            "locator": "Fig. 1b",
            "control": false
          },
          {
            "id": "psb",
            "label": "PSB parity conversion",
            "subtitle": "OUTER DOT PAIRS",
            "text": "Converts spin to charge signal.",
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            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-silicon-six",
            "locator": "Fig. 1c",
            "control": false
          },
          {
            "id": "sensor",
            "label": "Sensing dots / RF",
            "subtitle": "CLASSICAL SIGNAL",
            "text": "Reads charge differences.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-silicon-six",
            "locator": "Methods: parity mode PSB",
            "control": false
          },
          {
            "id": "feedback",
            "label": "FPGA / calibration",
            "subtitle": "CONDITIONAL CONTROL",
            "text": "Initializes and compensates drift.",
            "x": 30,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-silicon-six",
            "locator": "Fig. 1; Methods",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "awg",
            "to": "gate",
            "type": "control",
            "locator": "Methods: control setup",
            "label": "",
            "source": "alt-silicon-six"
          },
          {
            "from": "awg",
            "to": "spins",
            "type": "control",
            "locator": "Methods: control setup",
            "label": "microwave bursts",
            "source": "alt-silicon-six"
          },
          {
            "from": "mag",
            "to": "spins",
            "type": "association",
            "locator": "Fig. 1",
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          {
            "from": "gate",
            "to": "spins",
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            "label": "",
            "source": "alt-silicon-six"
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          {
            "from": "gate",
            "to": "exchange",
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            "locator": "Fig. 3",
            "label": "",
            "source": "alt-silicon-six"
          },
          {
            "from": "exchange",
            "to": "spins",
            "type": "association",
            "locator": "Fig. 3",
            "label": "",
            "source": "alt-silicon-six"
          },
          {
            "from": "spins",
            "to": "qnd",
            "type": "association",
            "locator": "Fig. 1b",
            "label": "",
            "source": "alt-silicon-six"
          },
          {
            "from": "qnd",
            "to": "psb",
            "type": "data",
            "locator": "Fig. 1e",
            "label": "",
            "source": "alt-silicon-six"
          },
          {
            "from": "psb",
            "to": "sensor",
            "type": "data",
            "locator": "Methods: parity mode PSB",
            "label": "",
            "source": "alt-silicon-six"
          },
          {
            "from": "sensor",
            "to": "feedback",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-silicon-six"
          },
          {
            "from": "feedback",
            "to": "awg",
            "type": "control",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-silicon-six"
          }
        ]
      },
      "originalCandidate": "Silicon spin-qubit arrays"
    },
    {
      "id": "queue-158",
      "name": "Kitaev anyon-computation proposal",
      "organization": "Landau Institute",
      "year": 1997,
      "yearLabel": "1997 theoretical preprint",
      "kind": "Theoretical quantum-computing proposal",
      "status": "dossier",
      "track": "quantum",
      "trackName": "Quantum systems & simulation",
      "discoveryParadigms": [
        "quantum"
      ],
      "paradigms": [
        "quantum"
      ],
      "architectures": [
        "gate-quantum",
        "fault-tolerant"
      ],
      "substrates": [],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-kitaev"
      ],
      "summary": "Topological degrees of freedom encode information; creating, braiding and fusing excitations define abstract operations.",
      "config": "Kitaev’s local-Hamiltonian construction, with nonabelian models considered for universal computation; a formal proposal, not built apparatus.",
      "gaps": [
        "Abelian toric-code operations are not automatically a universal gate set.",
        "Theoretical fault-tolerance conditions do not certify an experimentally realized device."
      ],
      "insight": "Why is the toric memory model alone insufficient for the proposed universal gate set?",
      "fields": {
        "state": {
          "value": "Degenerate protected subspace / anyon states",
          "locator": "Introduction; §1",
          "source": "alt-kitaev"
        },
        "compute": {
          "value": "Braiding unitary transformations",
          "locator": "Introduction; §7",
          "source": "alt-kitaev"
        },
        "memory": {
          "value": "Nonlocal encoded quantum information",
          "locator": "§1",
          "source": "alt-kitaev"
        },
        "control": {
          "value": "Abstract excitation creation and motion",
          "locator": "Introduction; §7",
          "source": "alt-kitaev"
        },
        "io": {
          "value": "Fusion outcomes",
          "locator": "Introduction",
          "source": "alt-kitaev"
        },
        "software": {
          "value": "Composite-qubit gate construction",
          "locator": "§7",
          "source": "alt-kitaev"
        },
        "workload": {
          "value": "Proposed universal quantum computation",
          "locator": "§7",
          "source": "alt-kitaev"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Abstract anyon operations and measurement boundary",
        "scope": "Logical dependencies in a proposed model; no laser, nanowire, cryostat or demonstrated material implementation is implied.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "ham",
            "label": "Local Hamiltonian",
            "subtitle": "MODEL DEFINITION",
            "text": "Defines the protected system.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-kitaev",
            "locator": "Introduction; §1",
            "control": false
          },
          {
            "id": "space",
            "label": "Protected subspace",
            "subtitle": "ENCODED STATE",
            "text": "Stores nonlocal information.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-kitaev",
            "locator": "§1",
            "control": false
          },
          {
            "id": "pair",
            "label": "Create excitation pairs",
            "subtitle": "ABSTRACT OPERATION",
            "text": "Introduces anyonic degrees.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-kitaev",
            "locator": "Introduction; §7",
            "control": false
          },
          {
            "id": "encode",
            "label": "Composite qubits",
            "subtitle": "NONABELIAN MODEL",
            "text": "Uses several vortex pairs.",
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            "w": 160,
            "h": 62,
            "source": "alt-kitaev",
            "locator": "§7",
            "control": false
          },
          {
            "id": "braid",
            "label": "Braid worldlines",
            "subtitle": "UNITARY ACTION",
            "text": "Moves excitations around others.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-kitaev",
            "locator": "Introduction; §7",
            "control": false
          },
          {
            "id": "fuse",
            "label": "Fuse selected pairs",
            "subtitle": "MEASUREMENT",
            "text": "Combines excitations.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-kitaev",
            "locator": "Introduction",
            "control": false
          },
          {
            "id": "outcome",
            "label": "Fusion result",
            "subtitle": "CLASSICAL OUTCOME",
            "text": "Reveals an allowed channel.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-kitaev",
            "locator": "Introduction",
            "control": false
          },
          {
            "id": "reference",
            "label": "Reference pair states",
            "subtitle": "MODEL RESOURCE",
            "text": "Supports state preparation.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-kitaev",
            "locator": "§7",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "ham",
            "to": "space",
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          {
            "from": "space",
            "to": "pair",
            "type": "association",
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            "label": "",
            "source": "alt-kitaev"
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          {
            "from": "pair",
            "to": "encode",
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            "label": "",
            "source": "alt-kitaev"
          },
          {
            "from": "encode",
            "to": "braid",
            "type": "association",
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            "label": "",
            "source": "alt-kitaev"
          },
          {
            "from": "braid",
            "to": "encode",
            "type": "association",
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            "label": "",
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          },
          {
            "from": "encode",
            "to": "fuse",
            "type": "association",
            "locator": "Introduction",
            "label": "",
            "source": "alt-kitaev"
          },
          {
            "from": "fuse",
            "to": "outcome",
            "type": "data",
            "locator": "Introduction",
            "label": "",
            "source": "alt-kitaev"
          },
          {
            "from": "outcome",
            "to": "reference",
            "type": "control",
            "locator": "§7",
            "label": "",
            "source": "alt-kitaev"
          },
          {
            "from": "reference",
            "to": "pair",
            "type": "control",
            "locator": "§7",
            "label": "",
            "source": "alt-kitaev"
          },
          {
            "from": "ham",
            "to": "braid",
            "type": "association",
            "locator": "Introduction",
            "label": "topological protection conditions",
            "source": "alt-kitaev"
          }
        ]
      },
      "originalCandidate": "Topological quantum proposals"
    },
    {
      "id": "queue-159",
      "name": "LightOn Appliance OPU",
      "organization": "LightOn",
      "year": 2021,
      "yearLabel": "March 2021 appliance reference",
      "kind": "Optical coprocessor system",
      "status": "dossier",
      "track": "light",
      "trackName": "Photonic processors",
      "discoveryParadigms": [
        "optical",
        "analog"
      ],
      "paradigms": [
        "analog",
        "optical",
        "hybrid"
      ],
      "architectures": [
        "optical-linear",
        "heterogeneous"
      ],
      "substrates": [
        "photonic",
        "integrated"
      ],
      "models": [
        "neural"
      ],
      "aliases": [],
      "sources": [
        "alt-lighton-opu"
      ],
      "summary": "A free-space optical core applies a fixed random projection within a conventional host computation pipeline.",
      "config": "LightOn Appliance described in the July 2021 paper; fixed optical matrix, not an arbitrary programmable weight matrix.",
      "gaps": [
        "The passive optical mapping has a fixed matrix; full-system costs include conversion, formatting, transfer, and laser power.",
        "No arbitrary optical neural-network training capability is inferred."
      ],
      "insight": "When is a fixed random transform useful enough to avoid reprogramming weights?",
      "fields": {
        "state": {
          "value": "Binary input and detected output intensities",
          "locator": "§II",
          "source": "alt-lighton-opu"
        },
        "compute": {
          "value": "Scattering projection and intensity nonlinearity",
          "locator": "§II",
          "source": "alt-lighton-opu"
        },
        "memory": {
          "value": "Fixed optical matrix",
          "locator": "§II",
          "source": "alt-lighton-opu"
        },
        "control": {
          "value": "FPGA data formatting and host API",
          "locator": "§II, Hardware/Software",
          "source": "alt-lighton-opu"
        },
        "io": {
          "value": "Gen2 ×4 external PCIe appliance link",
          "locator": "§II, Hardware",
          "source": "alt-lighton-opu"
        },
        "software": {
          "value": "LightOnML Python; CPU/GPU pipeline",
          "locator": "§II–III",
          "source": "alt-lighton-opu"
        },
        "workload": {
          "value": "Random features and accelerated linear algebra",
          "locator": "§III",
          "source": "alt-lighton-opu"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "A fixed optical transform in a programmable host pipeline",
        "scope": "Functional decomposition from the 2021 paper; exact commercial optical geometry is not published here.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "host",
            "label": "Python pipeline",
            "subtitle": "CPU / GPU",
            "text": "Prepares and consumes transformed data.",
            "x": 30,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-lighton-opu",
            "locator": "§III",
            "control": false
          },
          {
            "id": "pcie",
            "label": "PCIe interface",
            "subtitle": "HOST LINK",
            "text": "Transfers input and result batches.",
            "x": 245,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-lighton-opu",
            "locator": "§II, Hardware",
            "control": false
          },
          {
            "id": "fpga",
            "label": "FPGA I/O",
            "subtitle": "FORMATTING",
            "text": "Formats optical-core data.",
            "x": 460,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-lighton-opu",
            "locator": "§II, Hardware",
            "control": false
          },
          {
            "id": "mod",
            "label": "Light modulation",
            "subtitle": "INPUT ENCODING",
            "text": "Maps input onto light.",
            "x": 675,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-lighton-opu",
            "locator": "§II",
            "control": false
          },
          {
            "id": "laser",
            "label": "Laser",
            "subtitle": "ILLUMINATION",
            "text": "Supplies the optical carrier.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-lighton-opu",
            "locator": "§II, Hardware",
            "control": false
          },
          {
            "id": "scatter",
            "label": "Scattering core",
            "subtitle": "FIXED MATRIX",
            "text": "Performs random linear mixing.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-lighton-opu",
            "locator": "§II",
            "control": false
          },
          {
            "id": "detect",
            "label": "Detection",
            "subtitle": "INTENSITY OUTPUT",
            "text": "Measures transformed intensities.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-lighton-opu",
            "locator": "§II",
            "control": false
          },
          {
            "id": "api",
            "label": "LightOnML",
            "subtitle": "SOFTWARE API",
            "text": "Integrates preprocessing and calls.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-lighton-opu",
            "locator": "§II, Software",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "api",
            "type": "control",
            "locator": "§II, Software",
            "label": "",
            "source": "alt-lighton-opu"
          },
          {
            "from": "api",
            "to": "pcie",
            "type": "control",
            "locator": "§II",
            "label": "",
            "source": "alt-lighton-opu"
          },
          {
            "from": "pcie",
            "to": "fpga",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-lighton-opu"
          },
          {
            "from": "fpga",
            "to": "mod",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-lighton-opu"
          },
          {
            "from": "laser",
            "to": "mod",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-lighton-opu"
          },
          {
            "from": "mod",
            "to": "scatter",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-lighton-opu"
          },
          {
            "from": "scatter",
            "to": "detect",
            "type": "data",
            "locator": "§II",
            "label": "",
            "source": "alt-lighton-opu"
          },
          {
            "from": "detect",
            "to": "fpga",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-lighton-opu"
          },
          {
            "from": "fpga",
            "to": "pcie",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-lighton-opu"
          },
          {
            "from": "pcie",
            "to": "host",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-lighton-opu"
          }
        ]
      },
      "originalCandidate": "LightOn optical processing unit"
    },
    {
      "id": "queue-160",
      "name": "Envise 4U blade (announced configuration)",
      "organization": "Lightmatter",
      "year": 2021,
      "yearLabel": "March 2021 announcement",
      "kind": "Announced commercial architecture",
      "status": "dossier",
      "track": "light",
      "trackName": "Photonic processors",
      "discoveryParadigms": [
        "optical",
        "analog"
      ],
      "paradigms": [
        "optical",
        "hybrid",
        "digital",
        "parallel"
      ],
      "architectures": [
        "heterogeneous",
        "optical-linear",
        "distributed"
      ],
      "substrates": [
        "photonic",
        "integrated"
      ],
      "models": [
        "neural"
      ],
      "aliases": [],
      "sources": [
        "alt-envise-announcement"
      ],
      "summary": "An announced photonic inference blade places multiple Envise accelerators inside a software-managed scale-out platform.",
      "config": "The 4U, 16-chip blade described in Lightmatter’s 2021 announcement. Internal datapath details are not publicly specified by this source.",
      "gaps": [
        "The primary announcement does not disclose an inspectable chip-level netlist, exact memory paths, or end-to-end benchmark conditions.",
        "No projected product claim is converted into an installed-system fact."
      ],
      "insight": "Which parts of an optical computing product are still conventional system resources?",
      "fields": {
        "state": {
          "value": "Neural-model weights and activations",
          "locator": "Product announcement",
          "source": "alt-envise-announcement"
        },
        "compute": {
          "value": "16 Envise chips per announced blade",
          "locator": "Blade configuration paragraph",
          "source": "alt-envise-announcement"
        },
        "memory": {
          "value": "1 TB DDR4 and 3 TB solid-state storage",
          "locator": "Blade configuration paragraph",
          "source": "alt-envise-announcement"
        },
        "control": {
          "value": "Idiom model compilation and execution",
          "locator": "Idiom paragraph",
          "source": "alt-envise-announcement"
        },
        "io": {
          "value": "Published optical multi-blade scale-out interface",
          "locator": "Blade configuration paragraph",
          "source": "alt-envise-announcement"
        },
        "software": {
          "value": "Idiom debug, profiling, optimization, discovery",
          "locator": "Idiom paragraph",
          "source": "alt-envise-announcement"
        },
        "workload": {
          "value": "Neural-network inference",
          "locator": "Product announcement",
          "source": "alt-envise-announcement"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Published platform hierarchy and software boundary",
        "scope": "Containment and software relationships from the announcement, not undisclosed bus wiring or evidence of shipment. Optical chip internals are deliberately unexpanded.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "model",
            "label": "Neural model",
            "subtitle": "USER WORKLOAD",
            "text": "Defines inference computation.",
            "x": 30,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-envise-announcement",
            "locator": "Product announcement",
            "control": false
          },
          {
            "id": "idiom",
            "label": "Idiom compiler",
            "subtitle": "COMPILE / EXECUTE",
            "text": "Prepares and runs mapped models.",
            "x": 245,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-envise-announcement",
            "locator": "Idiom paragraph",
            "control": false
          },
          {
            "id": "manage",
            "label": "Deployment tools",
            "subtitle": "DISCOVER / PROFILE",
            "text": "Manage blade execution.",
            "x": 460,
            "y": 40,
            "w": 160,
            "h": 62,
            "source": "alt-envise-announcement",
            "locator": "Idiom paragraph",
            "control": false
          },
          {
            "id": "blade",
            "label": "4U blade",
            "subtitle": "ANNOUNCED SYSTEM",
            "text": "Contains compute and memory resources.",
            "x": 460,
            "y": 210,
            "w": 160,
            "h": 62,
            "source": "alt-envise-announcement",
            "locator": "Blade configuration paragraph",
            "control": false
          },
          {
            "id": "chips",
            "label": "16 Envise chips",
            "subtitle": "PHOTONIC ACCELERATORS",
            "text": "Execute mapped inference.",
            "x": 675,
            "y": 210,
            "w": 160,
            "h": 62,
            "source": "alt-envise-announcement",
            "locator": "Blade configuration paragraph",
            "control": false
          },
          {
            "id": "dram",
            "label": "DDR4 memory",
            "subtitle": "1 TB",
            "text": "Conventional system memory.",
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            "y": 210,
            "w": 160,
            "h": 62,
            "source": "alt-envise-announcement",
            "locator": "Blade configuration paragraph",
            "control": false
          },
          {
            "id": "ssd",
            "label": "Solid-state storage",
            "subtitle": "3 TB",
            "text": "Conventional persistent storage.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-envise-announcement",
            "locator": "Blade configuration paragraph",
            "control": false
          },
          {
            "id": "scale",
            "label": "Optical scale-out",
            "subtitle": "MULTI-BLADE",
            "text": "Connects announced blade systems.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-envise-announcement",
            "locator": "Blade configuration paragraph",
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          }
        ],
        "edges": [
          {
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          {
            "from": "idiom",
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          {
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            "locator": "Idiom paragraph",
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          {
            "from": "manage",
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          {
            "from": "blade",
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            "locator": "Blade configuration paragraph",
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          },
          {
            "from": "blade",
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            "locator": "Blade configuration paragraph",
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          },
          {
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            "to": "ssd",
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            "locator": "Blade configuration paragraph",
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            "source": "alt-envise-announcement"
          },
          {
            "from": "blade",
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            "locator": "Blade configuration paragraph",
            "label": "",
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          }
        ]
      },
      "originalCandidate": "Lightmatter Envise"
    },
    {
      "id": "queue-161",
      "name": "Lightelligence PACE 64×64",
      "organization": "Lightelligence",
      "year": 2025,
      "yearLabel": "2025 system paper",
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      "status": "dossier",
      "track": "light",
      "trackName": "Photonic processors",
      "discoveryParadigms": [
        "optical",
        "analog"
      ],
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        "analog",
        "optical",
        "hybrid",
        "probabilistic"
      ],
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        "optical-linear",
        "ising-machine",
        "heterogeneous"
      ],
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        "photonic",
        "integrated"
      ],
      "models": [
        "ising"
      ],
      "aliases": [],
      "sources": [
        "alt-pace-2025"
      ],
      "summary": "A co-packaged photonic/electronic system performs matrix products within an electronic recurrent Ising-search loop.",
      "config": "The 64×64 PACE SiP and board in Hua et al. (2025); PCIe-card-sized form factor communicates through Ethernet/SOM/SPI, not an inferred PCIe data interface.",
      "gaps": [
        "Optical MAC time excludes host overhead.",
        "Heuristic search does not guarantee optimality."
      ],
      "insight": "How much of the iterative computation happens after optical detection?",
      "fields": {
        "state": {
          "value": "Binary state vector and analog weighted signals",
          "locator": "Fig. 1b",
          "source": "alt-pace-2025"
        },
        "compute": {
          "value": "1×64 vector and 64×64 optical weight modules",
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          "source": "alt-pace-2025"
        },
        "memory": {
          "value": "Electronic SRAM stores state and results",
          "locator": "System implementation",
          "source": "alt-pace-2025"
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          "value": "Electronic threshold/comparator feedback",
          "locator": "Figs. 1b–2a",
          "source": "alt-pace-2025"
        },
        "io": {
          "value": "Ethernet → SOM → SPI; laser fiber inputs",
          "locator": "Fig. 2c–e",
          "source": "alt-pace-2025"
        },
        "software": {
          "value": "Configured recurrent heuristic algorithm",
          "locator": "Optical MAC section",
          "source": "alt-pace-2025"
        },
        "workload": {
          "value": "Ising/max-cut and image-search demonstrations",
          "locator": "Fig. 4",
          "source": "alt-pace-2025"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Optical MAC inside an electronic recurrent loop",
        "scope": "Fig. 2 functional paths, including lasers and host; package wiring omitted.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "host",
            "label": "Host / SOM",
            "subtitle": "ETHERNET + SPI",
            "text": "Loads vectors, weights and thresholds.",
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            "w": 160,
            "h": 62,
            "source": "alt-pace-2025",
            "locator": "Fig. 2c",
            "control": false
          },
          {
            "id": "sram",
            "label": "EIC SRAM",
            "subtitle": "STATE STORAGE",
            "text": "Retains vectors and results.",
            "x": 245,
            "y": 35,
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            "source": "alt-pace-2025",
            "locator": "System implementation",
            "control": false
          },
          {
            "id": "tx",
            "label": "Vector DAC / driver",
            "subtitle": "TX",
            "text": "Drives input modulators.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-pace-2025",
            "locator": "Fig. 2a",
            "control": false
          },
          {
            "id": "data",
            "label": "Vector modulators",
            "subtitle": "1 × 64",
            "text": "Encodes the binary input in light.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-pace-2025",
            "locator": "Fig. 2a",
            "control": false
          },
          {
            "id": "laser",
            "label": "Laser array",
            "subtitle": "EXTERNAL LIGHT",
            "text": "Illuminates the PIC.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-pace-2025",
            "locator": "Fig. 2e",
            "control": false
          },
          {
            "id": "weight",
            "label": "Weight modulators",
            "subtitle": "64 × 64",
            "text": "Applies the programmed matrix.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-pace-2025",
            "locator": "Fig. 2a",
            "control": false
          },
          {
            "id": "wtx",
            "label": "Weight DAC / driver",
            "subtitle": "WTX",
            "text": "Programs matrix weights.",
            "x": 245,
            "y": 205,
            "w": 160,
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            "source": "alt-pace-2025",
            "locator": "Fig. 2a",
            "control": true
          },
          {
            "id": "rx",
            "label": "Photodetectors / TIA",
            "subtitle": "RX",
            "text": "Converts summed light to voltage.",
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            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-pace-2025",
            "locator": "Fig. 2a",
            "control": false
          },
          {
            "id": "compare",
            "label": "Threshold comparator",
            "subtitle": "EIC FEEDBACK",
            "text": "Produces the next binary vector.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-pace-2025",
            "locator": "Figs. 1b–2a",
            "control": false
          },
          {
            "id": "threshold",
            "label": "Threshold settings",
            "subtitle": "CONFIGURATION",
            "text": "Sets the recurrent nonlinearity.",
            "x": 30,
            "y": 375,
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            "source": "alt-pace-2025",
            "locator": "Fig. 2a",
            "control": true
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        ],
        "edges": [
          {
            "from": "host",
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          {
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          {
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          },
          {
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          },
          {
            "from": "host",
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          },
          {
            "from": "weight",
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            "locator": "Fig. 2e",
            "label": "",
            "source": "alt-pace-2025"
          },
          {
            "from": "rx",
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            "locator": "Fig. 2a",
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          },
          {
            "from": "threshold",
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            "locator": "Fig. 2a",
            "label": "",
            "source": "alt-pace-2025"
          },
          {
            "from": "compare",
            "to": "sram",
            "type": "data",
            "locator": "System implementation",
            "label": "",
            "source": "alt-pace-2025"
          },
          {
            "from": "compare",
            "to": "tx",
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            "locator": "System implementation",
            "label": "next iteration",
            "source": "alt-pace-2025"
          }
        ]
      },
      "originalCandidate": "Lightelligence PACE"
    },
    {
      "id": "queue-162",
      "name": "Feldmann photonic tensor core",
      "organization": "Münster / Oxford / EPFL / IBM and collaborators",
      "year": 2020,
      "yearLabel": "2020 manuscript / 2021 publication",
      "kind": "Photonic laboratory experiment",
      "status": "dossier",
      "track": "light",
      "trackName": "Photonic processors",
      "discoveryParadigms": [
        "optical",
        "analog"
      ],
      "paradigms": [
        "analog",
        "optical",
        "parallel"
      ],
      "architectures": [
        "optical-linear",
        "in-memory"
      ],
      "substrates": [
        "photonic"
      ],
      "models": [
        "neural"
      ],
      "aliases": [],
      "sources": [
        "alt-photonic-tensor"
      ],
      "summary": "Wavelength-multiplexed optical vectors interact with nonvolatile phase-change weights in a waveguide crossbar.",
      "config": "Integrated tensor-core experiments in Feldmann et al.; array sizes and demonstrated convolution cases are explicitly experiment-dependent.",
      "gaps": [
        "Optical fan-out and accumulation have physical loss and finite precision.",
        "The record does not claim all functions or memory in the surrounding system are optical."
      ],
      "insight": "How do wavelengths add parallel inputs without copying the weight matrix?",
      "fields": {
        "state": {
          "value": "Optical amplitudes and phase-change transmission states",
          "locator": "Tensor-core section",
          "source": "alt-photonic-tensor"
        },
        "compute": {
          "value": "Waveguide crossbar matrix–vector products",
          "locator": "Fig. 2",
          "source": "alt-photonic-tensor"
        },
        "memory": {
          "value": "GST phase-change weight cells",
          "locator": "Tensor-core section",
          "source": "alt-photonic-tensor"
        },
        "control": {
          "value": "Input modulation and cell programming",
          "locator": "Fig. 2",
          "source": "alt-photonic-tensor"
        },
        "io": {
          "value": "Microcomb wavelengths and photodetector outputs",
          "locator": "Figs. 1–2",
          "source": "alt-photonic-tensor"
        },
        "software": {
          "value": "Convolution reshaping into MVMs",
          "locator": "Fig. 1c",
          "source": "alt-photonic-tensor"
        },
        "workload": {
          "value": "Parallel convolution demonstrations",
          "locator": "Main text",
          "source": "alt-photonic-tensor"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Wavelength parallelism with stored optical weights",
        "scope": "Logical optical/electronic path; individual couplers, crossings and programming pulses are aggregated.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "image",
            "label": "Input image",
            "subtitle": "ELECTRONIC DATA",
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            "locator": "Fig. 1c",
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          },
          {
            "id": "comb",
            "label": "Soliton microcomb",
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            "y": 35,
            "w": 160,
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            "source": "alt-photonic-tensor",
            "locator": "Fig. 1b",
            "control": false
          },
          {
            "id": "encode",
            "label": "Input modulation",
            "subtitle": "AMPLITUDE ENCODING",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-tensor",
            "locator": "Fig. 1b",
            "control": false
          },
          {
            "id": "fanout",
            "label": "Directional couplers",
            "subtitle": "ROW FAN-OUT",
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            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-tensor",
            "locator": "Fig. 2a",
            "control": false
          },
          {
            "id": "gst",
            "label": "GST weight cells",
            "subtitle": "NONVOLATILE",
            "text": "Attenuate light by stored values.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-tensor",
            "locator": "Fig. 2a",
            "control": false
          },
          {
            "id": "program",
            "label": "Weight programming",
            "subtitle": "PHASE-CHANGE STATE",
            "text": "Configures matrix transmissions.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-tensor",
            "locator": "Tensor-core section",
            "control": true
          },
          {
            "id": "sum",
            "label": "Output waveguides",
            "subtitle": "COLUMN ACCUMULATION",
            "text": "Combine weighted optical powers.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-tensor",
            "locator": "Tensor-core section",
            "control": false
          },
          {
            "id": "detector",
            "label": "Photodetectors",
            "subtitle": "MVM RESULTS",
            "text": "Measure output inner products.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-tensor",
            "locator": "Fig. 1b",
            "control": false
          },
          {
            "id": "kernel",
            "label": "Kernel mapping",
            "subtitle": "FILTER MATRIX",
            "text": "Assigns convolution weights.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-photonic-tensor",
            "locator": "Fig. 1c",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "image",
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            "locator": "Fig. 1c",
            "label": "",
            "source": "alt-photonic-tensor"
          },
          {
            "from": "comb",
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          },
          {
            "from": "encode",
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          },
          {
            "from": "fanout",
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          },
          {
            "from": "gst",
            "to": "sum",
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            "locator": "Tensor-core section",
            "label": "",
            "source": "alt-photonic-tensor"
          },
          {
            "from": "sum",
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            "locator": "Fig. 1b",
            "label": "",
            "source": "alt-photonic-tensor"
          },
          {
            "from": "kernel",
            "to": "program",
            "type": "control",
            "locator": "Fig. 1c",
            "label": "",
            "source": "alt-photonic-tensor"
          },
          {
            "from": "program",
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            "type": "control",
            "locator": "Tensor-core section",
            "label": "",
            "source": "alt-photonic-tensor"
          },
          {
            "from": "detector",
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            "type": "association",
            "locator": "Fig. 1c",
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            "source": "alt-photonic-tensor"
          },
          {
            "from": "comb",
            "to": "sum",
            "type": "association",
            "locator": "Tensor-core section",
            "label": "noninterfering channels",
            "source": "alt-photonic-tensor"
          }
        ]
      },
      "originalCandidate": "Photonic tensor-core experiments"
    },
    {
      "id": "queue-163",
      "name": "NTT measurement-feedback coherent Ising machine",
      "organization": "NTT and collaborators",
      "year": 2016,
      "yearLabel": "2016 measurement-feedback system",
      "kind": "Optical optimization experiment",
      "status": "dossier",
      "track": "light",
      "trackName": "Photonic processors",
      "discoveryParadigms": [
        "optical",
        "analog",
        "probabilistic"
      ],
      "paradigms": [
        "analog",
        "optical",
        "hybrid",
        "probabilistic"
      ],
      "architectures": [
        "ising-machine"
      ],
      "substrates": [
        "photonic",
        "integrated"
      ],
      "models": [
        "ising"
      ],
      "aliases": [],
      "sources": [
        "alt-ntt-cim"
      ],
      "summary": "Time-multiplexed optical parametric oscillators represent spins while measured amplitudes drive FPGA-computed coupling feedback.",
      "config": "Measurement-feedback CIM in the NTT report corresponding to the 2016 2,000-node optimization experiments.",
      "gaps": [
        "An Ising heuristic is not a general quantum gate processor.",
        "Observed optimization outcomes do not establish guaranteed polynomial-time solutions for arbitrary hard problems."
      ],
      "insight": "Which part of the spin coupling is computed electronically rather than by a physical optical edge?",
      "fields": {
        "state": {
          "value": "DOPO phases 0 or π represent spins",
          "locator": "Report, first paragraph",
          "source": "alt-ntt-cim"
        },
        "compute": {
          "value": "Time-multiplexed oscillator network",
          "locator": "Report, second paragraph",
          "source": "alt-ntt-cim"
        },
        "memory": {
          "value": "Circulating pulse state and configured graph",
          "locator": "Fig. 1",
          "source": "alt-ntt-cim"
        },
        "control": {
          "value": "FPGA calculates graph-dependent feedback",
          "locator": "Measurement-feedback paragraph",
          "source": "alt-ntt-cim"
        },
        "io": {
          "value": "Balanced homodyne detection and injected light",
          "locator": "Measurement-feedback paragraph",
          "source": "alt-ntt-cim"
        },
        "software": {
          "value": "Graph-to-feedback configuration",
          "locator": "Measurement-feedback paragraph",
          "source": "alt-ntt-cim"
        },
        "workload": {
          "value": "Ising / maximum-cut optimization",
          "locator": "Benchmark paragraph",
          "source": "alt-ntt-cim"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Optical spin states with electronic all-to-all coupling",
        "scope": "Measurement-feedback configuration, not a claim of direct all-to-all optical wiring or a universal quantum computer.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "pump",
            "label": "Pump reference",
            "subtitle": "OPTICAL PHASE",
            "text": "Defines oscillator phase reference.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-ntt-cim",
            "locator": "Report, first paragraph",
            "control": false
          },
          {
            "id": "dopo",
            "label": "DOPO pulse train",
            "subtitle": "BINARY SPIN PHASES",
            "text": "Carries time-multiplexed spin states.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-ntt-cim",
            "locator": "Report, first paragraph",
            "control": false
          },
          {
            "id": "cavity",
            "label": "Fiber-ring cavity",
            "subtitle": "RECIRCULATING STATE",
            "text": "Supports the pulse network.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-ntt-cim",
            "locator": "Report, second paragraph",
            "control": false
          },
          {
            "id": "homodyne",
            "label": "Homodyne detector",
            "subtitle": "MEASUREMENT",
            "text": "Measures a tapped oscillator signal.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-ntt-cim",
            "locator": "Measurement-feedback paragraph",
            "control": false
          },
          {
            "id": "fpga",
            "label": "FPGA feedback",
            "subtitle": "COUPLING COMPUTATION",
            "text": "Calculates graph-dependent feedback.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-ntt-cim",
            "locator": "Measurement-feedback paragraph",
            "control": false
          },
          {
            "id": "graph",
            "label": "Coupling graph",
            "subtitle": "PROBLEM INPUT",
            "text": "Configures the interaction matrix.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-ntt-cim",
            "locator": "Measurement-feedback paragraph",
            "control": true
          },
          {
            "id": "inject",
            "label": "Optical feedback",
            "subtitle": "PULSE INJECTION",
            "text": "Converts feedback to injected pulses.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-ntt-cim",
            "locator": "Measurement-feedback paragraph",
            "control": false
          },
          {
            "id": "result",
            "label": "Spin readout",
            "subtitle": "OPTIMIZATION RESULT",
            "text": "Records the resulting configuration.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-ntt-cim",
            "locator": "Benchmark paragraph",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "pump",
            "to": "dopo",
            "type": "association",
            "locator": "Report, first paragraph",
            "label": "",
            "source": "alt-ntt-cim"
          },
          {
            "from": "dopo",
            "to": "cavity",
            "type": "association",
            "locator": "Report, second paragraph",
            "label": "",
            "source": "alt-ntt-cim"
          },
          {
            "from": "cavity",
            "to": "homodyne",
            "type": "data",
            "locator": "Measurement-feedback paragraph",
            "label": "",
            "source": "alt-ntt-cim"
          },
          {
            "from": "homodyne",
            "to": "fpga",
            "type": "data",
            "locator": "Measurement-feedback paragraph",
            "label": "",
            "source": "alt-ntt-cim"
          },
          {
            "from": "graph",
            "to": "fpga",
            "type": "control",
            "locator": "Measurement-feedback paragraph",
            "label": "",
            "source": "alt-ntt-cim"
          },
          {
            "from": "fpga",
            "to": "inject",
            "type": "data",
            "locator": "Measurement-feedback paragraph",
            "label": "",
            "source": "alt-ntt-cim"
          },
          {
            "from": "inject",
            "to": "dopo",
            "type": "data",
            "locator": "Measurement-feedback paragraph",
            "label": "",
            "source": "alt-ntt-cim"
          },
          {
            "from": "homodyne",
            "to": "result",
            "type": "data",
            "locator": "Benchmark paragraph",
            "label": "",
            "source": "alt-ntt-cim"
          },
          {
            "from": "result",
            "to": "graph",
            "type": "association",
            "locator": "Benchmark paragraph",
            "label": "evaluate objective",
            "source": "alt-ntt-cim"
          }
        ]
      },
      "originalCandidate": "Coherent Ising machines"
    },
    {
      "id": "queue-164",
      "name": "Carolan six-mode linear optical processor",
      "organization": "University of Bristol and collaborators",
      "year": 2015,
      "yearLabel": "2015 six-mode experiment",
      "kind": "Programmable photonic experiment",
      "status": "dossier",
      "track": "light",
      "trackName": "Photonic processors",
      "discoveryParadigms": [
        "optical",
        "analog"
      ],
      "paradigms": [
        "optical",
        "quantum"
      ],
      "architectures": [
        "optical-linear"
      ],
      "substrates": [
        "photonic"
      ],
      "models": [
        "quantum-circuit"
      ],
      "aliases": [],
      "sources": [
        "alt-universal-linear-optics"
      ],
      "summary": "Fifteen tunable Mach–Zehnder interferometers implement programmable six-mode linear optical transformations.",
      "config": "The six-mode silica-on-silicon LPU in Carolan et al. (2015), with photon sources and detection as external system components.",
      "gaps": [
        "Linear optical universality is bounded by six modes and available states/detection; it is not universal fault-tolerant quantum computation.",
        "No optical gain or nonlinear activation is invented inside the passive MZI cascade."
      ],
      "insight": "Which phase settings turn one physical mesh into different optical protocols?",
      "fields": {
        "state": {
          "value": "Optical mode amplitudes / photon occupations",
          "locator": "Fig. 1",
          "source": "alt-universal-linear-optics"
        },
        "compute": {
          "value": "15-MZI cascade over six modes",
          "locator": "Device description",
          "source": "alt-universal-linear-optics"
        },
        "memory": {
          "value": "30 configured thermo-optic phase shifts",
          "locator": "Device description",
          "source": "alt-universal-linear-optics"
        },
        "control": {
          "value": "Electronic phase-shifter settings",
          "locator": "Fig. 1",
          "source": "alt-universal-linear-optics"
        },
        "io": {
          "value": "Fiber input and 12 single-photon detectors",
          "locator": "Fig. 1",
          "source": "alt-universal-linear-optics"
        },
        "software": {
          "value": "Unitary decomposition into phase settings",
          "locator": "Fig. 1A",
          "source": "alt-universal-linear-optics"
        },
        "workload": {
          "value": "Linear-optical protocols and boson sampling",
          "locator": "Main text",
          "source": "alt-universal-linear-optics"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Prepare photons, configure a unitary, measure outputs",
        "scope": "System boundary around the six-mode processor. Source and detector components are not claimed to be integrated on the LPU.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "laser",
            "label": "Pulsed laser",
            "subtitle": "SOURCE PUMP",
            "text": "Drives photon preparation.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-universal-linear-optics",
            "locator": "Fig. 1B",
            "control": false
          },
          {
            "id": "shg",
            "label": "Frequency doubling",
            "subtitle": "BBO CRYSTAL",
            "text": "Prepares the SPDC pump.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-universal-linear-optics",
            "locator": "Fig. 1B",
            "control": false
          },
          {
            "id": "spdc",
            "label": "SPDC source",
            "subtitle": "BiBO CRYSTAL",
            "text": "Generates photon ensembles.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-universal-linear-optics",
            "locator": "Fig. 1B",
            "control": false
          },
          {
            "id": "filter",
            "label": "Filters / fibers",
            "subtitle": "STATE INPUT",
            "text": "Collects and couples photons.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-universal-linear-optics",
            "locator": "Fig. 1B",
            "control": false
          },
          {
            "id": "mesh",
            "label": "Six-mode MZI mesh",
            "subtitle": "15 INTERFEROMETERS",
            "text": "Implements the selected unitary.",
            "x": 675,
            "y": 210,
            "w": 160,
            "h": 62,
            "source": "alt-universal-linear-optics",
            "locator": "Fig. 1B",
            "control": false
          },
          {
            "id": "phase",
            "label": "Phase shifters",
            "subtitle": "30 CONTROLS",
            "text": "Tune mixing and output phase.",
            "x": 460,
            "y": 210,
            "w": 160,
            "h": 62,
            "source": "alt-universal-linear-optics",
            "locator": "Fig. 1A–B",
            "control": false
          },
          {
            "id": "program",
            "label": "Unitary program",
            "subtitle": "DECOMPOSITION",
            "text": "Determines phase settings.",
            "x": 245,
            "y": 210,
            "w": 160,
            "h": 62,
            "source": "alt-universal-linear-optics",
            "locator": "Fig. 1A",
            "control": true
          },
          {
            "id": "detectors",
            "label": "Photon detectors",
            "subtitle": "12 CHANNELS",
            "text": "Measure output occupations.",
            "x": 675,
            "y": 380,
            "w": 160,
            "h": 62,
            "source": "alt-universal-linear-optics",
            "locator": "Main device description",
            "control": false
          },
          {
            "id": "counts",
            "label": "Detection records",
            "subtitle": "PROTOCOL RESULTS",
            "text": "Support interference statistics.",
            "x": 460,
            "y": 380,
            "w": 160,
            "h": 62,
            "source": "alt-universal-linear-optics",
            "locator": "Main text",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "laser",
            "to": "shg",
            "type": "data",
            "locator": "Fig. 1B",
            "label": "",
            "source": "alt-universal-linear-optics"
          },
          {
            "from": "shg",
            "to": "spdc",
            "type": "data",
            "locator": "Fig. 1B",
            "label": "",
            "source": "alt-universal-linear-optics"
          },
          {
            "from": "spdc",
            "to": "filter",
            "type": "data",
            "locator": "Fig. 1B",
            "label": "",
            "source": "alt-universal-linear-optics"
          },
          {
            "from": "filter",
            "to": "mesh",
            "type": "data",
            "locator": "Fig. 1B",
            "label": "",
            "source": "alt-universal-linear-optics"
          },
          {
            "from": "program",
            "to": "phase",
            "type": "control",
            "locator": "Fig. 1A",
            "label": "",
            "source": "alt-universal-linear-optics"
          },
          {
            "from": "phase",
            "to": "mesh",
            "type": "control",
            "locator": "Fig. 1A–B",
            "label": "",
            "source": "alt-universal-linear-optics"
          },
          {
            "from": "mesh",
            "to": "detectors",
            "type": "data",
            "locator": "Main device description",
            "label": "",
            "source": "alt-universal-linear-optics"
          },
          {
            "from": "detectors",
            "to": "counts",
            "type": "data",
            "locator": "Main text",
            "label": "",
            "source": "alt-universal-linear-optics"
          },
          {
            "from": "program",
            "to": "counts",
            "type": "association",
            "locator": "Main text",
            "label": "target protocol",
            "source": "alt-universal-linear-optics"
          },
          {
            "from": "filter",
            "to": "counts",
            "type": "association",
            "locator": "Main text",
            "label": "input ensemble",
            "source": "alt-universal-linear-optics"
          }
        ]
      },
      "originalCandidate": "Programmable MZI mesh processors"
    },
    {
      "id": "queue-165",
      "name": "Benenson–Shapiro two-state DNA automaton",
      "organization": "Weizmann Institute",
      "year": 2001,
      "yearLabel": "2001 experimental report",
      "kind": "Biomolecular finite-automaton experiment",
      "status": "dossier",
      "track": "molecular",
      "trackName": "Molecular, cellular & chemical",
      "discoveryParadigms": [
        "molecular",
        "biological"
      ],
      "paradigms": [
        "molecular",
        "parallel"
      ],
      "architectures": [
        "dna-reaction"
      ],
      "substrates": [
        "molecular-material"
      ],
      "models": [
        "rewriting",
        "chemical"
      ],
      "aliases": [],
      "sources": [
        "alt-benenson-2001"
      ],
      "summary": "DNA transition molecules select enzyme cuts that expose the next state and input symbol.",
      "config": "Original FokI-and-ligase two-state, two-symbol automaton; even-ones program is one experimentally tested configuration.",
      "gaps": [
        "Finite automaton, not a universal processor.",
        "Only selected programs were tested; the combinatorial program count is not a count of experiments."
      ],
      "insight": "Where is state stored when there is no electronic register?",
      "fields": {
        "state": {
          "value": "Sticky end: state plus current symbol",
          "locator": "Sticky-end paragraphs",
          "source": "alt-benenson-2001"
        },
        "compute": {
          "value": "Hybridization, ligation and FokI cleavage",
          "locator": "Processing-step paragraphs",
          "source": "alt-benenson-2001"
        },
        "memory": {
          "value": "Remaining input DNA and transition molecules",
          "locator": "Hardware/software paragraphs",
          "source": "alt-benenson-2001"
        },
        "control": {
          "value": "Complementarity and programmed cut position",
          "locator": "Processing-step paragraphs",
          "source": "alt-benenson-2001"
        },
        "io": {
          "value": "DNA input; gel-visible output display",
          "locator": "Output-display paragraph",
          "source": "alt-benenson-2001"
        },
        "software": {
          "value": "Chosen transition-molecule mixture",
          "locator": "Programs paragraph",
          "source": "alt-benenson-2001"
        },
        "workload": {
          "value": "Finite-language recognition",
          "locator": "Tested-programs paragraph",
          "source": "alt-benenson-2001"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "A restriction enzyme advances the input",
        "scope": "One molecular transition and terminal readout. Laboratory preparation supplies the program; no in-vivo smart-drug capability is implied.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "input",
            "label": "Input DNA",
            "subtitle": "BINARY WORD",
            "text": "Unprocessed symbols remain.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-benenson-2001",
            "locator": "Hardware/software paragraphs",
            "control": false
          },
          {
            "id": "program",
            "label": "Transition DNA",
            "subtitle": "RULE MIXTURE",
            "text": "Encodes state transitions.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-benenson-2001",
            "locator": "Programs paragraph",
            "control": false
          },
          {
            "id": "match",
            "label": "Sticky-end match",
            "subtitle": "STATE + SYMBOL",
            "text": "Selects complementary rule.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-benenson-2001",
            "locator": "Hybridization paragraph",
            "control": false
          },
          {
            "id": "ligase",
            "label": "Ligase + ATP",
            "subtitle": "SEAL",
            "text": "Joins matched molecules.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-benenson-2001",
            "locator": "Hybridization paragraph",
            "control": false
          },
          {
            "id": "cut",
            "label": "FokI cleavage",
            "subtitle": "ADVANCE",
            "text": "Exposes next encoded pair.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-benenson-2001",
            "locator": "Cleavage paragraph",
            "control": false
          },
          {
            "id": "next",
            "label": "New sticky end",
            "subtitle": "REPEAT",
            "text": "Carries subsequent state.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-benenson-2001",
            "locator": "Cleavage paragraph",
            "control": false
          },
          {
            "id": "display",
            "label": "Output display DNA",
            "subtitle": "FINAL STATE",
            "text": "Captures terminal overhang.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-benenson-2001",
            "locator": "Output-display paragraph",
            "control": false
          },
          {
            "id": "gel",
            "label": "Electrophoresis",
            "subtitle": "EXTERNAL READOUT",
            "text": "Separates result molecules.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-benenson-2001",
            "locator": "Output-display paragraph",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "input",
            "to": "match",
            "type": "data",
            "locator": "Hybridization paragraph",
            "label": "",
            "source": "alt-benenson-2001"
          },
          {
            "from": "program",
            "to": "match",
            "type": "control",
            "locator": "Hybridization paragraph",
            "label": "",
            "source": "alt-benenson-2001"
          },
          {
            "from": "match",
            "to": "ligase",
            "type": "data",
            "locator": "Hybridization paragraph",
            "label": "",
            "source": "alt-benenson-2001"
          },
          {
            "from": "ligase",
            "to": "cut",
            "type": "data",
            "locator": "Cleavage paragraph",
            "label": "",
            "source": "alt-benenson-2001"
          },
          {
            "from": "program",
            "to": "cut",
            "type": "control",
            "locator": "Cleavage paragraph",
            "label": "cut position",
            "source": "alt-benenson-2001"
          },
          {
            "from": "cut",
            "to": "next",
            "type": "data",
            "locator": "Cleavage paragraph",
            "label": "",
            "source": "alt-benenson-2001"
          },
          {
            "from": "next",
            "to": "match",
            "type": "data",
            "locator": "Cleavage paragraph",
            "label": "next transition",
            "source": "alt-benenson-2001"
          },
          {
            "from": "next",
            "to": "display",
            "type": "data",
            "locator": "Output-display paragraph",
            "label": "end of input",
            "source": "alt-benenson-2001"
          },
          {
            "from": "program",
            "to": "display",
            "type": "association",
            "locator": "Hardware/software paragraphs",
            "label": "DNA encoding",
            "source": "alt-benenson-2001"
          },
          {
            "from": "display",
            "to": "gel",
            "type": "data",
            "locator": "Output-display paragraph",
            "label": "",
            "source": "alt-benenson-2001"
          }
        ]
      },
      "originalCandidate": "Shapiro DNA automaton"
    },
    {
      "id": "queue-166",
      "name": "Qian–Winfree four-bit DNA square-root circuit",
      "organization": "California Institute of Technology",
      "year": 2011,
      "yearLabel": "June 2011 experiment",
      "kind": "Enzyme-free DNA logic experiment",
      "status": "dossier",
      "track": "molecular",
      "trackName": "Molecular, cellular & chemical",
      "discoveryParadigms": [
        "molecular",
        "biological"
      ],
      "paradigms": [
        "molecular",
        "digital",
        "parallel"
      ],
      "architectures": [
        "dna-reaction",
        "dataflow-arch"
      ],
      "substrates": [
        "molecular-material"
      ],
      "models": [
        "logic",
        "chemical"
      ],
      "aliases": [],
      "sources": [
        "alt-seesaw-2011"
      ],
      "summary": "Seesaw strand exchange, thresholds and fuel restore digital signals through a molecular logic cascade.",
      "config": "Fig. 4 four-bit integer square root: 130 strands interacting in one tube, with all sixteen input combinations tested.",
      "gaps": [
        "Finite reagent stocks and leakage limit operation.",
        "Digital encoding does not make reaction kinetics instantaneous or clocked."
      ],
      "insight": "Why must both Boolean values have explicit molecular signals?",
      "fields": {
        "state": {
          "value": "Dual-rail strand concentrations",
          "locator": "Fig. 4",
          "source": "alt-seesaw-2011"
        },
        "compute": {
          "value": "Integrating and amplifying seesaw gates",
          "locator": "Figs. 1–2",
          "source": "alt-seesaw-2011"
        },
        "memory": {
          "value": "Free/bound strands; consumed threshold/fuel stocks",
          "locator": "Fig. 1",
          "source": "alt-seesaw-2011"
        },
        "control": {
          "value": "Sequences and initial concentrations",
          "locator": "Figs. 1–4",
          "source": "alt-seesaw-2011"
        },
        "io": {
          "value": "Input strands; fluorescent reporters",
          "locator": "Fig. 4",
          "source": "alt-seesaw-2011"
        },
        "software": {
          "value": "Logic-to-seesaw compilation",
          "locator": "p. 1201",
          "source": "alt-seesaw-2011"
        },
        "workload": {
          "value": "Floor of square root, four-bit input",
          "locator": "Fig. 4",
          "source": "alt-seesaw-2011"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Molecular restoration inside the square-root cascade",
        "scope": "Gate mechanism is expanded inside the published circuit, not a guessed gate-by-gate reproduction of Fig. 4.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "bits",
            "label": "Four dual-rail inputs",
            "subtitle": "0 / 1 STRANDS",
            "text": "Selects each input value.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-seesaw-2011",
            "locator": "Fig. 4",
            "control": false
          },
          {
            "id": "integrate",
            "label": "Integrating gate",
            "subtitle": "SUM INPUTS",
            "text": "Exchanges bound signals.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-seesaw-2011",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "threshold",
            "label": "Threshold complex",
            "subtitle": "FAST SINK",
            "text": "Absorbs subthreshold input.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-seesaw-2011",
            "locator": "Fig. 1C",
            "control": false
          },
          {
            "id": "amplify",
            "label": "Amplifying gate",
            "subtitle": "SIGNAL RESTORATION",
            "text": "Releases downstream signal.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-seesaw-2011",
            "locator": "Figs. 1–2",
            "control": false
          },
          {
            "id": "fuel",
            "label": "Fuel strands",
            "subtitle": "CATALYTIC CYCLE",
            "text": "Displaces and recycles input.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-seesaw-2011",
            "locator": "Fig. 1D",
            "control": false
          },
          {
            "id": "cascade",
            "label": "AND / OR network",
            "subtitle": "SQUARE-ROOT LOGIC",
            "text": "Composes restored signals.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-seesaw-2011",
            "locator": "Fig. 4B",
            "control": false
          },
          {
            "id": "rails",
            "label": "Two dual-rail outputs",
            "subtitle": "RESULT SPECIES",
            "text": "Encodes two result bits.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-seesaw-2011",
            "locator": "Fig. 4B",
            "control": false
          },
          {
            "id": "report",
            "label": "Reporter complexes",
            "subtitle": "DYE / QUENCHER",
            "text": "Converts strands to fluorescence.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-seesaw-2011",
            "locator": "Figs. 1C; 4",
            "control": false
          },
          {
            "id": "trace",
            "label": "Fluorescence traces",
            "subtitle": "EXTERNAL READOUT",
            "text": "Resolves ON/OFF outputs.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-seesaw-2011",
            "locator": "Fig. 4C–D",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "bits",
            "to": "integrate",
            "type": "data",
            "locator": "Fig. 4B",
            "label": "",
            "source": "alt-seesaw-2011"
          },
          {
            "from": "integrate",
            "to": "threshold",
            "type": "data",
            "locator": "Fig. 2",
            "label": "competitive sink",
            "source": "alt-seesaw-2011"
          },
          {
            "from": "integrate",
            "to": "amplify",
            "type": "data",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-seesaw-2011"
          },
          {
            "from": "threshold",
            "to": "amplify",
            "type": "control",
            "locator": "Fig. 2",
            "label": "sets activation boundary",
            "source": "alt-seesaw-2011"
          },
          {
            "from": "fuel",
            "to": "amplify",
            "type": "data",
            "locator": "Fig. 1D",
            "label": "",
            "source": "alt-seesaw-2011"
          },
          {
            "from": "amplify",
            "to": "fuel",
            "type": "association",
            "locator": "Fig. 1D",
            "label": "fuel consumed",
            "source": "alt-seesaw-2011"
          },
          {
            "from": "amplify",
            "to": "cascade",
            "type": "data",
            "locator": "Fig. 4B",
            "label": "",
            "source": "alt-seesaw-2011"
          },
          {
            "from": "cascade",
            "to": "rails",
            "type": "data",
            "locator": "Fig. 4B",
            "label": "",
            "source": "alt-seesaw-2011"
          },
          {
            "from": "rails",
            "to": "report",
            "type": "data",
            "locator": "Fig. 4B",
            "label": "",
            "source": "alt-seesaw-2011"
          },
          {
            "from": "report",
            "to": "trace",
            "type": "data",
            "locator": "Fig. 4C–D",
            "label": "",
            "source": "alt-seesaw-2011"
          }
        ]
      },
      "originalCandidate": "DNA strand-displacement circuits"
    },
    {
      "id": "queue-167",
      "name": "DAE-E Sierpinski DNA-tile experiment",
      "organization": "California Institute of Technology",
      "year": 2004,
      "yearLabel": "December 2004 publication",
      "kind": "Algorithmic self-assembly experiment",
      "status": "dossier",
      "track": "molecular",
      "trackName": "Molecular, cellular & chemical",
      "discoveryParadigms": [
        "molecular",
        "biological"
      ],
      "paradigms": [
        "molecular",
        "parallel",
        "unconventional"
      ],
      "architectures": [
        "cellular-arch",
        "dna-reaction"
      ],
      "substrates": [
        "molecular-material"
      ],
      "models": [
        "cellular"
      ],
      "aliases": [],
      "sources": [
        "alt-dna-sierpinski"
      ],
      "summary": "Four molecular tile types extend a seeded lattice using a local XOR rule.",
      "config": "DAE-E implementation in Figs. 4A and 5; bulk annealing and AFM inspection of imperfect crystals.",
      "gaps": [
        "Mismatch, unseeded growth and distorted crystals occur.",
        "The experiment demonstrates XOR-pattern assembly, not arbitrary error-free algorithms."
      ],
      "insight": "How does geometry turn local molecular matching into a computation history?",
      "fields": {
        "state": {
          "value": "Tile identity and exposed sticky ends",
          "locator": "Fig. 4A",
          "source": "alt-dna-sierpinski"
        },
        "compute": {
          "value": "Neighbor-dependent tile attachment",
          "locator": "Fig. 1",
          "source": "alt-dna-sierpinski"
        },
        "memory": {
          "value": "Accumulated crystal pattern",
          "locator": "Fig. 5",
          "source": "alt-dna-sierpinski"
        },
        "control": {
          "value": "Sequence complementarity; annealing schedule",
          "locator": "Methods",
          "source": "alt-dna-sierpinski"
        },
        "io": {
          "value": "PCR-generated seed; hairpin AFM contrast",
          "locator": "Fig. 4A; Methods",
          "source": "alt-dna-sierpinski"
        },
        "software": {
          "value": "Four XOR rule tiles",
          "locator": "Fig. 4A",
          "source": "alt-dna-sierpinski"
        },
        "workload": {
          "value": "Sierpinski pattern growth",
          "locator": "Fig. 5",
          "source": "alt-dna-sierpinski"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "XOR propagation grows a readable crystal",
        "scope": "DAE-E chemistry; rows represent a logical history, while physical attachment is asynchronous.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "pcr",
            "label": "Assembly PCR",
            "subtitle": "SEED PREPARATION",
            "text": "Builds long nucleating strand.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-dna-sierpinski",
            "locator": "Methods: Nucleating strands",
            "control": false
          },
          {
            "id": "seed",
            "label": "Seed + cap strands",
            "subtitle": "INPUT ROW",
            "text": "Supplies 0 and sparse 1 sites.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-dna-sierpinski",
            "locator": "Fig. 4A",
            "control": false
          },
          {
            "id": "rules",
            "label": "Four DAE-E tiles",
            "subtitle": "XOR PROGRAM",
            "text": "VE00, UE11, RE01, SE10.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-dna-sierpinski",
            "locator": "Fig. 4A",
            "control": false
          },
          {
            "id": "cool",
            "label": "Bulk annealing",
            "subtitle": "EXTERNAL CONTROL",
            "text": "Forms tiles before crystals.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-dna-sierpinski",
            "locator": "Self-Assembly section",
            "control": true
          },
          {
            "id": "front",
            "label": "Two-neighbor match",
            "subtitle": "LOCAL COMPUTE",
            "text": "Selects a matching XOR tile.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-dna-sierpinski",
            "locator": "Fig. 1B–D",
            "control": false
          },
          {
            "id": "ends",
            "label": "Duplicated output ends",
            "subtitle": "NEXT NEIGHBORS",
            "text": "Exposes the computed symbol.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-dna-sierpinski",
            "locator": "Fig. 1B",
            "control": false
          },
          {
            "id": "lattice",
            "label": "Growing lattice",
            "subtitle": "SPATIAL HISTORY",
            "text": "Retains results and errors.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-dna-sierpinski",
            "locator": "Fig. 5",
            "control": false
          },
          {
            "id": "mica",
            "label": "Mica deposition",
            "subtitle": "SAMPLE PREPARATION",
            "text": "Supports final inspection.",
            "x": 30,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-dna-sierpinski",
            "locator": "Self-Assembly section",
            "control": false
          },
          {
            "id": "afm",
            "label": "Tapping-mode AFM",
            "subtitle": "READOUT",
            "text": "Hairpins distinguish 1 tiles.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-dna-sierpinski",
            "locator": "Fig. 4A; Methods",
            "control": false
          }
        ],
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          {
            "from": "pcr",
            "to": "seed",
            "type": "data",
            "locator": "Fig. 4A",
            "label": "",
            "source": "alt-dna-sierpinski"
          },
          {
            "from": "seed",
            "to": "front",
            "type": "data",
            "locator": "Fig. 4A",
            "label": "",
            "source": "alt-dna-sierpinski"
          },
          {
            "from": "rules",
            "to": "front",
            "type": "data",
            "locator": "Fig. 4A",
            "label": "",
            "source": "alt-dna-sierpinski"
          },
          {
            "from": "cool",
            "to": "rules",
            "type": "control",
            "locator": "Self-Assembly section",
            "label": "",
            "source": "alt-dna-sierpinski"
          },
          {
            "from": "cool",
            "to": "front",
            "type": "control",
            "locator": "Self-Assembly section",
            "label": "",
            "source": "alt-dna-sierpinski"
          },
          {
            "from": "front",
            "to": "ends",
            "type": "data",
            "locator": "Fig. 1B",
            "label": "",
            "source": "alt-dna-sierpinski"
          },
          {
            "from": "ends",
            "to": "front",
            "type": "data",
            "locator": "Fig. 1D",
            "label": "further growth",
            "source": "alt-dna-sierpinski"
          },
          {
            "from": "front",
            "to": "lattice",
            "type": "data",
            "locator": "Fig. 5",
            "label": "",
            "source": "alt-dna-sierpinski"
          },
          {
            "from": "lattice",
            "to": "mica",
            "type": "data",
            "locator": "Self-Assembly section",
            "label": "",
            "source": "alt-dna-sierpinski"
          },
          {
            "from": "mica",
            "to": "afm",
            "type": "data",
            "locator": "Self-Assembly section",
            "label": "",
            "source": "alt-dna-sierpinski"
          }
        ]
      },
      "originalCandidate": "DNA tile self-assembly computers"
    },
    {
      "id": "queue-168",
      "name": "Cello 2016 Eco1C1G1T1 circuits",
      "organization": "MIT / Boston University / NIST",
      "year": 2016,
      "yearLabel": "April 2016 experimental paper",
      "kind": "Genetic design system with built circuits",
      "status": "dossier",
      "track": "molecular",
      "trackName": "Molecular, cellular & chemical",
      "discoveryParadigms": [
        "molecular",
        "biological"
      ],
      "paradigms": [
        "biological",
        "digital"
      ],
      "architectures": [
        "configured",
        "cellular-arch"
      ],
      "substrates": [
        "living",
        "molecular-material"
      ],
      "models": [
        "logic"
      ],
      "aliases": [],
      "sources": [
        "alt-cello-2016"
      ],
      "summary": "A compiler assigns insulated repressor gates and emits DNA for experimentally built E. coli circuits.",
      "config": "Original Eco1C1G1T1 UCF, E. coli NEB 10-beta and two-plasmid specification; Priority Detector is the named example.",
      "gaps": [
        "Growth, context and invalid gate combinations constrain designs.",
        "Later Cello versions and other organisms are separate configurations."
      ],
      "insight": "Why are gate response functions insufficient without genetic insulation?",
      "fields": {
        "state": {
          "value": "Promoter activity and regulator expression",
          "locator": "Figs. 1–3",
          "source": "alt-cello-2016"
        },
        "compute": {
          "value": "Insulated NOT/NOR repressor network",
          "locator": "Fig. 3B",
          "source": "alt-cello-2016"
        },
        "memory": {
          "value": "DNA construct; cellular expression state",
          "locator": "Fig. 1B",
          "source": "alt-cello-2016"
        },
        "control": {
          "value": "Sensor promoters and genetic layout",
          "locator": "Figs. 1; 4",
          "source": "alt-cello-2016"
        },
        "io": {
          "value": "IPTG, aTc, arabinose; YFP cytometry",
          "locator": "Fig. 4 caption",
          "source": "alt-cello-2016"
        },
        "software": {
          "value": "Verilog, UCF, ABC and assignment search",
          "locator": "Fig. 1; Cello design environment",
          "source": "alt-cello-2016"
        },
        "workload": {
          "value": "Combinational circuits including priority detection",
          "locator": "Fig. 4",
          "source": "alt-cello-2016"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Compilation boundary and living computation",
        "scope": "Design pipeline plus physical gate organization. Each Priority Detector output was measured in a separate YFP experiment.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "verilog",
            "label": "Verilog specification",
            "subtitle": "DESIGN INPUT",
            "text": "Defines a truth table.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-cello-2016",
            "locator": "Fig. 1A",
            "control": false
          },
          {
            "id": "ucf",
            "label": "UCF library",
            "subtitle": "CHARACTERIZATION",
            "text": "Contains gates and constraints.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-cello-2016",
            "locator": "Cello design environment",
            "control": false
          },
          {
            "id": "logic",
            "label": "Synthesis + assignment",
            "subtitle": "HOST SOFTWARE",
            "text": "Chooses repressor gates.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-cello-2016",
            "locator": "Fig. 1A",
            "control": false
          },
          {
            "id": "dna",
            "label": "DNA construct",
            "subtitle": "FABRICATION OUTPUT",
            "text": "Encodes insulated circuits.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-cello-2016",
            "locator": "Fig. 1A",
            "control": false
          },
          {
            "id": "sensors",
            "label": "Sensor promoters",
            "subtitle": "IPTG / aTc / Ara",
            "text": "Convert chemical inputs.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-cello-2016",
            "locator": "Fig. 4 caption",
            "control": false
          },
          {
            "id": "network",
            "label": "Repressor network",
            "subtitle": "LIVING COMPUTE",
            "text": "Implements assigned logic.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-cello-2016",
            "locator": "Figs. 2A; 3B",
            "control": false
          },
          {
            "id": "insulate",
            "label": "Ribozyme / terminators",
            "subtitle": "GENETIC CONTEXT",
            "text": "Protects gate interfaces.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-cello-2016",
            "locator": "Insulated gates section",
            "control": false
          },
          {
            "id": "yfp",
            "label": "Output promoter → YFP",
            "subtitle": "REPORTER PLASMID",
            "text": "Reports one selected output.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-cello-2016",
            "locator": "Figs. 1B; 4 caption",
            "control": false
          },
          {
            "id": "flow",
            "label": "Flow cytometry",
            "subtitle": "EXTERNAL READOUT",
            "text": "Measures cell populations.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-cello-2016",
            "locator": "Fig. 4 caption",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "verilog",
            "to": "logic",
            "type": "control",
            "locator": "Fig. 1A",
            "label": "",
            "source": "alt-cello-2016"
          },
          {
            "from": "ucf",
            "to": "logic",
            "type": "data",
            "locator": "Fig. 1A",
            "label": "",
            "source": "alt-cello-2016"
          },
          {
            "from": "logic",
            "to": "dna",
            "type": "data",
            "locator": "Fig. 1A",
            "label": "",
            "source": "alt-cello-2016"
          },
          {
            "from": "dna",
            "to": "sensors",
            "type": "control",
            "locator": "Fig. 1B",
            "label": "",
            "source": "alt-cello-2016"
          },
          {
            "from": "dna",
            "to": "network",
            "type": "control",
            "locator": "Fig. 1B",
            "label": "",
            "source": "alt-cello-2016"
          },
          {
            "from": "sensors",
            "to": "network",
            "type": "data",
            "locator": "Fig. 2A",
            "label": "",
            "source": "alt-cello-2016"
          },
          {
            "from": "insulate",
            "to": "network",
            "type": "association",
            "locator": "Fig. 3B",
            "label": "",
            "source": "alt-cello-2016"
          },
          {
            "from": "network",
            "to": "yfp",
            "type": "control",
            "locator": "Fig. 1B",
            "label": "",
            "source": "alt-cello-2016"
          },
          {
            "from": "yfp",
            "to": "flow",
            "type": "data",
            "locator": "Fig. 4 caption",
            "label": "",
            "source": "alt-cello-2016"
          },
          {
            "from": "ucf",
            "to": "insulate",
            "type": "control",
            "locator": "Insulated gates section",
            "label": "",
            "source": "alt-cello-2016"
          }
        ]
      },
      "originalCandidate": "Cello genetic circuits"
    },
    {
      "id": "queue-169",
      "name": "Tamsir four-colony bacterial XOR",
      "organization": "University of California, San Francisco",
      "year": 2011,
      "yearLabel": "2011 issue; online December 2010",
      "kind": "Multicellular logic experiment",
      "status": "dossier",
      "track": "molecular",
      "trackName": "Molecular, cellular & chemical",
      "discoveryParadigms": [
        "molecular",
        "biological"
      ],
      "paradigms": [
        "biological",
        "digital",
        "parallel"
      ],
      "architectures": [
        "cellular-arch",
        "distributed"
      ],
      "substrates": [
        "living",
        "molecular-material"
      ],
      "models": [
        "logic",
        "process"
      ],
      "aliases": [],
      "sources": [
        "alt-bacterial-xor"
      ],
      "summary": "Spatially arranged bacterial colonies communicate using diffusible quorum signals to compute XOR.",
      "config": "Four-strain agar-plate XOR in Fig. 3: three NOR colonies and a final buffer colony.",
      "gaps": [
        "Liquid-culture timing is less robust.",
        "This finite circuit does not establish a scalable autonomous biological computer."
      ],
      "insight": "Which sequencing is supplied by the experimenter rather than the bacteria?",
      "fields": {
        "state": {
          "value": "Promoter / repressor activity in colonies",
          "locator": "§1.3; Supplementary Table 5",
          "source": "alt-bacterial-xor"
        },
        "compute": {
          "value": "Three NOR gates plus buffer",
          "locator": "Supplementary Table 5",
          "source": "alt-bacterial-xor"
        },
        "memory": {
          "value": "Encoded gates and transient expression",
          "locator": "§1.3; Supplementary Table 5",
          "source": "alt-bacterial-xor"
        },
        "control": {
          "value": "Spatial arrangement; delayed colony spotting",
          "locator": "§4; Supplementary Fig. 11",
          "source": "alt-bacterial-xor"
        },
        "io": {
          "value": "Ara and aTc inputs; YFP cytometry",
          "locator": "Supplementary Figs. 6; 11",
          "source": "alt-bacterial-xor"
        },
        "software": {
          "value": "Gate-strain choice and placement",
          "locator": "Supplementary Table 5",
          "source": "alt-bacterial-xor"
        },
        "workload": {
          "value": "Two-input XOR",
          "locator": "Supplementary Table 5; §5",
          "source": "alt-bacterial-xor"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Chemical wires between four colony populations",
        "scope": "Aggregates each colony. Inputs are uniform; layer timing is externally staged.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "ara",
            "label": "Arabinose",
            "subtitle": "INPUT A",
            "text": "Uniform plate input.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-bacterial-xor",
            "locator": "Supplementary Table 5; §5",
            "control": false
          },
          {
            "id": "atc",
            "label": "aTc",
            "subtitle": "INPUT B",
            "text": "Uniform plate input.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-bacterial-xor",
            "locator": "Supplementary Table 5; §5",
            "control": false
          },
          {
            "id": "c1",
            "label": "Colony 1: NOR",
            "subtitle": "LasI OUTPUT",
            "text": "Computes neither input.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-bacterial-xor",
            "locator": "Supplementary Table 5; §5",
            "control": false
          },
          {
            "id": "las",
            "label": "3OC12-HSL",
            "subtitle": "CHEMICAL WIRE",
            "text": "Diffuses to next colonies.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-bacterial-xor",
            "locator": "Supplementary Table 5; §5",
            "control": false
          },
          {
            "id": "c2",
            "label": "Colony 2: NOR",
            "subtitle": "RhlI OUTPUT",
            "text": "Combines A and Las signal.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-bacterial-xor",
            "locator": "Supplementary Table 5; §5",
            "control": false
          },
          {
            "id": "c3",
            "label": "Colony 3: NOR",
            "subtitle": "RhlI OUTPUT",
            "text": "Combines B and Las signal.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-bacterial-xor",
            "locator": "Supplementary Table 5; §5",
            "control": false
          },
          {
            "id": "rhl",
            "label": "C4-HSL",
            "subtitle": "CHEMICAL WIRE",
            "text": "Combines second-layer output.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-bacterial-xor",
            "locator": "Supplementary Table 5; §5",
            "control": false
          },
          {
            "id": "c4",
            "label": "Colony 4: buffer",
            "subtitle": "YFP OUTPUT",
            "text": "Reports either branch.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-bacterial-xor",
            "locator": "Supplementary Table 5; §5",
            "control": false
          },
          {
            "id": "timing",
            "label": "Layer spotting schedule",
            "subtitle": "EXTERNAL CONTROL",
            "text": "Reduces asynchronous hazards.",
            "x": 30,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-bacterial-xor",
            "locator": "§4; Supplementary Fig. 11",
            "control": true
          },
          {
            "id": "flow",
            "label": "Flow cytometry",
            "subtitle": "READOUT",
            "text": "Measures final population.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-bacterial-xor",
            "locator": "Supplementary Fig. 11",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "ara",
            "to": "c1",
            "type": "data",
            "locator": "Supplementary Table 5; §5",
            "label": "",
            "source": "alt-bacterial-xor"
          },
          {
            "from": "atc",
            "to": "c1",
            "type": "data",
            "locator": "Supplementary Table 5; §5",
            "label": "",
            "source": "alt-bacterial-xor"
          },
          {
            "from": "c1",
            "to": "las",
            "type": "data",
            "locator": "Supplementary Table 5; §5",
            "label": "",
            "source": "alt-bacterial-xor"
          },
          {
            "from": "las",
            "to": "c2",
            "type": "data",
            "locator": "Supplementary Table 5; §5",
            "label": "",
            "source": "alt-bacterial-xor"
          },
          {
            "from": "las",
            "to": "c3",
            "type": "data",
            "locator": "Supplementary Table 5; §5",
            "label": "",
            "source": "alt-bacterial-xor"
          },
          {
            "from": "ara",
            "to": "c2",
            "type": "data",
            "locator": "Supplementary Table 5; §5",
            "label": "",
            "source": "alt-bacterial-xor"
          },
          {
            "from": "atc",
            "to": "c3",
            "type": "data",
            "locator": "Supplementary Table 5; §5",
            "label": "",
            "source": "alt-bacterial-xor"
          },
          {
            "from": "c2",
            "to": "rhl",
            "type": "data",
            "locator": "Supplementary Table 5; §5",
            "label": "",
            "source": "alt-bacterial-xor"
          },
          {
            "from": "c3",
            "to": "rhl",
            "type": "data",
            "locator": "Supplementary Table 5; §5",
            "label": "",
            "source": "alt-bacterial-xor"
          },
          {
            "from": "rhl",
            "to": "c4",
            "type": "data",
            "locator": "Supplementary Table 5; §5",
            "label": "",
            "source": "alt-bacterial-xor"
          },
          {
            "from": "c4",
            "to": "flow",
            "type": "data",
            "locator": "Supplementary Fig. 11",
            "label": "",
            "source": "alt-bacterial-xor"
          },
          {
            "from": "timing",
            "to": "c1",
            "type": "control",
            "locator": "§4; Supplementary Fig. 11",
            "label": "",
            "source": "alt-bacterial-xor"
          },
          {
            "from": "timing",
            "to": "c4",
            "type": "control",
            "locator": "§4; Supplementary Fig. 11",
            "label": "",
            "source": "alt-bacterial-xor"
          }
        ]
      },
      "originalCandidate": "Bacterial logic-gate experiments"
    },
    {
      "id": "queue-170",
      "name": "Soloveichik–Seelig–Winfree CRN compiler proposal",
      "organization": "University of Washington / Caltech",
      "year": 2010,
      "yearLabel": "2010 theoretical construction",
      "kind": "Molecular architecture proposal",
      "status": "dossier",
      "track": "molecular",
      "trackName": "Molecular, cellular & chemical",
      "discoveryParadigms": [
        "molecular",
        "biological"
      ],
      "paradigms": [
        "molecular",
        "analog",
        "parallel"
      ],
      "architectures": [
        "dna-reaction"
      ],
      "substrates": [
        "molecular-material"
      ],
      "models": [
        "chemical",
        "continuous"
      ],
      "aliases": [],
      "sources": [
        "alt-crn-compiler"
      ],
      "summary": "A domain-level compiler maps formal chemical kinetics into auxiliary DNA strand-displacement modules.",
      "config": "2010 construction; diagram expands the proposed X1 → X2 + X3 unimolecular module in Fig. 2.",
      "gaps": [
        "Accuracy assumes suitable rate separation and abundant auxiliaries.",
        "Finite stocks and unmodeled chemistry limit physical applicability; universality is a construction claim."
      ],
      "insight": "Why do auxiliary molecules supply both kinetics and material resources?",
      "fields": {
        "state": {
          "value": "Concentrations of active signal strands",
          "locator": "Unimolecular Reactions",
          "source": "alt-crn-compiler"
        },
        "compute": {
          "value": "Toehold-mediated displacement cascades",
          "locator": "Fig. 1",
          "source": "alt-crn-compiler"
        },
        "memory": {
          "value": "Free/bound species; auxiliary stocks",
          "locator": "Implementing Networks",
          "source": "alt-crn-compiler"
        },
        "control": {
          "value": "Sequences, concentrations and toehold rates",
          "locator": "Figs. 1–2",
          "source": "alt-crn-compiler"
        },
        "io": {
          "value": "Initial species; modeled concentration trajectories",
          "locator": "Figs. 5–6",
          "source": "alt-crn-compiler"
        },
        "software": {
          "value": "Formal CRN compilation",
          "locator": "Implementing Networks",
          "source": "alt-crn-compiler"
        },
        "workload": {
          "value": "Numerically modeled dynamical networks",
          "locator": "Figs. 5–6",
          "source": "alt-crn-compiler"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Proposed two-stage reaction module",
        "scope": "Molecular design and modeled behavior, not an experimentally built circuit. Arrows denote reactant/product dependencies.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "rule",
            "label": "Formal reaction",
            "subtitle": "X1 → X2 + X3",
            "text": "Specifies desired kinetics.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-crn-compiler",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "compile",
            "label": "Domain-level construction",
            "subtitle": "DESIGN STEP",
            "text": "Chooses auxiliary complexes.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-crn-compiler",
            "locator": "Implementing Networks",
            "control": false
          },
          {
            "id": "x1",
            "label": "Signal X1",
            "subtitle": "ACTIVE STRAND",
            "text": "Represents reactant.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-crn-compiler",
            "locator": "Fig. 2A",
            "control": false
          },
          {
            "id": "gate",
            "label": "Gate complex Gi",
            "subtitle": "AUXILIARY STOCK",
            "text": "Binds and inactivates X1.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-crn-compiler",
            "locator": "Fig. 2A",
            "control": false
          },
          {
            "id": "oi",
            "label": "Intermediate Oi",
            "subtitle": "RELEASED STRAND",
            "text": "Bridges arbitrary species IDs.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-crn-compiler",
            "locator": "Fig. 2A–B",
            "control": false
          },
          {
            "id": "translator",
            "label": "Translator Ti",
            "subtitle": "AUXILIARY STOCK",
            "text": "Releases product signals.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-crn-compiler",
            "locator": "Fig. 2B",
            "control": false
          },
          {
            "id": "products",
            "label": "X2 and X3",
            "subtitle": "ACTIVE PRODUCTS",
            "text": "Represent formal products.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-crn-compiler",
            "locator": "Fig. 2B",
            "control": false
          },
          {
            "id": "waste",
            "label": "Inactive complexes",
            "subtitle": "BOUND MATERIAL",
            "text": "Retains consumed strands.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-crn-compiler",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "model",
            "label": "Kinetic simulation",
            "subtitle": "ANALYSIS BOUNDARY",
            "text": "Compares concentration traces.",
            "x": 30,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-crn-compiler",
            "locator": "Figs. 5–6",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "rule",
            "to": "compile",
            "type": "control",
            "locator": "Implementing Networks",
            "label": "",
            "source": "alt-crn-compiler"
          },
          {
            "from": "compile",
            "to": "gate",
            "type": "control",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-crn-compiler"
          },
          {
            "from": "compile",
            "to": "translator",
            "type": "control",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-crn-compiler"
          },
          {
            "from": "x1",
            "to": "gate",
            "type": "data",
            "locator": "Fig. 2A",
            "label": "",
            "source": "alt-crn-compiler"
          },
          {
            "from": "gate",
            "to": "oi",
            "type": "data",
            "locator": "Fig. 2A",
            "label": "",
            "source": "alt-crn-compiler"
          },
          {
            "from": "gate",
            "to": "waste",
            "type": "data",
            "locator": "Fig. 2A",
            "label": "",
            "source": "alt-crn-compiler"
          },
          {
            "from": "oi",
            "to": "translator",
            "type": "data",
            "locator": "Fig. 2B",
            "label": "",
            "source": "alt-crn-compiler"
          },
          {
            "from": "translator",
            "to": "products",
            "type": "data",
            "locator": "Fig. 2B",
            "label": "",
            "source": "alt-crn-compiler"
          },
          {
            "from": "translator",
            "to": "waste",
            "type": "data",
            "locator": "Fig. 2B",
            "label": "",
            "source": "alt-crn-compiler"
          },
          {
            "from": "products",
            "to": "model",
            "type": "association",
            "locator": "Figs. 5–6",
            "label": "",
            "source": "alt-crn-compiler"
          },
          {
            "from": "rule",
            "to": "model",
            "type": "control",
            "locator": "Figs. 5–6",
            "label": "",
            "source": "alt-crn-compiler"
          }
        ]
      },
      "originalCandidate": "Chemical reaction-network computers"
    },
    {
      "id": "queue-171",
      "name": "MAREX Lite FPGA membrane processor",
      "organization": "University of Seville research team",
      "year": 2022,
      "yearLabel": "2022 journal issue; accepted 2021",
      "kind": "FPGA synthesis proof of concept",
      "status": "dossier",
      "track": "molecular",
      "trackName": "Molecular, cellular & chemical",
      "discoveryParadigms": [
        "molecular",
        "biological"
      ],
      "paradigms": [
        "digital",
        "parallel"
      ],
      "architectures": [
        "reconfigurable",
        "dataflow-arch"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "rewriting"
      ],
      "aliases": [],
      "sources": [
        "alt-marex-lite"
      ],
      "summary": "Digital object containers circulate through rule units that implement one membrane’s multiset rewriting.",
      "config": "MAREX Lite synthesis for Xilinx Ultra96, with configuration in ARM PS and membrane processor in FPGA PL.",
      "gaps": [
        "Multi-membrane dissolution/division remains future work.",
        "Bus ordering and probabilistic gathering affect outcomes; synthesis results are not a scaling guarantee."
      ],
      "insight": "Why must newly produced objects wait for a computation-step boundary?",
      "fields": {
        "state": {
          "value": "Object type, active and queued multiplicities",
          "locator": "§5.1",
          "source": "alt-marex-lite"
        },
        "compute": {
          "value": "Rule Container Units",
          "locator": "§5.2",
          "source": "alt-marex-lite"
        },
        "memory": {
          "value": "GOC and rule-local object registers",
          "locator": "Figs. 1–2",
          "source": "alt-marex-lite"
        },
        "control": {
          "value": "MCU; purge and step/end detection",
          "locator": "§§4–5",
          "source": "alt-marex-lite"
        },
        "io": {
          "value": "PS configuration and GOC final state",
          "locator": "§6.3",
          "source": "alt-marex-lite"
        },
        "software": {
          "value": "Loaded P-system rules; MAREX-SIM reference",
          "locator": "§6",
          "source": "alt-marex-lite"
        },
        "workload": {
          "value": "Single-membrane example in §6.1",
          "locator": "§6.3",
          "source": "alt-marex-lite"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Object circulation around rule containers",
        "scope": "One membrane in programmable logic; one representative RCU expanded. This is electronic emulation, not physical biological membranes.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "ps",
            "label": "ARM processing system",
            "subtitle": "CONFIGURATION",
            "text": "Loads object/rule definitions.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-marex-lite",
            "locator": "§6.3",
            "control": false
          },
          {
            "id": "mcu",
            "label": "Membrane control",
            "subtitle": "MCU",
            "text": "Coordinates processing.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-marex-lite",
            "locator": "§4",
            "control": true
          },
          {
            "id": "goc",
            "label": "Global Object Container",
            "subtitle": "ACTIVE / QUEUED",
            "text": "Stores object multiplicities.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-marex-lite",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "bus",
            "label": "Object Circulating Bus",
            "subtitle": "DAISY CHAIN",
            "text": "Carries object containers.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-marex-lite",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "lhs",
            "label": "Rule LHS registers",
            "subtitle": "GATHER / PURGE",
            "text": "Collects required objects.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-marex-lite",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "rcu",
            "label": "Rule control unit",
            "subtitle": "EXECUTE",
            "text": "Tests conditions and counts.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-marex-lite",
            "locator": "§5.2",
            "control": true
          },
          {
            "id": "rhs",
            "label": "Rule RHS registers",
            "subtitle": "QUEUED PRODUCTS",
            "text": "Stages newly produced objects.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-marex-lite",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "others",
            "label": "Other rule units",
            "subtitle": "PARALLEL OPPORTUNITY",
            "text": "Process circulating objects.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-marex-lite",
            "locator": "§7.3",
            "control": false
          },
          {
            "id": "step",
            "label": "Step / end detection",
            "subtitle": "BOUNDARY SIGNALS",
            "text": "Promotes queued counts or stops.",
            "x": 30,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-marex-lite",
            "locator": "§4; §6.2",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "ps",
            "to": "mcu",
            "type": "control",
            "locator": "§6.3",
            "label": "",
            "source": "alt-marex-lite"
          },
          {
            "from": "ps",
            "to": "goc",
            "type": "control",
            "locator": "§6.3",
            "label": "",
            "source": "alt-marex-lite"
          },
          {
            "from": "goc",
            "to": "bus",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-marex-lite"
          },
          {
            "from": "bus",
            "to": "lhs",
            "type": "data",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-marex-lite"
          },
          {
            "from": "lhs",
            "to": "rcu",
            "type": "control",
            "locator": "§5.2",
            "label": "",
            "source": "alt-marex-lite"
          },
          {
            "from": "rcu",
            "to": "rhs",
            "type": "control",
            "locator": "§5.2",
            "label": "",
            "source": "alt-marex-lite"
          },
          {
            "from": "rhs",
            "to": "bus",
            "type": "data",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-marex-lite"
          },
          {
            "from": "bus",
            "to": "others",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-marex-lite"
          },
          {
            "from": "others",
            "to": "goc",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-marex-lite"
          },
          {
            "from": "goc",
            "to": "step",
            "type": "control",
            "locator": "§4",
            "label": "",
            "source": "alt-marex-lite"
          },
          {
            "from": "step",
            "to": "goc",
            "type": "control",
            "locator": "§4",
            "label": "next computation step",
            "source": "alt-marex-lite"
          },
          {
            "from": "mcu",
            "to": "rcu",
            "type": "control",
            "locator": "§4",
            "label": "",
            "source": "alt-marex-lite"
          }
        ]
      },
      "originalCandidate": "Membrane-computing realizations"
    },
    {
      "id": "queue-172",
      "name": "Bennett three-tape reversible Turing machine",
      "organization": "IBM Research",
      "year": 1973,
      "yearLabel": "1973 theoretical construction",
      "kind": "Formal computational model",
      "status": "dossier",
      "track": "other",
      "trackName": "Reversible, stochastic & unusual media",
      "discoveryParadigms": [
        "unconventional",
        "reversible"
      ],
      "paradigms": [
        "digital",
        "reversible"
      ],
      "architectures": [
        "reversible-arch"
      ],
      "substrates": [],
      "models": [
        "turing",
        "reversible-model"
      ],
      "aliases": [],
      "sources": [
        "alt-bennett1973"
      ],
      "summary": "A reversible simulator records computation history, copies its result, and retraces the computation to clean temporary state.",
      "config": "The three-tape construction and Table 1 in Bennett (1973); no built machine or energy measurement is claimed.",
      "gaps": [
        "Logical reversibility alone is not an experimental claim of zero dissipation.",
        "Temporary history storage can grow with simulated time; later space-saving schemes are separate constructions."
      ],
      "insight": "Why does copying output before retracing avoid erasing the answer?",
      "fields": {
        "state": {
          "value": "Control state, heads, and three tapes",
          "locator": "Theorem; Table 1",
          "source": "alt-bennett1973"
        },
        "compute": {
          "value": "Reversible transition rules",
          "locator": "Proof",
          "source": "alt-bennett1973"
        },
        "memory": {
          "value": "Working, history, and output tapes",
          "locator": "Table 1",
          "source": "alt-bennett1973"
        },
        "control": {
          "value": "Forward, copy, and retrace stages",
          "locator": "Table 1",
          "source": "alt-bennett1973"
        },
        "io": {
          "value": "Input retained; desired output written separately",
          "locator": "Theorem",
          "source": "alt-bennett1973"
        },
        "software": {
          "value": "Compiled reversible simulator of a deterministic machine",
          "locator": "Proof",
          "source": "alt-bennett1973"
        },
        "workload": {
          "value": "General terminating deterministic computation",
          "locator": "Theorem",
          "source": "alt-bennett1973"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Compute → copy → uncompute",
        "scope": "Abstract information-flow stages and tapes. Lines are logical dependencies, not physical devices or wiring.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "input",
            "label": "Input configuration",
            "subtitle": "FORMAL DATA",
            "text": "Initializes the working tape.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-bennett1973",
            "locator": "Theorem",
            "control": false
          },
          {
            "id": "forward",
            "label": "Forward simulation",
            "subtitle": "STAGE 1",
            "text": "Records every simulated transition.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-bennett1973",
            "locator": "Table 1",
            "control": false
          },
          {
            "id": "working",
            "label": "Working tape",
            "subtitle": "INTERMEDIATE RESULT",
            "text": "Holds simulated tape contents.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-bennett1973",
            "locator": "Table 1",
            "control": false
          },
          {
            "id": "history",
            "label": "History tape",
            "subtitle": "TRANSITION RECORD",
            "text": "Retains information for inversion.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-bennett1973",
            "locator": "Proof",
            "control": false
          },
          {
            "id": "copy",
            "label": "Reversible copy",
            "subtitle": "STAGE 2",
            "text": "Copies the desired output.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-bennett1973",
            "locator": "Table 1",
            "control": false
          },
          {
            "id": "output",
            "label": "Output tape",
            "subtitle": "RETAINED ANSWER",
            "text": "Keeps the copied result.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-bennett1973",
            "locator": "Theorem",
            "control": false
          },
          {
            "id": "reverse",
            "label": "Retrace simulation",
            "subtitle": "STAGE 3",
            "text": "Runs inverse transitions.",
            "x": 460,
            "y": 370,
            "w": 160,
            "h": 62,
            "source": "alt-bennett1973",
            "locator": "Table 1",
            "control": false
          },
          {
            "id": "restored",
            "label": "Restored input",
            "subtitle": "CLEAN HISTORY",
            "text": "Leaves input and output only.",
            "x": 245,
            "y": 370,
            "w": 160,
            "h": 62,
            "source": "alt-bennett1973",
            "locator": "Theorem",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "input",
            "to": "forward",
            "type": "data",
            "locator": "Theorem",
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          },
          {
            "from": "forward",
            "to": "working",
            "type": "data",
            "locator": "Proof",
            "label": "",
            "source": "alt-bennett1973"
          },
          {
            "from": "forward",
            "to": "history",
            "type": "data",
            "locator": "Proof",
            "label": "",
            "source": "alt-bennett1973"
          },
          {
            "from": "working",
            "to": "copy",
            "type": "data",
            "locator": "Table 1",
            "label": "",
            "source": "alt-bennett1973"
          },
          {
            "from": "copy",
            "to": "output",
            "type": "data",
            "locator": "Table 1",
            "label": "",
            "source": "alt-bennett1973"
          },
          {
            "from": "copy",
            "to": "reverse",
            "type": "control",
            "locator": "Table 1",
            "label": "",
            "source": "alt-bennett1973"
          },
          {
            "from": "history",
            "to": "reverse",
            "type": "data",
            "locator": "Proof",
            "label": "",
            "source": "alt-bennett1973"
          },
          {
            "from": "working",
            "to": "reverse",
            "type": "data",
            "locator": "Table 1",
            "label": "",
            "source": "alt-bennett1973"
          },
          {
            "from": "reverse",
            "to": "restored",
            "type": "data",
            "locator": "Theorem",
            "label": "",
            "source": "alt-bennett1973"
          },
          {
            "from": "output",
            "to": "restored",
            "type": "association",
            "locator": "Theorem",
            "label": "retained separately",
            "source": "alt-bennett1973"
          }
        ]
      },
      "originalCandidate": "Bennett reversible Turing machine (model)"
    },
    {
      "id": "queue-173",
      "name": "Fredkin–Toffoli billiard-ball model",
      "organization": "MIT Laboratory for Computer Science",
      "year": 1982,
      "yearLabel": "1982 journal model",
      "kind": "Idealized physical computational model",
      "status": "dossier",
      "track": "other",
      "trackName": "Reversible, stochastic & unusual media",
      "discoveryParadigms": [
        "unconventional",
        "reversible"
      ],
      "paradigms": [
        "digital",
        "reversible",
        "unconventional"
      ],
      "architectures": [
        "reversible-arch",
        "mechanical"
      ],
      "substrates": [
        "mechanical"
      ],
      "models": [
        "reversible-model"
      ],
      "aliases": [],
      "sources": [
        "alt-billiard"
      ],
      "summary": "Ideal elastic collisions and fixed mirrors implement conservative logical networks through ball-presence encodings.",
      "config": "The idealized two-dimensional hard-ball model in Conservative Logic §§6.1–6.4, not a constructed mechanical computer.",
      "gaps": [
        "Perfect rigidity, elasticity, and arrival timing are idealizations.",
        "A model of reversible mechanics does not demonstrate a practical zero-energy computer."
      ],
      "insight": "How do timing and geometry become part of a logical circuit?",
      "fields": {
        "state": {
          "value": "Presence or absence of balls on timed paths",
          "locator": "§6.1",
          "source": "alt-billiard"
        },
        "compute": {
          "value": "Elastic collision interaction gates",
          "locator": "§6.2",
          "source": "alt-billiard"
        },
        "memory": {
          "value": "Ball trajectories and optional feedback circuits",
          "locator": "§6; conservative-network discussion",
          "source": "alt-billiard"
        },
        "control": {
          "value": "Initial conditions, mirror layout, synchronized arrival",
          "locator": "§6.1–3",
          "source": "alt-billiard"
        },
        "io": {
          "value": "Input/output path occupation",
          "locator": "Figs. 13–14",
          "source": "alt-billiard"
        },
        "software": {
          "value": "Conservative circuit translated to physical geometry",
          "locator": "§6",
          "source": "alt-billiard"
        },
        "workload": {
          "value": "Conservative universal logical constructions",
          "locator": "§6.4",
          "source": "alt-billiard"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "From timed paths to conservative gates",
        "scope": "Construction relationships and ideal signal paths. The diagram does not claim fabrication, tolerance, or energy performance.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "initial",
            "label": "Initial conditions",
            "subtitle": "INPUT ENCODING",
            "text": "Places balls on timed paths.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-billiard",
            "locator": "§6.1",
            "control": false
          },
          {
            "id": "path",
            "label": "Ball paths",
            "subtitle": "POTENTIAL WIRES",
            "text": "Carry presence/absence signals.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-billiard",
            "locator": "§6.3",
            "control": false
          },
          {
            "id": "collision",
            "label": "Interaction gate",
            "subtitle": "ELASTIC COLLISION",
            "text": "Changes paths when two balls meet.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-billiard",
            "locator": "§6.2",
            "control": false
          },
          {
            "id": "mirror",
            "label": "Fixed mirrors",
            "subtitle": "ROUTING",
            "text": "Deflect, delay, or cross paths.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-billiard",
            "locator": "§6.3",
            "control": false
          },
          {
            "id": "switch",
            "label": "Switch construction",
            "subtitle": "CONDITIONAL ROUTE",
            "text": "Steers a signal using another.",
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            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-billiard",
            "locator": "§6.4",
            "control": false
          },
          {
            "id": "fredkin",
            "label": "Fredkin gate",
            "subtitle": "CONSERVATIVE LOGIC",
            "text": "Composes interaction/switch primitives.",
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            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-billiard",
            "locator": "§6.4",
            "control": false
          },
          {
            "id": "output",
            "label": "Output paths",
            "subtitle": "OBSERVED BITS",
            "text": "Encode logical results by occupancy.",
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            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-billiard",
            "locator": "Figs. 14–18",
            "control": false
          },
          {
            "id": "timing",
            "label": "Arrival timing",
            "subtitle": "GEOMETRIC CONSTRAINT",
            "text": "Aligns the intended collisions.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-billiard",
            "locator": "§6.3",
            "control": true
          }
        ],
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          {
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          },
          {
            "from": "path",
            "to": "collision",
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          },
          {
            "from": "mirror",
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          },
          {
            "from": "timing",
            "to": "collision",
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            "label": "",
            "source": "alt-billiard"
          },
          {
            "from": "timing",
            "to": "mirror",
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            "label": "delay geometry",
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          },
          {
            "from": "collision",
            "to": "switch",
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            "source": "alt-billiard"
          },
          {
            "from": "switch",
            "to": "fredkin",
            "type": "association",
            "locator": "§6.4",
            "label": "construction",
            "source": "alt-billiard"
          },
          {
            "from": "fredkin",
            "to": "output",
            "type": "data",
            "locator": "Fig. 18",
            "label": "",
            "source": "alt-billiard"
          },
          {
            "from": "collision",
            "to": "output",
            "type": "data",
            "locator": "Fig. 14",
            "label": "",
            "source": "alt-billiard"
          },
          {
            "from": "mirror",
            "to": "output",
            "type": "association",
            "locator": "§6.3",
            "label": "",
            "source": "alt-billiard"
          }
        ]
      },
      "originalCandidate": "Fredkin–Toffoli billiard-ball computer (model)"
    },
    {
      "id": "queue-174",
      "name": "SCAL-D eight-bit energy-recovery multiplier",
      "organization": "University of Michigan / IBM",
      "year": 2003,
      "yearLabel": "2003 detailed experimental paper",
      "kind": "Fabricated CMOS arithmetic prototype",
      "status": "dossier",
      "track": "other",
      "trackName": "Reversible, stochastic & unusual media",
      "discoveryParadigms": [
        "unconventional",
        "reversible"
      ],
      "paradigms": [
        "digital"
      ],
      "architectures": [
        "pipelined",
        "reversible-arch"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "register"
      ],
      "aliases": [],
      "sources": [
        "alt-scald-multiplier"
      ],
      "summary": "A single sinusoidal power-clock drives pipelined arithmetic and built-in self-test using charge recovery.",
      "config": "0.5 µm SCAL-D chip in the 2003 paper; integrated-clock and external-clock instances are distinguished.",
      "gaps": [
        "Power-clock generation and interfaces dissipate energy.",
        "This is an arithmetic chip, not a general reversible computer."
      ],
      "insight": "Which energy costs remain after recovering charge?",
      "fields": {
        "state": {
          "value": "Dual-rail dynamic voltages",
          "locator": "§II",
          "source": "alt-scald-multiplier"
        },
        "compute": {
          "value": "Eight-bit unsigned carry-save multiplication",
          "locator": "§IV",
          "source": "alt-scald-multiplier"
        },
        "memory": {
          "value": "Gate state and BILBO registers",
          "locator": "§IV.A",
          "source": "alt-scald-multiplier"
        },
        "control": {
          "value": "Power-clock and self-test modes",
          "locator": "Fig. 4",
          "source": "alt-scald-multiplier"
        },
        "io": {
          "value": "Adiabatic-to-digital conversion and pads",
          "locator": "§VII",
          "source": "alt-scald-multiplier"
        },
        "software": {
          "value": "Fixed arithmetic; hardware self-test",
          "locator": "§IV.A",
          "source": "alt-scald-multiplier"
        },
        "workload": {
          "value": "Multiplication and signature testing",
          "locator": "§VII",
          "source": "alt-scald-multiplier"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Arithmetic, self-test and the power-clock boundary",
        "scope": "Functional blocks of the fabricated chip; charge recovery does not establish logical reversibility.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "clock",
            "label": "Sinusoidal power-clock",
            "subtitle": "ENERGY + TIMING",
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            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-scald-multiplier",
            "locator": "§IV.B; §VII",
            "control": false
          },
          {
            "id": "control",
            "label": "Self-test controller",
            "subtitle": "MODE SIGNALS",
            "text": "Selects latch or test behavior.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-scald-multiplier",
            "locator": "Fig. 4",
            "control": true
          },
          {
            "id": "bilbo1",
            "label": "BILBO-1",
            "subtitle": "INPUT STATE",
            "text": "Latch / pseudorandom generator.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-scald-multiplier",
            "locator": "§IV.A",
            "control": false
          },
          {
            "id": "multiply",
            "label": "SCAL-D multiplier",
            "subtitle": "PIPELINED CARRY SAVE",
            "text": "Computes unsigned product.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-scald-multiplier",
            "locator": "§IV.A",
            "control": false
          },
          {
            "id": "bilbo2",
            "label": "BILBO-2",
            "subtitle": "OUTPUT STATE",
            "text": "Latch / signature compression.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-scald-multiplier",
            "locator": "§IV.A",
            "control": false
          },
          {
            "id": "convert",
            "label": "Adiabatic → digital",
            "subtitle": "OBSERVATION INTERFACE",
            "text": "Converts critical signals.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-scald-multiplier",
            "locator": "§VII",
            "control": false
          },
          {
            "id": "pads",
            "label": "Pads / oscilloscope",
            "subtitle": "EXTERNAL READOUT",
            "text": "Checks input/output sequences.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-scald-multiplier",
            "locator": "§VII",
            "control": false
          },
          {
            "id": "bias",
            "label": "Bias and DC supplies",
            "subtitle": "OPERATING POINT",
            "text": "Sets gate currents.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-scald-multiplier",
            "locator": "§II; §VII",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "clock",
            "to": "bilbo1",
            "type": "control",
            "locator": "Fig. 4",
            "label": "",
            "source": "alt-scald-multiplier"
          },
          {
            "from": "clock",
            "to": "multiply",
            "type": "control",
            "locator": "Fig. 4",
            "label": "",
            "source": "alt-scald-multiplier"
          },
          {
            "from": "clock",
            "to": "bilbo2",
            "type": "control",
            "locator": "Fig. 4",
            "label": "",
            "source": "alt-scald-multiplier"
          },
          {
            "from": "control",
            "to": "bilbo1",
            "type": "control",
            "locator": "§IV.A",
            "label": "",
            "source": "alt-scald-multiplier"
          },
          {
            "from": "control",
            "to": "bilbo2",
            "type": "control",
            "locator": "§IV.A",
            "label": "",
            "source": "alt-scald-multiplier"
          },
          {
            "from": "bilbo1",
            "to": "multiply",
            "type": "data",
            "locator": "Fig. 4",
            "label": "",
            "source": "alt-scald-multiplier"
          },
          {
            "from": "multiply",
            "to": "bilbo2",
            "type": "data",
            "locator": "Fig. 4",
            "label": "",
            "source": "alt-scald-multiplier"
          },
          {
            "from": "bilbo1",
            "to": "convert",
            "type": "data",
            "locator": "§VII",
            "label": "",
            "source": "alt-scald-multiplier"
          },
          {
            "from": "bilbo2",
            "to": "convert",
            "type": "data",
            "locator": "§VII",
            "label": "",
            "source": "alt-scald-multiplier"
          },
          {
            "from": "convert",
            "to": "pads",
            "type": "data",
            "locator": "§VII",
            "label": "",
            "source": "alt-scald-multiplier"
          },
          {
            "from": "bias",
            "to": "multiply",
            "type": "association",
            "locator": "§II",
            "label": "",
            "source": "alt-scald-multiplier"
          }
        ]
      },
      "originalCandidate": "Adiabatic CMOS prototypes"
    },
    {
      "id": "queue-175",
      "name": "RQFP reversible superconducting gate experiment",
      "organization": "Yokohama National University",
      "year": 2014,
      "yearLabel": "September 2014 experimental paper",
      "kind": "Josephson-junction logic experiment",
      "status": "dossier",
      "track": "other",
      "trackName": "Reversible, stochastic & unusual media",
      "discoveryParadigms": [
        "unconventional",
        "reversible"
      ],
      "paradigms": [
        "digital",
        "reversible"
      ],
      "architectures": [
        "reversible-arch"
      ],
      "substrates": [
        "superconducting"
      ],
      "models": [
        "reversible-model",
        "logic"
      ],
      "aliases": [],
      "sources": [
        "alt-rqfp-2014"
      ],
      "summary": "Symmetric splitter and majority networks transfer classical bits under reversible excitation order.",
      "config": "AIST STP2 niobium RQFP gates; Fig. 2γ paired circuit with the second gate physically mirrored.",
      "gaps": [
        "Gate energy was simulated, too small to measure in this experiment.",
        "Readout, refrigeration and control are outside the claimed gate energy."
      ],
      "insight": "What does reversing excitation order demonstrate that a truth table cannot?",
      "fields": {
        "state": {
          "value": "Direction of superconducting output current",
          "locator": "Fig. 1a",
          "source": "alt-rqfp-2014"
        },
        "compute": {
          "value": "Three splitters and three majority gates",
          "locator": "Fig. 1d",
          "source": "alt-rqfp-2014"
        },
        "memory": {
          "value": "AQFP circuit state during excitation",
          "locator": "Fig. 1",
          "source": "alt-rqfp-2014"
        },
        "control": {
          "value": "Three-phase trapezoidal excitation",
          "locator": "Fig. 2",
          "source": "alt-rqfp-2014"
        },
        "io": {
          "value": "Pattern-generator input; dc-SQUID readout",
          "locator": "Fig. 2 caption",
          "source": "alt-rqfp-2014"
        },
        "software": {
          "value": "Fixed reversible gate mapping",
          "locator": "Table 1",
          "source": "alt-rqfp-2014"
        },
        "workload": {
          "value": "Forward/inverse mapping verification",
          "locator": "Fig. 2γ",
          "source": "alt-rqfp-2014"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "A gate followed by its mirrored partner",
        "scope": "Aggregate RQFP construction and experimental readout. These are classical superconducting bits, not qubits.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "pattern",
            "label": "Pattern generator",
            "subtitle": "a, b, c",
            "text": "Applies input currents.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-rqfp-2014",
            "locator": "Fig. 2 caption",
            "control": false
          },
          {
            "id": "split",
            "label": "Three splitter gates",
            "subtitle": "FIRST RQFP",
            "text": "Distributes input state.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-rqfp-2014",
            "locator": "Fig. 1d",
            "control": false
          },
          {
            "id": "major",
            "label": "Three majority gates",
            "subtitle": "FIRST RQFP",
            "text": "Forms reversible outputs.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-rqfp-2014",
            "locator": "Fig. 1d",
            "control": false
          },
          {
            "id": "mirror",
            "label": "Mirrored RQFP",
            "subtitle": "REVERSE DATA DIRECTION",
            "text": "Recovers original triplet.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-rqfp-2014",
            "locator": "Fig. 2γ",
            "control": false
          },
          {
            "id": "excite",
            "label": "Excitation phases",
            "subtitle": "ORDERED DRIVE",
            "text": "Controls propagation direction.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-rqfp-2014",
            "locator": "Figs. 1–2",
            "control": true
          },
          {
            "id": "helium",
            "label": "Liquid-helium environment",
            "subtitle": "4.2 K",
            "text": "Supports superconducting circuit.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-rqfp-2014",
            "locator": "Fig. 2 caption",
            "control": false
          },
          {
            "id": "squid",
            "label": "dc-SQUID detectors",
            "subtitle": "a″, b″, c″",
            "text": "Senses output currents.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-rqfp-2014",
            "locator": "Fig. 2 caption",
            "control": false
          },
          {
            "id": "amps",
            "label": "Differential amplifiers",
            "subtitle": "EXTERNAL READOUT",
            "text": "Amplifies detector voltages.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-rqfp-2014",
            "locator": "Fig. 2 caption",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "pattern",
            "to": "split",
            "type": "data",
            "locator": "Fig. 2γ",
            "label": "",
            "source": "alt-rqfp-2014"
          },
          {
            "from": "split",
            "to": "major",
            "type": "data",
            "locator": "Fig. 1d",
            "label": "",
            "source": "alt-rqfp-2014"
          },
          {
            "from": "major",
            "to": "mirror",
            "type": "data",
            "locator": "Fig. 2γ",
            "label": "",
            "source": "alt-rqfp-2014"
          },
          {
            "from": "mirror",
            "to": "squid",
            "type": "data",
            "locator": "Fig. 2γ",
            "label": "",
            "source": "alt-rqfp-2014"
          },
          {
            "from": "squid",
            "to": "amps",
            "type": "data",
            "locator": "Fig. 2 caption",
            "label": "",
            "source": "alt-rqfp-2014"
          },
          {
            "from": "excite",
            "to": "split",
            "type": "control",
            "locator": "Fig. 1d",
            "label": "",
            "source": "alt-rqfp-2014"
          },
          {
            "from": "excite",
            "to": "major",
            "type": "control",
            "locator": "Fig. 1d",
            "label": "",
            "source": "alt-rqfp-2014"
          },
          {
            "from": "excite",
            "to": "mirror",
            "type": "control",
            "locator": "Fig. 2γ",
            "label": "",
            "source": "alt-rqfp-2014"
          },
          {
            "from": "helium",
            "to": "split",
            "type": "association",
            "locator": "Fig. 2 caption",
            "label": "",
            "source": "alt-rqfp-2014"
          },
          {
            "from": "helium",
            "to": "mirror",
            "type": "association",
            "locator": "Fig. 2 caption",
            "label": "",
            "source": "alt-rqfp-2014"
          }
        ]
      },
      "originalCandidate": "Reversible superconducting logic prototypes"
    },
    {
      "id": "queue-176",
      "name": "Borders eight-magnetic-p-bit factoring experiment",
      "organization": "Tohoku University / Purdue University",
      "year": 2019,
      "yearLabel": "September 2019 experiment",
      "kind": "Magnetic–electronic probabilistic prototype",
      "status": "dossier",
      "track": "other",
      "trackName": "Reversible, stochastic & unusual media",
      "discoveryParadigms": [
        "unconventional",
        "probabilistic"
      ],
      "paradigms": [
        "probabilistic",
        "hybrid"
      ],
      "architectures": [
        "pbit",
        "heterogeneous"
      ],
      "substrates": [
        "magnetic",
        "transistor",
        "integrated"
      ],
      "models": [
        "ising"
      ],
      "aliases": [],
      "sources": [
        "alt-magnetic-pbits-2019"
      ],
      "summary": "Fluctuating magnetic devices provide randomness while a microcontroller computes interactions and drives analogue biases.",
      "config": "2019 asynchronous network, up to eight correlated magnetic p-bits; factorization examples extend to 945.",
      "gaps": [
        "Finite examples do not establish efficient large-number factoring.",
        "Microcontroller/DAC costs belong to the physical prototype; p-bits are not coherent qubits."
      ],
      "insight": "Where are the synaptic interactions actually computed?",
      "fields": {
        "state": {
          "value": "Classical fluctuating binary p-bits",
          "locator": "Abstract",
          "source": "alt-magnetic-pbits-2019"
        },
        "compute": {
          "value": "Stochastic MTJs plus electronic feedback",
          "locator": "Extended Data Fig. 2",
          "source": "alt-magnetic-pbits-2019"
        },
        "memory": {
          "value": "Interaction parameters and sampled state",
          "locator": "Extended Data Figs. 2; 6",
          "source": "alt-magnetic-pbits-2019"
        },
        "control": {
          "value": "Microcontroller and calibrated biases",
          "locator": "Extended Data Figs. 2; 4",
          "source": "alt-magnetic-pbits-2019"
        },
        "io": {
          "value": "DAC voltages; sampled p-bit outputs",
          "locator": "Extended Data Fig. 2",
          "source": "alt-magnetic-pbits-2019"
        },
        "software": {
          "value": "Encoded factoring objective",
          "locator": "Abstract; Extended Data Fig. 6",
          "source": "alt-magnetic-pbits-2019"
        },
        "workload": {
          "value": "Small-integer factorization",
          "locator": "Abstract",
          "source": "alt-magnetic-pbits-2019"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Magnetic randomness inside a classical feedback loop",
        "scope": "Publicly documented system boundary; no hidden all-to-all magnetic coupling is inferred.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "objective",
            "label": "Factoring objective",
            "subtitle": "ENCODED INTERACTIONS",
            "text": "Sets correlated-state problem.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-magnetic-pbits-2019",
            "locator": "Abstract; Extended Data Fig. 6",
            "control": false
          },
          {
            "id": "micro",
            "label": "Microcontroller",
            "subtitle": "INTERACTION COMPUTE",
            "text": "Reads outputs and updates drive.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-magnetic-pbits-2019",
            "locator": "Extended Data Fig. 2",
            "control": true
          },
          {
            "id": "dac",
            "label": "DAC",
            "subtitle": "DIGITAL → ANALOGUE",
            "text": "Produces each input voltage.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-magnetic-pbits-2019",
            "locator": "Extended Data Fig. 2",
            "control": false
          },
          {
            "id": "mtj",
            "label": "Stochastic MTJ p-bits",
            "subtitle": "MAGNETIC RANDOMNESS",
            "text": "Thermally fluctuating devices.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-magnetic-pbits-2019",
            "locator": "Abstract",
            "control": false
          },
          {
            "id": "output",
            "label": "p-bit output voltages",
            "subtitle": "BINARY STATE",
            "text": "Returns current sampled bits.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-magnetic-pbits-2019",
            "locator": "Extended Data Fig. 2",
            "control": false
          },
          {
            "id": "cal",
            "label": "Bias calibration",
            "subtitle": "DEVICE VARIATION",
            "text": "Corrects shifted responses.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-magnetic-pbits-2019",
            "locator": "Extended Data Fig. 4",
            "control": false
          },
          {
            "id": "samples",
            "label": "Joint-state samples",
            "subtitle": "CLASSICAL READOUT",
            "text": "Collects factor configurations.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-magnetic-pbits-2019",
            "locator": "Extended Data Figs. 3; 7",
            "control": false
          },
          {
            "id": "factors",
            "label": "x and y statistics",
            "subtitle": "RESULT",
            "text": "Identifies factor peaks.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-magnetic-pbits-2019",
            "locator": "Extended Data Figs. 3; 6",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "objective",
            "to": "micro",
            "type": "control",
            "locator": "Abstract; Extended Data Fig. 6",
            "label": "",
            "source": "alt-magnetic-pbits-2019"
          },
          {
            "from": "micro",
            "to": "dac",
            "type": "data",
            "locator": "Extended Data Fig. 2",
            "label": "",
            "source": "alt-magnetic-pbits-2019"
          },
          {
            "from": "dac",
            "to": "mtj",
            "type": "control",
            "locator": "Extended Data Fig. 2",
            "label": "",
            "source": "alt-magnetic-pbits-2019"
          },
          {
            "from": "mtj",
            "to": "output",
            "type": "data",
            "locator": "Extended Data Fig. 2",
            "label": "",
            "source": "alt-magnetic-pbits-2019"
          },
          {
            "from": "output",
            "to": "micro",
            "type": "data",
            "locator": "Extended Data Fig. 2",
            "label": "",
            "source": "alt-magnetic-pbits-2019"
          },
          {
            "from": "cal",
            "to": "micro",
            "type": "control",
            "locator": "Extended Data Fig. 4",
            "label": "",
            "source": "alt-magnetic-pbits-2019"
          },
          {
            "from": "output",
            "to": "cal",
            "type": "data",
            "locator": "Extended Data Fig. 4",
            "label": "",
            "source": "alt-magnetic-pbits-2019"
          },
          {
            "from": "output",
            "to": "samples",
            "type": "data",
            "locator": "Extended Data Fig. 3",
            "label": "",
            "source": "alt-magnetic-pbits-2019"
          },
          {
            "from": "samples",
            "to": "factors",
            "type": "data",
            "locator": "Extended Data Fig. 3",
            "label": "",
            "source": "alt-magnetic-pbits-2019"
          },
          {
            "from": "objective",
            "to": "factors",
            "type": "association",
            "locator": "Extended Data Fig. 6",
            "label": "",
            "source": "alt-magnetic-pbits-2019"
          }
        ]
      },
      "originalCandidate": "Magnetic p-bit systems"
    },
    {
      "id": "queue-177",
      "name": "Fernandes stochastic Bayesian FPGA machine",
      "organization": "University of Coimbra research team",
      "year": 2016,
      "yearLabel": "2016 FPL implementation",
      "kind": "FPGA stochastic-arithmetic prototype",
      "status": "dossier",
      "track": "other",
      "trackName": "Reversible, stochastic & unusual media",
      "discoveryParadigms": [
        "unconventional",
        "stochastic"
      ],
      "paradigms": [
        "digital",
        "stochastic",
        "parallel"
      ],
      "architectures": [
        "bitstream",
        "reconfigurable"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "dataflow-model"
      ],
      "aliases": [],
      "sources": [
        "alt-stochastic-bayesian-fpga"
      ],
      "summary": "Parallel AND and OR-plus-memory circuits evaluate Bayesian expressions encoded as bitstream densities.",
      "config": "Cyclone IV EP4CE115F29C7 robot-inference example with five output circuits and 32-bit LFSR stream generation.",
      "gaps": [
        "Longer streams trade time/energy for accuracy.",
        "LFSRs dominate resources; power is estimated, not measured at the supply."
      ],
      "insight": "Why can stream generation cost more area than arithmetic?",
      "fields": {
        "state": {
          "value": "Fraction of ones in a finite stream",
          "locator": "§III.A",
          "source": "alt-stochastic-bayesian-fpga"
        },
        "compute": {
          "value": "AND multiplication; OR+ addition",
          "locator": "§IV",
          "source": "alt-stochastic-bayesian-fpga"
        },
        "memory": {
          "value": "Input/output memories; operator state",
          "locator": "Fig. 2; §III.B",
          "source": "alt-stochastic-bayesian-fpga"
        },
        "control": {
          "value": "Control register and finite run length",
          "locator": "Fig. 2; §IV.A",
          "source": "alt-stochastic-bayesian-fpga"
        },
        "io": {
          "value": "Binary/stream converters and counters",
          "locator": "Fig. 2",
          "source": "alt-stochastic-bayesian-fpga"
        },
        "software": {
          "value": "ProBT model → VHDL toolchain",
          "locator": "§II",
          "source": "alt-stochastic-bayesian-fpga"
        },
        "workload": {
          "value": "Five-valued robot rotation inference",
          "locator": "§IV",
          "source": "alt-stochastic-bayesian-fpga"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Compilation, stochastic arithmetic and binary conversion",
        "scope": "Inference circuit and measurement boundary; finite-stream arithmetic approximates the exact model.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "model",
            "label": "ProBT model",
            "subtitle": "HOST DESIGN",
            "text": "Defines Bayesian expression.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-stochastic-bayesian-fpga",
            "locator": "§II",
            "control": false
          },
          {
            "id": "vhdl",
            "label": "VHDL compilation",
            "subtitle": "FABRIC CONFIGURATION",
            "text": "Instantiates operator graph.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-stochastic-bayesian-fpga",
            "locator": "§II",
            "control": false
          },
          {
            "id": "memory",
            "label": "Input memory",
            "subtitle": "BINARY PROBABILITIES",
            "text": "Stores parameters/evidence.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-stochastic-bayesian-fpga",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "lfsr",
            "label": "32-bit LFSRs",
            "subtitle": "PSEUDORANDOM SOURCES",
            "text": "Drives stream conversion.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-stochastic-bayesian-fpga",
            "locator": "§IV",
            "control": false
          },
          {
            "id": "convert",
            "label": "Binary → stochastic",
            "subtitle": "216 INPUT STREAMS",
            "text": "Encodes probability densities.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-stochastic-bayesian-fpga",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "ops",
            "label": "Five parallel BM circuits",
            "subtitle": "AND / OR+",
            "text": "Evaluates sums and products.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-stochastic-bayesian-fpga",
            "locator": "§IV",
            "control": false
          },
          {
            "id": "count",
            "label": "Accumulator counters",
            "subtitle": "FIVE OUTPUTS",
            "text": "Converts streams to binary.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-stochastic-bayesian-fpga",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "out",
            "label": "Output memory",
            "subtitle": "READOUT",
            "text": "Stores inferred distributions.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-stochastic-bayesian-fpga",
            "locator": "Fig. 2",
            "control": false
          },
          {
            "id": "ctrl",
            "label": "Control register",
            "subtitle": "RUN WINDOW",
            "text": "Controls accumulation.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-stochastic-bayesian-fpga",
            "locator": "Fig. 2",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "model",
            "to": "vhdl",
            "type": "control",
            "locator": "§II",
            "label": "",
            "source": "alt-stochastic-bayesian-fpga"
          },
          {
            "from": "vhdl",
            "to": "ops",
            "type": "control",
            "locator": "§II",
            "label": "",
            "source": "alt-stochastic-bayesian-fpga"
          },
          {
            "from": "memory",
            "to": "convert",
            "type": "data",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-stochastic-bayesian-fpga"
          },
          {
            "from": "lfsr",
            "to": "convert",
            "type": "data",
            "locator": "§IV",
            "label": "",
            "source": "alt-stochastic-bayesian-fpga"
          },
          {
            "from": "convert",
            "to": "ops",
            "type": "data",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-stochastic-bayesian-fpga"
          },
          {
            "from": "ops",
            "to": "count",
            "type": "data",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-stochastic-bayesian-fpga"
          },
          {
            "from": "count",
            "to": "out",
            "type": "data",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-stochastic-bayesian-fpga"
          },
          {
            "from": "ctrl",
            "to": "convert",
            "type": "control",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-stochastic-bayesian-fpga"
          },
          {
            "from": "ctrl",
            "to": "count",
            "type": "control",
            "locator": "Fig. 2",
            "label": "",
            "source": "alt-stochastic-bayesian-fpga"
          },
          {
            "from": "vhdl",
            "to": "lfsr",
            "type": "control",
            "locator": "§II; §IV",
            "label": "",
            "source": "alt-stochastic-bayesian-fpga"
          }
        ]
      },
      "originalCandidate": "Stochastic bitstream processors"
    },
    {
      "id": "queue-178",
      "name": "Prakash–Gershenfeld bubble AND/OR gate",
      "organization": "MIT Center for Bits and Atoms",
      "year": 2007,
      "yearLabel": "February 2007 experiment",
      "kind": "Two-phase microfluidic logic experiment",
      "status": "dossier",
      "track": "other",
      "trackName": "Reversible, stochastic & unusual media",
      "discoveryParadigms": [
        "unconventional"
      ],
      "paradigms": [
        "digital",
        "unconventional"
      ],
      "architectures": [
        "fluidic",
        "configured"
      ],
      "substrates": [
        "fluid"
      ],
      "models": [
        "logic"
      ],
      "aliases": [],
      "sources": [
        "alt-bubble-logic"
      ],
      "summary": "An arriving bubble raises channel resistance and redirects a second bubble, producing simultaneous AND/OR outputs.",
      "config": "Fig. 1 top-row nitrogen/water gate in PDMS channels bonded to Pyrex; other sequential devices are separate demonstrations.",
      "gaps": [
        "Timing and bubble-size constraints affect cascading.",
        "A universal gate family is not evidence of a complete general-purpose fluidic computer."
      ],
      "insight": "Why does this gate have two outputs?",
      "fields": {
        "state": {
          "value": "Bubble presence / absence",
          "locator": "Fig. 1",
          "source": "alt-bubble-logic"
        },
        "compute": {
          "value": "Bubble-dependent hydraulic routing",
          "locator": "p. 833",
          "source": "alt-bubble-logic"
        },
        "memory": {
          "value": "Transient bubble occupancy",
          "locator": "p. 833",
          "source": "alt-bubble-logic"
        },
        "control": {
          "value": "Geometry, pressure and arrival timing",
          "locator": "Fig. 1",
          "source": "alt-bubble-logic"
        },
        "io": {
          "value": "Bubble input/output channels",
          "locator": "Fig. 1",
          "source": "alt-bubble-logic"
        },
        "software": {
          "value": "Fixed channel layout",
          "locator": "Fig. 1",
          "source": "alt-bubble-logic"
        },
        "workload": {
          "value": "Two-input AND and OR",
          "locator": "Fig. 1",
          "source": "alt-bubble-logic"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Bubble occupancy changes the next routing decision",
        "scope": "Functional hydraulic mechanism; edges marked control denote resistance effects, not electronic control.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "a",
            "label": "Input A",
            "subtitle": "BUBBLE BIT",
            "text": "Arrives at junction.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-bubble-logic",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "b",
            "label": "Input B",
            "subtitle": "BUBBLE BIT",
            "text": "May overlap arrival window.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-bubble-logic",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "flow",
            "label": "Pressure-driven medium",
            "subtitle": "WATER + NITROGEN",
            "text": "Carries both input streams.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-bubble-logic",
            "locator": "pp. 832–833",
            "control": false
          },
          {
            "id": "junction",
            "label": "Shared junction",
            "subtitle": "FLOW SELECTION",
            "text": "Routes by instantaneous flow.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-bubble-logic",
            "locator": "p. 833",
            "control": false
          },
          {
            "id": "wide",
            "label": "Wider branch",
            "subtitle": "LOW INITIAL RESISTANCE",
            "text": "Accepts first bubble.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-bubble-logic",
            "locator": "p. 833",
            "control": false
          },
          {
            "id": "occupy",
            "label": "Bubble in wider branch",
            "subtitle": "RESISTANCE INCREASE",
            "text": "Deflects later arrival.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-bubble-logic",
            "locator": "p. 833",
            "control": false
          },
          {
            "id": "other",
            "label": "Other branch",
            "subtitle": "SECOND BUBBLE PATH",
            "text": "Conducts coincident second bit.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-bubble-logic",
            "locator": "p. 833",
            "control": false
          },
          {
            "id": "orout",
            "label": "A OR B",
            "subtitle": "OUTPUT CHANNEL",
            "text": "First bubble output.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-bubble-logic",
            "locator": "Fig. 1",
            "control": false
          },
          {
            "id": "andout",
            "label": "A AND B",
            "subtitle": "OUTPUT CHANNEL",
            "text": "Coincident second output.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-bubble-logic",
            "locator": "Fig. 1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "a",
            "to": "junction",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-bubble-logic"
          },
          {
            "from": "b",
            "to": "junction",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-bubble-logic"
          },
          {
            "from": "flow",
            "to": "junction",
            "type": "association",
            "locator": "pp. 832–833",
            "label": "",
            "source": "alt-bubble-logic"
          },
          {
            "from": "junction",
            "to": "wide",
            "type": "data",
            "locator": "p. 833",
            "label": "",
            "source": "alt-bubble-logic"
          },
          {
            "from": "wide",
            "to": "occupy",
            "type": "data",
            "locator": "p. 833",
            "label": "",
            "source": "alt-bubble-logic"
          },
          {
            "from": "occupy",
            "to": "junction",
            "type": "control",
            "locator": "p. 833",
            "label": "changes hydraulic resistance",
            "source": "alt-bubble-logic"
          },
          {
            "from": "junction",
            "to": "other",
            "type": "data",
            "locator": "p. 833",
            "label": "",
            "source": "alt-bubble-logic"
          },
          {
            "from": "wide",
            "to": "orout",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-bubble-logic"
          },
          {
            "from": "other",
            "to": "andout",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-bubble-logic"
          },
          {
            "from": "a",
            "to": "b",
            "type": "association",
            "locator": "p. 833",
            "label": "finite coincidence window",
            "source": "alt-bubble-logic"
          }
        ]
      },
      "originalCandidate": "Fluidic logic computers"
    },
    {
      "id": "queue-179",
      "name": "Preston two-bit soft pneumatic shift register",
      "organization": "Harvard University research team",
      "year": 2019,
      "yearLabel": "March 2019 publication",
      "kind": "Soft pneumatic sequential-logic experiment",
      "status": "dossier",
      "track": "other",
      "trackName": "Reversible, stochastic & unusual media",
      "discoveryParadigms": [
        "unconventional"
      ],
      "paradigms": [
        "digital",
        "unconventional"
      ],
      "architectures": [
        "fluidic"
      ],
      "substrates": [
        "fluid",
        "mechanical"
      ],
      "models": [
        "register",
        "logic"
      ],
      "aliases": [],
      "sources": [
        "alt-soft-pneumatic"
      ],
      "summary": "Bistable soft valves retain pressure bits while a delayed clock sequences their transfer.",
      "config": "Fig. 5 serial-in/parallel-out two-bit shift register, using two D latches and a pressure follower.",
      "gaps": [
        "Sustained clock high can overwrite data.",
        "No autonomous soft oscillator is claimed for this measured shift-register setup."
      ],
      "insight": "What prevents the first stored bit from being overwritten too early?",
      "fields": {
        "state": {
          "value": "High/low pressure and membrane state",
          "locator": "Figs. 1–2",
          "source": "alt-soft-pneumatic"
        },
        "compute": {
          "value": "Soft NOT, OR and AND gates",
          "locator": "Figs. 2–3",
          "source": "alt-soft-pneumatic"
        },
        "memory": {
          "value": "Two D-latch pressure bits",
          "locator": "Fig. 5",
          "source": "alt-soft-pneumatic"
        },
        "control": {
          "value": "Electronic-regulator clock with pneumatic delay",
          "locator": "Shift Register section",
          "source": "alt-soft-pneumatic"
        },
        "io": {
          "value": "Serial pressure data; parallel Q0/Q1",
          "locator": "Fig. 5",
          "source": "alt-soft-pneumatic"
        },
        "software": {
          "value": "Fixed valve connections",
          "locator": "Fig. 5",
          "source": "alt-soft-pneumatic"
        },
        "workload": {
          "value": "Two-bit shifting demonstration",
          "locator": "Fig. 5C",
          "source": "alt-soft-pneumatic"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "A delayed clock preserves the old first bit",
        "scope": "Latches are aggregate valve circuits; the actual experiment’s clock source remains outside the soft logic boundary.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "data",
            "label": "Serial D",
            "subtitle": "PRESSURE INPUT",
            "text": "Supplies next bit.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-soft-pneumatic",
            "locator": "Fig. 5",
            "control": false
          },
          {
            "id": "clock",
            "label": "Electronic pressure regulator",
            "subtitle": "EXTERNAL CLK",
            "text": "Generates test clock.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-soft-pneumatic",
            "locator": "Shift Register section",
            "control": true
          },
          {
            "id": "delay",
            "label": "Pressure follower",
            "subtitle": "CLOCK DELAY",
            "text": "Delays first-latch update.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-soft-pneumatic",
            "locator": "Fig. 5B",
            "control": false
          },
          {
            "id": "l0",
            "label": "D latch 0",
            "subtitle": "SOFT VALVE LOGIC",
            "text": "Stores incoming bit.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-soft-pneumatic",
            "locator": "Fig. 5",
            "control": false
          },
          {
            "id": "q0",
            "label": "Q0",
            "subtitle": "FIRST STORED BIT",
            "text": "Feeds the second latch.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-soft-pneumatic",
            "locator": "Fig. 5",
            "control": false
          },
          {
            "id": "l1",
            "label": "D latch 1",
            "subtitle": "SOFT VALVE LOGIC",
            "text": "Stores previous Q0.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-soft-pneumatic",
            "locator": "Fig. 5",
            "control": false
          },
          {
            "id": "q1",
            "label": "Q1",
            "subtitle": "SECOND STORED BIT",
            "text": "Parallel pressure output.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-soft-pneumatic",
            "locator": "Fig. 5",
            "control": false
          },
          {
            "id": "trace",
            "label": "Pressure time traces",
            "subtitle": "EXPERIMENTAL READOUT",
            "text": "Checks shifting sequence.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-soft-pneumatic",
            "locator": "Fig. 5C",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "data",
            "to": "l0",
            "type": "data",
            "locator": "Fig. 5B",
            "label": "",
            "source": "alt-soft-pneumatic"
          },
          {
            "from": "clock",
            "to": "delay",
            "type": "control",
            "locator": "Fig. 5B",
            "label": "",
            "source": "alt-soft-pneumatic"
          },
          {
            "from": "delay",
            "to": "l0",
            "type": "control",
            "locator": "Fig. 5B",
            "label": "",
            "source": "alt-soft-pneumatic"
          },
          {
            "from": "clock",
            "to": "l1",
            "type": "control",
            "locator": "Fig. 5B",
            "label": "",
            "source": "alt-soft-pneumatic"
          },
          {
            "from": "l0",
            "to": "q0",
            "type": "data",
            "locator": "Fig. 5B",
            "label": "",
            "source": "alt-soft-pneumatic"
          },
          {
            "from": "q0",
            "to": "l1",
            "type": "data",
            "locator": "Fig. 5B",
            "label": "",
            "source": "alt-soft-pneumatic"
          },
          {
            "from": "l1",
            "to": "q1",
            "type": "data",
            "locator": "Fig. 5B",
            "label": "",
            "source": "alt-soft-pneumatic"
          },
          {
            "from": "q0",
            "to": "trace",
            "type": "data",
            "locator": "Fig. 5C",
            "label": "",
            "source": "alt-soft-pneumatic"
          },
          {
            "from": "q1",
            "to": "trace",
            "type": "data",
            "locator": "Fig. 5C",
            "label": "",
            "source": "alt-soft-pneumatic"
          },
          {
            "from": "clock",
            "to": "trace",
            "type": "association",
            "locator": "Fig. 5C",
            "label": "",
            "source": "alt-soft-pneumatic"
          }
        ]
      },
      "originalCandidate": "Pneumatic logic systems"
    },
    {
      "id": "queue-180",
      "name": "D1 conductive-metamaterial AND gate",
      "organization": "Pennsylvania State University / AFRL",
      "year": 2021,
      "yearLabel": "2021 physical gate experiment",
      "kind": "Mechanical–electrical logic experiment",
      "status": "dossier",
      "track": "other",
      "trackName": "Reversible, stochastic & unusual media",
      "discoveryParadigms": [
        "unconventional"
      ],
      "paradigms": [
        "digital",
        "unconventional",
        "hybrid"
      ],
      "architectures": [
        "mechanical",
        "configured"
      ],
      "substrates": [
        "mechanical"
      ],
      "models": [
        "logic"
      ],
      "aliases": [],
      "sources": [
        "alt-conductive-metamaterial"
      ],
      "summary": "Layer rotation selects self-contacting conductive paths, turning mechanical inputs into an electrical Boolean output.",
      "config": "Two D1 layers, five unit cells per layer; AND network in Figs. 4c and 5a.",
      "gaps": [
        "Higher modes may require manual perturbations.",
        "This is electrically read mechanical logic; large autonomous networks were not demonstrated."
      ],
      "insight": "Which inputs require controlled mechanical mode selection?",
      "fields": {
        "state": {
          "value": "Clockwise/counterclockwise layer rotation",
          "locator": "Fig. 4a–b",
          "source": "alt-conductive-metamaterial"
        },
        "compute": {
          "value": "Series contact switches",
          "locator": "Fig. 4c",
          "source": "alt-conductive-metamaterial"
        },
        "memory": {
          "value": "Configuration during applied deformation",
          "locator": "Figs. 4–5",
          "source": "alt-conductive-metamaterial"
        },
        "control": {
          "value": "Compression, shear and manual perturbation",
          "locator": "Methods",
          "source": "alt-conductive-metamaterial"
        },
        "io": {
          "value": "Mechanical inputs; powered electrical output",
          "locator": "Fig. 4",
          "source": "alt-conductive-metamaterial"
        },
        "software": {
          "value": "Ag-TPU trace topology",
          "locator": "Fig. 4c",
          "source": "alt-conductive-metamaterial"
        },
        "workload": {
          "value": "Two-input AND truth table",
          "locator": "Fig. 5a",
          "source": "alt-conductive-metamaterial"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Mechanical contact implements a series electrical path",
        "scope": "Experimental AND gate with its test boundary. No autonomous mechanical instruction execution is implied.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "load",
            "label": "Load frame / shear",
            "subtitle": "EXTERNAL INPUT",
            "text": "Selects deformation mode.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-conductive-metamaterial",
            "locator": "Methods",
            "control": true
          },
          {
            "id": "a",
            "label": "Top-layer rotation A",
            "subtitle": "MECHANICAL BIT",
            "text": "First input state.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-conductive-metamaterial",
            "locator": "Fig. 4a",
            "control": false
          },
          {
            "id": "b",
            "label": "Bottom-layer rotation B",
            "subtitle": "MECHANICAL BIT",
            "text": "Second input state.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-conductive-metamaterial",
            "locator": "Fig. 4a",
            "control": false
          },
          {
            "id": "ca",
            "label": "Top contact",
            "subtitle": "Ag-TPU NETWORK",
            "text": "Opens or closes first path.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-conductive-metamaterial",
            "locator": "Fig. 4c",
            "control": false
          },
          {
            "id": "cb",
            "label": "Bottom contact",
            "subtitle": "Ag-TPU NETWORK",
            "text": "Opens or closes second path.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-conductive-metamaterial",
            "locator": "Fig. 4c",
            "control": false
          },
          {
            "id": "vcc",
            "label": "Powered terminal",
            "subtitle": "ELECTRICAL SUPPLY",
            "text": "Biases conductive network.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-conductive-metamaterial",
            "locator": "Fig. 4c",
            "control": false
          },
          {
            "id": "q",
            "label": "Output Q",
            "subtitle": "SERIES CONTINUITY",
            "text": "High when both paths close.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-conductive-metamaterial",
            "locator": "Figs. 4c; 5a",
            "control": false
          },
          {
            "id": "read",
            "label": "Divider / NI DAQ",
            "subtitle": "EXTERNAL READOUT",
            "text": "Measures resistance/voltage.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-conductive-metamaterial",
            "locator": "Methods",
            "control": false
          },
          {
            "id": "matlab",
            "label": "MATLAB analysis",
            "subtitle": "TRUTH-TABLE CHECK",
            "text": "Analyzes acquired response.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-conductive-metamaterial",
            "locator": "Methods",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "load",
            "to": "a",
            "type": "control",
            "locator": "Methods",
            "label": "",
            "source": "alt-conductive-metamaterial"
          },
          {
            "from": "load",
            "to": "b",
            "type": "control",
            "locator": "Methods",
            "label": "",
            "source": "alt-conductive-metamaterial"
          },
          {
            "from": "a",
            "to": "ca",
            "type": "control",
            "locator": "Fig. 4c",
            "label": "",
            "source": "alt-conductive-metamaterial"
          },
          {
            "from": "b",
            "to": "cb",
            "type": "control",
            "locator": "Fig. 4c",
            "label": "",
            "source": "alt-conductive-metamaterial"
          },
          {
            "from": "vcc",
            "to": "ca",
            "type": "data",
            "locator": "Fig. 4c",
            "label": "",
            "source": "alt-conductive-metamaterial"
          },
          {
            "from": "ca",
            "to": "cb",
            "type": "data",
            "locator": "Fig. 4c",
            "label": "series connection",
            "source": "alt-conductive-metamaterial"
          },
          {
            "from": "cb",
            "to": "q",
            "type": "data",
            "locator": "Fig. 4c",
            "label": "",
            "source": "alt-conductive-metamaterial"
          },
          {
            "from": "q",
            "to": "read",
            "type": "data",
            "locator": "Methods",
            "label": "",
            "source": "alt-conductive-metamaterial"
          },
          {
            "from": "read",
            "to": "matlab",
            "type": "data",
            "locator": "Methods",
            "label": "",
            "source": "alt-conductive-metamaterial"
          },
          {
            "from": "a",
            "to": "b",
            "type": "association",
            "locator": "Fig. 4b",
            "label": "four deformation modes",
            "source": "alt-conductive-metamaterial"
          }
        ]
      },
      "originalCandidate": "Mechanical metamaterial logic"
    },
    {
      "id": "queue-181",
      "name": "CAM-8 eight-module prototype",
      "organization": "MIT Laboratory for Computer Science",
      "year": 1993,
      "yearLabel": "December 1993 report; posted 1995",
      "kind": "Built cellular-automata computer",
      "status": "dossier",
      "track": "other",
      "trackName": "Reversible, stochastic & unusual media",
      "discoveryParadigms": [
        "unconventional"
      ],
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "architectures": [
        "simd",
        "distributed",
        "pipelined",
        "cellular-arch"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "cellular"
      ],
      "aliases": [],
      "sources": [
        "alt-cam8"
      ],
      "summary": "Time-shared spatial sites stream through local lookup tables while scheduled shifts exchange bit fields across a mesh.",
      "config": "Eight-module 25 MHz prototype: 64 MB DRAM site state and 2 MB SRAM lookup storage.",
      "gaps": [
        "Virtual cells are not individual physical processors.",
        "Large scalability claims exceed the documented eight-module implementation."
      ],
      "insight": "How does changing scan addresses emulate movement through a lattice?",
      "fields": {
        "state": {
          "value": "Bit fields at virtual lattice sites",
          "locator": "§2.2",
          "source": "alt-cam8"
        },
        "compute": {
          "value": "Sixteen-bit table-lookup interactions",
          "locator": "§2.2.3",
          "source": "alt-cam8"
        },
        "memory": {
          "value": "DRAM state; double-buffered SRAM tables",
          "locator": "§2.1",
          "source": "alt-cam8"
        },
        "control": {
          "value": "Lockstep scans; programmable shift parameters",
          "locator": "§2.1",
          "source": "alt-cam8"
        },
        "io": {
          "value": "Workstation tree and six-neighbor mesh",
          "locator": "§2.1",
          "source": "alt-cam8"
        },
        "software": {
          "value": "Space-time event programs",
          "locator": "§2.2.3",
          "source": "alt-cam8"
        },
        "workload": {
          "value": "Lattice-gas and spatial simulations",
          "locator": "§3",
          "source": "alt-cam8"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "Movement and interaction share one streaming pass",
        "scope": "One hardware module and surrounding system links; multiple virtual sites share its datapath.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "host",
            "label": "Front-end workstation",
            "subtitle": "EXPERIMENT CONTROL",
            "text": "Loads rules and parameters.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-cam8",
            "locator": "§2.1",
            "control": true
          },
          {
            "id": "tree",
            "label": "Broadcast / readback tree",
            "subtitle": "HOST INTERFACE",
            "text": "Reaches selected modules.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-cam8",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "params",
            "label": "Per-module scan parameters",
            "subtitle": "LOCKSTEP CONTROL",
            "text": "Sets relative bit-slice offsets.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-cam8",
            "locator": "§2.1",
            "control": true
          },
          {
            "id": "dram",
            "label": "DRAM bit slices",
            "subtitle": "SPATIAL STATE",
            "text": "Streams predictable site order.",
            "x": 30,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-cam8",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "move",
            "label": "Addressing + static routing",
            "subtitle": "FIELD MOVEMENT",
            "text": "Aligns arriving site bits.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-cam8",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "lut",
            "label": "Double-buffered SRAM LUT",
            "subtitle": "LOCAL INTERACTION",
            "text": "Transforms sixteen input bits.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-cam8",
            "locator": "§2.1; §2.2.3",
            "control": false
          },
          {
            "id": "mesh",
            "label": "Six-neighbor links",
            "subtitle": "INTERMODULE MOVEMENT",
            "text": "Exchanges boundary fields.",
            "x": 245,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-cam8",
            "locator": "§2.1",
            "control": false
          },
          {
            "id": "stats",
            "label": "Statistics hardware",
            "subtitle": "ANALYSIS",
            "text": "Accumulates local event counts.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-cam8",
            "locator": "§3.1",
            "control": false
          },
          {
            "id": "display",
            "label": "Workstation visualization",
            "subtitle": "READOUT",
            "text": "Plots reported observables.",
            "x": 675,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-cam8",
            "locator": "§3.1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "host",
            "to": "tree",
            "type": "control",
            "locator": "§2.1",
            "label": "",
            "source": "alt-cam8"
          },
          {
            "from": "tree",
            "to": "params",
            "type": "control",
            "locator": "§2.1",
            "label": "",
            "source": "alt-cam8"
          },
          {
            "from": "tree",
            "to": "lut",
            "type": "control",
            "locator": "§2.1",
            "label": "",
            "source": "alt-cam8"
          },
          {
            "from": "params",
            "to": "move",
            "type": "control",
            "locator": "§2.1",
            "label": "",
            "source": "alt-cam8"
          },
          {
            "from": "dram",
            "to": "move",
            "type": "data",
            "locator": "§2.1",
            "label": "",
            "source": "alt-cam8"
          },
          {
            "from": "move",
            "to": "lut",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-cam8"
          },
          {
            "from": "lut",
            "to": "dram",
            "type": "data",
            "locator": "Fig. 1",
            "label": "",
            "source": "alt-cam8"
          },
          {
            "from": "move",
            "to": "mesh",
            "type": "data",
            "locator": "§2.1",
            "label": "",
            "source": "alt-cam8"
          },
          {
            "from": "mesh",
            "to": "move",
            "type": "data",
            "locator": "§2.1",
            "label": "",
            "source": "alt-cam8"
          },
          {
            "from": "lut",
            "to": "stats",
            "type": "data",
            "locator": "§3.1",
            "label": "",
            "source": "alt-cam8"
          },
          {
            "from": "stats",
            "to": "tree",
            "type": "data",
            "locator": "§3.1",
            "label": "",
            "source": "alt-cam8"
          },
          {
            "from": "tree",
            "to": "display",
            "type": "data",
            "locator": "§3.1",
            "label": "",
            "source": "alt-cam8"
          }
        ]
      },
      "originalCandidate": "Cellular-automaton hardware"
    },
    {
      "id": "queue-182",
      "name": "Lent five-dot QCA logic proposal",
      "organization": "University of Notre Dame",
      "year": 1993,
      "yearLabel": "1993 proposal and calculations",
      "kind": "Quantum-dot binary-logic architecture proposal",
      "status": "dossier",
      "track": "other",
      "trackName": "Reversible, stochastic & unusual media",
      "discoveryParadigms": [
        "unconventional"
      ],
      "paradigms": [
        "digital",
        "unconventional"
      ],
      "architectures": [
        "cellular-arch"
      ],
      "substrates": [
        "integrated"
      ],
      "models": [
        "cellular",
        "logic"
      ],
      "aliases": [],
      "sources": [
        "alt-qca-1993"
      ],
      "summary": "Electrostatically fixed boundary cells bias an interacting dot array whose relaxed polarization encodes a Boolean result.",
      "config": "Original five-dot, two-electron cell; Fig. 7 biased-intersection OR gate and proposed set/sense boundary.",
      "gaps": [
        "Fabrication, relaxation, addressing and stability remain open engineering issues.",
        "No operating processor, measured speed or fault tolerance follows from the calculated ground states."
      ],
      "insight": "Why is this proposal distinct from coherent gate-model quantum computing?",
      "fields": {
        "state": {
          "value": "Two-electron cell polarization",
          "locator": "Fig. 1",
          "source": "alt-qca-1993"
        },
        "compute": {
          "value": "Coulomb-coupled ground-state relaxation",
          "locator": "§3",
          "source": "alt-qca-1993"
        },
        "memory": {
          "value": "Polarization; stability remains a design issue",
          "locator": "§4.4",
          "source": "alt-qca-1993"
        },
        "control": {
          "value": "Fixed input polarization and built-in cell bias",
          "locator": "§3; Fig. 7",
          "source": "alt-qca-1993"
        },
        "io": {
          "value": "Proposed electrostatic set/sense lines",
          "locator": "Fig. 4",
          "source": "alt-qca-1993"
        },
        "software": {
          "value": "Geometrical wire/gate arrangement",
          "locator": "§4",
          "source": "alt-qca-1993"
        },
        "workload": {
          "value": "Calculated binary OR gate",
          "locator": "Fig. 7",
          "source": "alt-qca-1993"
        }
      },
      "researchDepth": "architecture-dossier",
      "diagram": {
        "title": "A proposed biased intersection computes OR",
        "scope": "Logical functional reduction of Fig. 7, not an exact physical cell-placement drawing. All elements remain proposed.",
        "width": 960,
        "height": 490,
        "nodes": [
          {
            "id": "set",
            "label": "Set-line voltages",
            "subtitle": "PROPOSED INPUT",
            "text": "Fixes boundary polarization.",
            "x": 30,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-qca-1993",
            "locator": "§3; Fig. 4",
            "control": false
          },
          {
            "id": "a",
            "label": "Input edge A",
            "subtitle": "POLARIZATION BIT",
            "text": "First fixed input.",
            "x": 245,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-qca-1993",
            "locator": "Fig. 7",
            "control": false
          },
          {
            "id": "b",
            "label": "Input edge B",
            "subtitle": "POLARIZATION BIT",
            "text": "Second fixed input.",
            "x": 245,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-qca-1993",
            "locator": "Fig. 7",
            "control": false
          },
          {
            "id": "center",
            "label": "Biased intersection",
            "subtitle": "FIVE-DOT CELL",
            "text": "Tie favors logic one.",
            "x": 460,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-qca-1993",
            "locator": "§4.3; Fig. 7",
            "control": false
          },
          {
            "id": "bias",
            "label": "Dot-site energy asymmetry",
            "subtitle": "FIXED GEOMETRY",
            "text": "Breaks equal-input influence.",
            "x": 460,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-qca-1993",
            "locator": "§4.3",
            "control": false
          },
          {
            "id": "wire",
            "label": "Output cell chain",
            "subtitle": "COULOMB COUPLING",
            "text": "Propagates polarization.",
            "x": 675,
            "y": 35,
            "w": 160,
            "h": 62,
            "source": "alt-qca-1993",
            "locator": "§4.1; Fig. 7",
            "control": false
          },
          {
            "id": "sense",
            "label": "Sense-line coupling",
            "subtitle": "PROPOSED READOUT",
            "text": "Observes output-edge state.",
            "x": 675,
            "y": 205,
            "w": 160,
            "h": 62,
            "source": "alt-qca-1993",
            "locator": "§3; Fig. 4",
            "control": false
          },
          {
            "id": "bath",
            "label": "Dissipative environment",
            "subtitle": "RELAXATION",
            "text": "Allows approach to ground state.",
            "x": 460,
            "y": 375,
            "w": 160,
            "h": 62,
            "source": "alt-qca-1993",
            "locator": "§3.1",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "set",
            "to": "a",
            "type": "control",
            "locator": "§3",
            "label": "",
            "source": "alt-qca-1993"
          },
          {
            "from": "set",
            "to": "b",
            "type": "control",
            "locator": "§3",
            "label": "",
            "source": "alt-qca-1993"
          },
          {
            "from": "a",
            "to": "center",
            "type": "data",
            "locator": "Fig. 7",
            "label": "",
            "source": "alt-qca-1993"
          },
          {
            "from": "b",
            "to": "center",
            "type": "data",
            "locator": "Fig. 7",
            "label": "",
            "source": "alt-qca-1993"
          },
          {
            "from": "bias",
            "to": "center",
            "type": "control",
            "locator": "§4.3",
            "label": "",
            "source": "alt-qca-1993"
          },
          {
            "from": "center",
            "to": "wire",
            "type": "data",
            "locator": "Fig. 7",
            "label": "",
            "source": "alt-qca-1993"
          },
          {
            "from": "wire",
            "to": "sense",
            "type": "data",
            "locator": "§3; Fig. 4",
            "label": "",
            "source": "alt-qca-1993"
          },
          {
            "from": "bath",
            "to": "center",
            "type": "association",
            "locator": "§3.1",
            "label": "",
            "source": "alt-qca-1993"
          },
          {
            "from": "bath",
            "to": "wire",
            "type": "association",
            "locator": "§3.1",
            "label": "",
            "source": "alt-qca-1993"
          },
          {
            "from": "a",
            "to": "b",
            "type": "association",
            "locator": "§2",
            "label": "electrostatic, no electron transfer between cells",
            "source": "alt-qca-1993"
          }
        ]
      },
      "originalCandidate": "Quantum-dot cellular automata proposals"
    },
    {
      "status": "dossier",
      "researchDepth": "architecture-dossier",
      "uses": [],
      "id": "arm-morello-sdp",
      "name": "Arm Morello — System Development Platform",
      "aliases": [
        "CHERI Morello",
        "Morello Evaluation Board",
        "Rainier",
        "CMN-Skeena"
      ],
      "organization": "Arm / University of Cambridge / SRI",
      "year": 2022,
      "yearLabel": "2022 reference-manual configuration",
      "kind": "Prototype development system",
      "paradigms": [
        "digital",
        "parallel"
      ],
      "models": [
        "register"
      ],
      "architectures": [
        "stored-program",
        "load-store",
        "risc",
        "superscalar",
        "smp",
        "capability"
      ],
      "substrates": [
        "integrated"
      ],
      "summary": "A capability-aware four-core development system with tagged coherent memory and conventional peripheral paths.",
      "config": "The Issue 04 SDP: two dual-core Rainier clusters, CMN-Skeena and two DMC-Bing controllers. Client and server tag modes are alternatives.",
      "sources": [
        "gap-morello-trm",
        "gap-morello-software"
      ],
      "fields": {
        "state": {
          "value": "AArch64 extended with CHERI capability protection",
          "source": "gap-morello-trm",
          "locator": "p. 19"
        },
        "compute": {
          "value": "Two superscalar, dual-core Rainier clusters",
          "source": "gap-morello-trm",
          "locator": "pp. 19, 35"
        },
        "memory": {
          "value": "Tagged DDR4; per-core caches and per-cluster shared L3",
          "source": "gap-morello-trm",
          "locator": "pp. 19, 35–36"
        },
        "control": {
          "value": "SCP/MCP manage boot, power and devices",
          "source": "gap-morello-trm",
          "locator": "p. 35"
        },
        "io": {
          "value": "PCIe/CCIX, PCIe switch and IOFPGA paths",
          "source": "gap-morello-trm",
          "locator": "pp. 30–36"
        },
        "software": {
          "value": "CheriBSD and capability-aware Clang/LLVM tools",
          "source": "gap-morello-software",
          "locator": "CHERI software stack"
        },
        "workload": {
          "value": "Capability-security experimentation and software evaluation",
          "source": "gap-morello-trm",
          "locator": "p. 19"
        }
      },
      "gaps": [
        "Client tag-cache storage and server ECC tag storage are alternative modes, not two simultaneous tag memories.",
        "The diagram aggregates clusters/controllers and omits debug, interrupt and some peripheral details.",
        "This is an experimental capability platform; it is not a specification for a production Arm architecture."
      ],
      "insight": "Protection metadata must survive CPU, cache and memory transfers while ordinary DMA paths remain controlled.",
      "diagram": {
        "title": "Capability-aware compute and memory inside the SDP",
        "width": 1120,
        "height": 535,
        "scope": "Selected board/SoC hierarchy from Figures 3-1/3-2; logical associations aggregate sub-blocks. No physical trace layout is reproduced.",
        "nodes": [
          {
            "id": "cluster0",
            "label": "Rainier cluster 0",
            "subtitle": "TWO CORES + CACHES",
            "text": "Capability-aware application execution.",
            "x": 25,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "gap-morello-trm",
            "locator": "pp. 19, 35",
            "control": false
          },
          {
            "id": "fabric",
            "label": "CMN-Skeena",
            "subtitle": "COHERENT TAGGED FABRIC",
            "text": "Carries memory data and capability tags.",
            "x": 310,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "gap-morello-trm",
            "locator": "pp. 19, 34",
            "control": false
          },
          {
            "id": "dmc",
            "label": "Two DMC-Bing controllers",
            "subtitle": "DDR4 + TAG SUPPORT",
            "text": "Provide the tagged memory interfaces.",
            "x": 595,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "gap-morello-trm",
            "locator": "pp. 19, 36",
            "control": false
          },
          {
            "id": "dram",
            "label": "DDR4 RDIMMs",
            "subtitle": "ONE PER INTERFACE",
            "text": "Retain application state and mode-dependent metadata.",
            "x": 880,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "gap-morello-trm",
            "locator": "pp. 19, 36",
            "control": false
          },
          {
            "id": "cluster1",
            "label": "Rainier cluster 1",
            "subtitle": "TWO CORES + CACHES",
            "text": "Second capability-aware compute cluster.",
            "x": 25,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-morello-trm",
            "locator": "pp. 19, 35",
            "control": false
          },
          {
            "id": "gpu",
            "label": "Mali GPU / DPU",
            "subtitle": "GRAPHICS / DISPLAY",
            "text": "Conventional graphics and display agents.",
            "x": 310,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-morello-trm",
            "locator": "pp. 34, 36",
            "control": false
          },
          {
            "id": "pcie",
            "label": "PCIe root / switch path",
            "subtitle": "BOARD I/O",
            "text": "Connects slots and Ethernet/SATA/USB controllers.",
            "x": 595,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-morello-trm",
            "locator": "pp. 30–31, 35",
            "control": false
          },
          {
            "id": "devices",
            "label": "Peripheral controllers",
            "subtitle": "ETHERNET / SATA / USB",
            "text": "Board I/O endpoints behind the switch.",
            "x": 880,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-morello-trm",
            "locator": "p. 31",
            "control": false
          },
          {
            "id": "management",
            "label": "SCP / MCP",
            "subtitle": "BOOT / POWER / DEVICES",
            "text": "Embedded management processors.",
            "x": 25,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "gap-morello-trm",
            "locator": "p. 35",
            "control": true
          },
          {
            "id": "iofpga",
            "label": "IOFPGA",
            "subtitle": "LOW-SPEED I/O",
            "text": "Connects through Thin Links.",
            "x": 310,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "gap-morello-trm",
            "locator": "pp. 31–32, 35–36",
            "control": false
          },
          {
            "id": "tagmode",
            "label": "Tag-storage mode",
            "subtitle": "CLIENT OR SERVER",
            "text": "Client uses main-memory tags/cache; server uses ECC.",
            "x": 595,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "gap-morello-trm",
            "locator": "p. 19",
            "control": true
          },
          {
            "id": "ccix",
            "label": "CCIX / PCIe slot",
            "subtitle": "DIRECT ROOT PATH",
            "text": "Separate coherent-accelerator expansion path.",
            "x": 880,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "gap-morello-trm",
            "locator": "pp. 31, 35",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "cluster0",
            "to": "fabric",
            "type": "data",
            "source": "gap-morello-trm",
            "locator": "Figure 3-2",
            "note": "Coherent CPU memory traffic.",
            "bidirectional": true
          },
          {
            "from": "cluster1",
            "to": "fabric",
            "type": "data",
            "source": "gap-morello-trm",
            "locator": "Figure 3-2",
            "note": "Second cluster memory traffic.",
            "bidirectional": true
          },
          {
            "from": "fabric",
            "to": "dmc",
            "type": "data",
            "source": "gap-morello-trm",
            "locator": "Figure 3-2",
            "note": "Memory path carries tags.",
            "bidirectional": true
          },
          {
            "from": "dmc",
            "to": "dram",
            "type": "data",
            "source": "gap-morello-trm",
            "locator": "Figure 3-2",
            "note": "DDR4 interfaces.",
            "bidirectional": true
          },
          {
            "from": "gpu",
            "to": "fabric",
            "type": "data",
            "source": "gap-morello-trm",
            "locator": "Figure 3-2",
            "note": "Aggregated GPU/DPU memory paths.",
            "bidirectional": true
          },
          {
            "from": "fabric",
            "to": "pcie",
            "type": "data",
            "source": "gap-morello-trm",
            "locator": "Figures 3-1/3-2",
            "note": "Aggregated peripheral path.",
            "bidirectional": true
          },
          {
            "from": "pcie",
            "to": "devices",
            "type": "data",
            "source": "gap-morello-trm",
            "locator": "Figure 3-1",
            "note": "Switch-mediated board I/O.",
            "bidirectional": true
          },
          {
            "from": "fabric",
            "to": "ccix",
            "type": "data",
            "source": "gap-morello-trm",
            "locator": "Figure 3-2",
            "note": "Separate CCIX root path.",
            "bidirectional": true
          },
          {
            "from": "fabric",
            "to": "iofpga",
            "type": "association",
            "source": "gap-morello-trm",
            "locator": "Figure 3-2",
            "note": "Thin Links and system interconnect are aggregated.",
            "bidirectional": false
          },
          {
            "from": "management",
            "to": "fabric",
            "type": "association",
            "source": "gap-morello-trm",
            "locator": "Figure 3-2",
            "note": "Management interfaces to the SoC hierarchy.",
            "bidirectional": false
          },
          {
            "from": "tagmode",
            "to": "dmc",
            "type": "association",
            "source": "gap-morello-trm",
            "locator": "p. 19",
            "note": "Alternative metadata-storage organizations.",
            "bidirectional": false
          }
        ]
      },
      "originalCandidate": null
    },
    {
      "status": "dossier",
      "researchDepth": "architecture-dossier",
      "uses": [],
      "id": "plasticine-2017",
      "name": "Plasticine — 2017 evaluated design",
      "aliases": [
        "Pattern Compute Unit",
        "Pattern Memory Unit",
        "PCU",
        "PMU"
      ],
      "organization": "Stanford University",
      "year": 2017,
      "yearLabel": "2017 ISCA synthesized/simulated design",
      "kind": "Evaluated architecture proposal",
      "paradigms": [
        "digital",
        "parallel",
        "dataflow"
      ],
      "models": [
        "dataflow-model"
      ],
      "architectures": [
        "cgra",
        "reconfigurable",
        "simd",
        "dataflow-arch"
      ],
      "substrates": [
        "integrated"
      ],
      "summary": "Coarse-grained spatial hardware separates SIMD compute pipelines, configurable memories and off-chip address management.",
      "config": "The paper’s 16 × 8 organization: 64 PCUs and 64 PMUs. Results use synthesis and a cycle-accurate simulator with modeled DDR3.",
      "sources": [
        "gap-plasticine-paper"
      ],
      "fields": {
        "state": {
          "value": "32-bit arithmetic and configured pipelines",
          "source": "gap-plasticine-paper",
          "locator": "§3.1"
        },
        "compute": {
          "value": "64 PCUs with staged SIMD functional units",
          "source": "gap-plasticine-paper",
          "locator": "§§3.1, 4.2"
        },
        "memory": {
          "value": "64 banked PMUs; 16 MB total scratchpad",
          "source": "gap-plasticine-paper",
          "locator": "§§3.2, 4.2"
        },
        "control": {
          "value": "Distributed counters, tokens, credits and FIFO readiness",
          "source": "gap-plasticine-paper",
          "locator": "§3.5"
        },
        "io": {
          "value": "Scalar/vector/control networks; four DDR channels",
          "source": "gap-plasticine-paper",
          "locator": "§§3.3–3.4"
        },
        "software": {
          "value": "DHDL compilation, partitioning, placement and routing",
          "source": "gap-plasticine-paper",
          "locator": "§3.6"
        },
        "workload": {
          "value": "Dense/sparse kernels evaluated in simulation",
          "source": "gap-plasticine-paper",
          "locator": "§§4.1–4.2"
        }
      },
      "gaps": [
        "No fabricated-chip operating result is inferred from synthesis area, timing targets or power estimates.",
        "The paper’s accelerator timing excludes host-to-device and device-to-host data copies.",
        "Representative PCU/PMU roles are expanded; the complete 128-unit mesh is aggregated."
      ],
      "insight": "A useful CGRA separates data computation from address generation and gives control its own routed resources.",
      "diagram": {
        "title": "Configured compute, distributed scratchpads and memory requests",
        "width": 1120,
        "height": 535,
        "scope": "PCU and PMU roles from Figures 3–5; all three static networks are aggregated in the fabric block.",
        "nodes": [
          {
            "id": "compiler",
            "label": "DHDL compiler",
            "subtitle": "OFFLINE MAPPING",
            "text": "Builds the static resource configuration.",
            "x": 25,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "gap-plasticine-paper",
            "locator": "§3.6",
            "control": true
          },
          {
            "id": "fabric",
            "label": "Static interconnect",
            "subtitle": "SCALAR / VECTOR / CONTROL",
            "text": "Routes between compute, memory and edge units.",
            "x": 310,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "gap-plasticine-paper",
            "locator": "§3.3; Figure 5",
            "control": false
          },
          {
            "id": "pcu",
            "label": "PCU SIMD pipeline",
            "subtitle": "FUNCTIONS + REGISTERS",
            "text": "Computes application operations.",
            "x": 595,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "gap-plasticine-paper",
            "locator": "§3.1; Figure 3",
            "control": false
          },
          {
            "id": "reduce",
            "label": "Reduction / shift paths",
            "subtitle": "WITHIN A PCU",
            "text": "Support cross-lane reduction and window reuse.",
            "x": 880,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "gap-plasticine-paper",
            "locator": "§3.1",
            "control": false
          },
          {
            "id": "control",
            "label": "Counters / control",
            "subtitle": "DISTRIBUTED EXECUTION",
            "text": "Coordinate dependencies and backpressure.",
            "x": 25,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-plasticine-paper",
            "locator": "§3.5",
            "control": true
          },
          {
            "id": "pmu",
            "label": "PMU scratchpad banks",
            "subtitle": "CONFIGURABLE BUFFERING",
            "text": "Store tiled, streamed or duplicated data.",
            "x": 310,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-plasticine-paper",
            "locator": "§3.2; Figure 4",
            "control": false
          },
          {
            "id": "address",
            "label": "PMU scalar datapath",
            "subtitle": "LOCAL ADDRESSES",
            "text": "Generates scratchpad read/write addresses.",
            "x": 595,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-plasticine-paper",
            "locator": "§3.2; Figure 4",
            "control": false
          },
          {
            "id": "fifo",
            "label": "Input FIFOs",
            "subtitle": "DECOUPLED ARRIVAL",
            "text": "Buffer scalar/vector inputs.",
            "x": 880,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-plasticine-paper",
            "locator": "§3.1; Figure 3",
            "control": false
          },
          {
            "id": "ag",
            "label": "Address generators",
            "subtitle": "DRAM REQUEST STREAMS",
            "text": "Generate and buffer external-memory requests.",
            "x": 25,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "gap-plasticine-paper",
            "locator": "§3.4",
            "control": false
          },
          {
            "id": "coalesce",
            "label": "Coalescing / arbitration",
            "subtitle": "FOUR CHANNEL PATHS",
            "text": "Combines requests into suitable memory operations.",
            "x": 310,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "gap-plasticine-paper",
            "locator": "§3.4",
            "control": false
          },
          {
            "id": "dram",
            "label": "Modeled DDR3 memory",
            "subtitle": "SIMULATION BOUNDARY",
            "text": "External-memory timing uses DRAMSim2.",
            "x": 595,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "gap-plasticine-paper",
            "locator": "§4.2",
            "control": false
          },
          {
            "id": "config",
            "label": "Configuration registers",
            "subtitle": "STATIC SETUP",
            "text": "Select operations and routing before execution.",
            "x": 880,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "gap-plasticine-paper",
            "locator": "§§3.1, 3.3, 3.6",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "compiler",
            "to": "config",
            "type": "association",
            "source": "gap-plasticine-paper",
            "locator": "§3.6",
            "note": "Offline compilation creates configuration.",
            "bidirectional": false
          },
          {
            "from": "config",
            "to": "fabric",
            "type": "association",
            "source": "gap-plasticine-paper",
            "locator": "§§3.3, 3.6",
            "note": "Configures static networks.",
            "bidirectional": false
          },
          {
            "from": "config",
            "to": "pcu",
            "type": "association",
            "source": "gap-plasticine-paper",
            "locator": "§3.1",
            "note": "Selects staged functional-unit operations.",
            "bidirectional": false
          },
          {
            "from": "fabric",
            "to": "fifo",
            "type": "data",
            "source": "gap-plasticine-paper",
            "locator": "§3.1; Figure 3",
            "note": "Network inputs are buffered.",
            "bidirectional": false
          },
          {
            "from": "fifo",
            "to": "pcu",
            "type": "data",
            "source": "gap-plasticine-paper",
            "locator": "Figure 3",
            "note": "Operands enter the pipeline.",
            "bidirectional": false
          },
          {
            "from": "pcu",
            "to": "fabric",
            "type": "data",
            "source": "gap-plasticine-paper",
            "locator": "§3.1",
            "note": "Scalar/vector outputs.",
            "bidirectional": false
          },
          {
            "from": "pcu",
            "to": "reduce",
            "type": "data",
            "source": "gap-plasticine-paper",
            "locator": "§3.1",
            "note": "Cross-lane operations.",
            "bidirectional": true
          },
          {
            "from": "fabric",
            "to": "pmu",
            "type": "data",
            "source": "gap-plasticine-paper",
            "locator": "§§3.2–3.3",
            "note": "Scratchpad data exchange.",
            "bidirectional": true
          },
          {
            "from": "address",
            "to": "pmu",
            "type": "control",
            "source": "gap-plasticine-paper",
            "locator": "Figure 4",
            "note": "Local read/write addressing.",
            "bidirectional": false
          },
          {
            "from": "control",
            "to": "pcu",
            "type": "control",
            "source": "gap-plasticine-paper",
            "locator": "§3.5",
            "note": "Execution enable and dependencies.",
            "bidirectional": false
          },
          {
            "from": "control",
            "to": "pmu",
            "type": "control",
            "source": "gap-plasticine-paper",
            "locator": "§3.5",
            "note": "Producer/consumer buffer coordination.",
            "bidirectional": false
          },
          {
            "from": "fabric",
            "to": "ag",
            "type": "data",
            "source": "gap-plasticine-paper",
            "locator": "Figure 5",
            "note": "External-memory streams.",
            "bidirectional": true
          },
          {
            "from": "ag",
            "to": "coalesce",
            "type": "data",
            "source": "gap-plasticine-paper",
            "locator": "§3.4",
            "note": "Requests, data and responses.",
            "bidirectional": true
          },
          {
            "from": "coalesce",
            "to": "dram",
            "type": "data",
            "source": "gap-plasticine-paper",
            "locator": "§§3.4, 4.2",
            "note": "Modeled DDR traffic.",
            "bidirectional": true
          }
        ]
      },
      "originalCandidate": null
    },
    {
      "status": "dossier",
      "researchDepth": "architecture-dossier",
      "uses": [],
      "id": "actor-model-hewitt",
      "name": "Actor model — message-reception semantics",
      "aliases": [
        "Hewitt actors",
        "Concurrent actor computation"
      ],
      "organization": "Carl Hewitt",
      "year": 2015,
      "yearLabel": "2015 v38 exposition; model introduced in 1973",
      "kind": "Computational model",
      "paradigms": [
        "digital",
        "parallel"
      ],
      "models": [
        "actor"
      ],
      "architectures": [],
      "substrates": [],
      "summary": "Concurrent computation through asynchronous messages, actor creation and behavior changes.",
      "config": "The three actions available on message reception in Hewitt’s v38 exposition. This is a semantic diagram, not a scheduler or hardware implementation.",
      "sources": [
        "gap-actor-hewitt"
      ],
      "fields": {
        "state": {
          "value": "Actor behavior and addresses it can use",
          "source": "gap-actor-hewitt",
          "locator": "pp. 1, 3"
        },
        "compute": {
          "value": "Concurrent activity within and among actors",
          "source": "gap-actor-hewitt",
          "locator": "p. 3"
        },
        "memory": {
          "value": "Retained behavior; no prescribed physical memory",
          "source": "gap-actor-hewitt",
          "locator": "p. 3"
        },
        "control": {
          "value": "Message reception permits three concurrent actions",
          "source": "gap-actor-hewitt",
          "locator": "pp. 1, 3"
        },
        "io": {
          "value": "One-way asynchronous messages to known addresses",
          "source": "gap-actor-hewitt",
          "locator": "pp. 3–4"
        },
        "software": {
          "value": "Model for concurrent implementations",
          "source": "gap-actor-hewitt",
          "locator": "pp. 3–4"
        },
        "workload": {
          "value": "Concurrent systems; web-service examples",
          "source": "gap-actor-hewitt",
          "locator": "pp. 1, 4"
        }
      },
      "gaps": [
        "A mailbox, OS process, hardware thread or central scheduler is not required by this model.",
        "The diagram depicts possible actions, not a mandatory serial execution pipeline.",
        "No timing, delivery-order guarantee, performance overhead or physical substrate is assigned."
      ],
      "insight": "Message ordering and runtime mechanisms belong to the implementation; they must not be smuggled into the model.",
      "diagram": {
        "title": "What an actor may do when a message arrives",
        "width": 1000,
        "height": 480,
        "scope": "Semantic decomposition of pp. 1 and 3–4. Dotted links associate model roles; they are not hardware wiring.",
        "nodes": [
          {
            "id": "sender",
            "label": "Sending actor",
            "subtitle": "KNOWN DESTINATION",
            "text": "Initiates a one-way message.",
            "x": 25,
            "y": 30,
            "w": 210,
            "h": 68,
            "source": "gap-actor-hewitt",
            "locator": "pp. 3–4",
            "control": false
          },
          {
            "id": "message",
            "label": "Message",
            "subtitle": "ASYNCHRONOUS SEND",
            "text": "Can include actor addresses.",
            "x": 280,
            "y": 30,
            "w": 210,
            "h": 68,
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "control": false
          },
          {
            "id": "receiver",
            "label": "Receiving actor",
            "subtitle": "CURRENT BEHAVIOR",
            "text": "Processes the arriving message.",
            "x": 535,
            "y": 30,
            "w": 210,
            "h": 68,
            "source": "gap-actor-hewitt",
            "locator": "pp. 1, 3",
            "control": false
          },
          {
            "id": "known",
            "label": "Known actor addresses",
            "subtitle": "COMMUNICATION AUTHORITY",
            "text": "Bound the actors it can contact.",
            "x": 25,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "control": false
          },
          {
            "id": "send",
            "label": "Send further messages",
            "subtitle": "POSSIBLE ACTION",
            "text": "Sends to addresses already available.",
            "x": 280,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-actor-hewitt",
            "locator": "pp. 1, 3",
            "control": false
          },
          {
            "id": "create",
            "label": "Create new actors",
            "subtitle": "POSSIBLE ACTION",
            "text": "Creates actors with new addresses.",
            "x": 535,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "control": false
          },
          {
            "id": "behavior",
            "label": "Designate next behavior",
            "subtitle": "POSSIBLE ACTION",
            "text": "Determines a later reception’s handling.",
            "x": 770,
            "y": 215,
            "w": 205,
            "h": 68,
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "control": true
          },
          {
            "id": "peer",
            "label": "Another actor",
            "subtitle": "INDEPENDENT ACTIVITY",
            "text": "May receive a further message.",
            "x": 280,
            "y": 390,
            "w": 210,
            "h": 68,
            "source": "gap-actor-hewitt",
            "locator": "pp. 3–4",
            "control": false
          },
          {
            "id": "new",
            "label": "New actor",
            "subtitle": "DYNAMIC CREATION",
            "text": "Can participate in later communication.",
            "x": 535,
            "y": 390,
            "w": 210,
            "h": 68,
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "control": false
          },
          {
            "id": "next",
            "label": "Next reception",
            "subtitle": "LATER MESSAGE",
            "text": "Uses the designated behavior.",
            "x": 770,
            "y": 390,
            "w": 205,
            "h": 68,
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "sender",
            "to": "message",
            "type": "data",
            "source": "gap-actor-hewitt",
            "locator": "pp. 3–4",
            "note": "One-way asynchronous send.",
            "bidirectional": false
          },
          {
            "from": "message",
            "to": "receiver",
            "type": "data",
            "source": "gap-actor-hewitt",
            "locator": "pp. 3–4",
            "note": "Message reception.",
            "bidirectional": false
          },
          {
            "from": "receiver",
            "to": "send",
            "type": "association",
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "note": "One of three possible concurrent actions.",
            "bidirectional": false
          },
          {
            "from": "receiver",
            "to": "create",
            "type": "association",
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "note": "One of three possible concurrent actions.",
            "bidirectional": false
          },
          {
            "from": "receiver",
            "to": "behavior",
            "type": "association",
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "note": "One of three possible concurrent actions.",
            "bidirectional": false
          },
          {
            "from": "known",
            "to": "send",
            "type": "association",
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "note": "A destination address is needed.",
            "bidirectional": false
          },
          {
            "from": "send",
            "to": "peer",
            "type": "data",
            "source": "gap-actor-hewitt",
            "locator": "pp. 3–4",
            "note": "Further asynchronous message.",
            "bidirectional": false
          },
          {
            "from": "create",
            "to": "new",
            "type": "association",
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "note": "Creation yields a new actor/address.",
            "bidirectional": false
          },
          {
            "from": "behavior",
            "to": "next",
            "type": "control",
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "note": "Designates handling for the next message.",
            "bidirectional": false
          },
          {
            "from": "message",
            "to": "known",
            "type": "association",
            "source": "gap-actor-hewitt",
            "locator": "p. 3",
            "note": "Messages may convey addresses.",
            "bidirectional": false
          }
        ]
      },
      "originalCandidate": null
    },
    {
      "status": "dossier",
      "researchDepth": "architecture-dossier",
      "uses": [],
      "id": "petri-bakery-run",
      "name": "Petri nets — bakery distributed run",
      "aliases": [
        "Petri net causal run",
        "Reisig Fettke bakery"
      ],
      "organization": "Reisig / Fettke",
      "year": 2024,
      "yearLabel": "2024 published model example",
      "kind": "Computational model example",
      "paradigms": [
        "parallel"
      ],
      "models": [
        "petri"
      ],
      "architectures": [],
      "substrates": [],
      "summary": "A small causal model separates local conditions from events and preserves dependencies without imposing a global clock.",
      "config": "The finite, four-event distributed run of Figure 3, not a cyclic bakery implementation or the entire class of Petri nets.",
      "sources": [
        "gap-petri-bakery"
      ],
      "fields": {
        "state": {
          "value": "Reached or abandoned local conditions",
          "source": "gap-petri-bakery",
          "locator": "p. 3"
        },
        "compute": {
          "value": "Four events update their adjacent conditions",
          "source": "gap-petri-bakery",
          "locator": "pp. 3–4; Figures 2–3"
        },
        "memory": {
          "value": "Condition occurrences retain causal state",
          "source": "gap-petri-bakery",
          "locator": "pp. 3–4"
        },
        "control": {
          "value": "Local causes and effects; no global clock",
          "source": "gap-petri-bakery",
          "locator": "pp. 2–4"
        },
        "io": {
          "value": "Directed arcs encode causal dependency",
          "source": "gap-petri-bakery",
          "locator": "p. 4"
        },
        "software": {
          "value": "Graphical modeling formalism",
          "source": "gap-petri-bakery",
          "locator": "pp. 1, 3–4"
        },
        "workload": {
          "value": "Bakery production and transfer example",
          "source": "gap-petri-bakery",
          "locator": "Figures 2–4"
        }
      },
      "gaps": [
        "This is one finite run. Repeated labels identify distinct condition occurrences.",
        "No electrical device, physical storage technology or execution latency is specified.",
        "Arrows express causality; the editor uses control styling rather than claiming data wires."
      ],
      "insight": "A partial order can preserve which event depends on which condition without declaring a universal sequence of machine states.",
      "diagram": {
        "title": "Four bakery events and their local causal dependencies",
        "width": 1430,
        "height": 420,
        "scope": "Original conceptual redrawing of Figure 3. Every state occurrence and event is retained; repeated state labels receive editorial occurrence suffixes.",
        "nodes": [
          {
            "id": "ready0",
            "label": "Ready to bake · 0",
            "subtitle": "INITIAL CONDITION",
            "text": "Enables the bake event.",
            "x": 20,
            "y": 25,
            "w": 170,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": false
          },
          {
            "id": "bake",
            "label": "Bake",
            "subtitle": "EVENT",
            "text": "Produces the on-counter condition.",
            "x": 225,
            "y": 25,
            "w": 170,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": true
          },
          {
            "id": "counter",
            "label": "On counter",
            "subtitle": "CONDITION",
            "text": "Connects bake to supply.",
            "x": 430,
            "y": 25,
            "w": 170,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": false
          },
          {
            "id": "supply",
            "label": "Supply to aide",
            "subtitle": "EVENT",
            "text": "Requires counter product and a free aide.",
            "x": 635,
            "y": 25,
            "w": 170,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": true
          },
          {
            "id": "ready1",
            "label": "Ready to bake · 1",
            "subtitle": "RESULT CONDITION",
            "text": "New readiness occurrence after supply.",
            "x": 840,
            "y": 25,
            "w": 170,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": false
          },
          {
            "id": "free0",
            "label": "Aide free · 0",
            "subtitle": "INITIAL CONDITION",
            "text": "Enables supply.",
            "x": 430,
            "y": 175,
            "w": 170,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": false
          },
          {
            "id": "busy",
            "label": "Aide busy",
            "subtitle": "CONDITION",
            "text": "Enables the move event.",
            "x": 840,
            "y": 175,
            "w": 170,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": false
          },
          {
            "id": "move",
            "label": "Move to shop",
            "subtitle": "EVENT",
            "text": "Requires busy aide and empty shelf.",
            "x": 1045,
            "y": 175,
            "w": 170,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": true
          },
          {
            "id": "free1",
            "label": "Aide free · 1",
            "subtitle": "RESULT CONDITION",
            "text": "New free-aide occurrence.",
            "x": 1250,
            "y": 25,
            "w": 160,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": false
          },
          {
            "id": "empty0",
            "label": "Shelf empty · 0",
            "subtitle": "INITIAL CONDITION",
            "text": "Enables move to shop.",
            "x": 430,
            "y": 325,
            "w": 170,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": false
          },
          {
            "id": "shelf",
            "label": "On shelf",
            "subtitle": "CONDITION",
            "text": "Enables sell.",
            "x": 840,
            "y": 325,
            "w": 170,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": false
          },
          {
            "id": "sell",
            "label": "Sell",
            "subtitle": "EVENT",
            "text": "Produces a new empty-shelf occurrence.",
            "x": 1045,
            "y": 325,
            "w": 170,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": true
          },
          {
            "id": "empty1",
            "label": "Shelf empty · 1",
            "subtitle": "RESULT CONDITION",
            "text": "Final condition of this finite run.",
            "x": 1250,
            "y": 325,
            "w": 160,
            "h": 62,
            "source": "gap-petri-bakery",
            "locator": "Figure 3",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "ready0",
            "to": "bake",
            "type": "control",
            "source": "gap-petri-bakery",
            "locator": "p. 4, Figure 3",
            "note": "Causal dependency in the published finite run.",
            "bidirectional": false
          },
          {
            "from": "bake",
            "to": "counter",
            "type": "control",
            "source": "gap-petri-bakery",
            "locator": "p. 4, Figure 3",
            "note": "Causal dependency in the published finite run.",
            "bidirectional": false
          },
          {
            "from": "counter",
            "to": "supply",
            "type": "control",
            "source": "gap-petri-bakery",
            "locator": "p. 4, Figure 3",
            "note": "Causal dependency in the published finite run.",
            "bidirectional": false
          },
          {
            "from": "free0",
            "to": "supply",
            "type": "control",
            "source": "gap-petri-bakery",
            "locator": "p. 4, Figure 3",
            "note": "Causal dependency in the published finite run.",
            "bidirectional": false
          },
          {
            "from": "supply",
            "to": "ready1",
            "type": "control",
            "source": "gap-petri-bakery",
            "locator": "p. 4, Figure 3",
            "note": "Causal dependency in the published finite run.",
            "bidirectional": false
          },
          {
            "from": "supply",
            "to": "busy",
            "type": "control",
            "source": "gap-petri-bakery",
            "locator": "p. 4, Figure 3",
            "note": "Causal dependency in the published finite run.",
            "bidirectional": false
          },
          {
            "from": "busy",
            "to": "move",
            "type": "control",
            "source": "gap-petri-bakery",
            "locator": "p. 4, Figure 3",
            "note": "Causal dependency in the published finite run.",
            "bidirectional": false
          },
          {
            "from": "empty0",
            "to": "move",
            "type": "control",
            "source": "gap-petri-bakery",
            "locator": "p. 4, Figure 3",
            "note": "Causal dependency in the published finite run.",
            "bidirectional": false
          },
          {
            "from": "move",
            "to": "free1",
            "type": "control",
            "source": "gap-petri-bakery",
            "locator": "p. 4, Figure 3",
            "note": "Causal dependency in the published finite run.",
            "bidirectional": false
          },
          {
            "from": "move",
            "to": "shelf",
            "type": "control",
            "source": "gap-petri-bakery",
            "locator": "p. 4, Figure 3",
            "note": "Causal dependency in the published finite run.",
            "bidirectional": false
          },
          {
            "from": "shelf",
            "to": "sell",
            "type": "control",
            "source": "gap-petri-bakery",
            "locator": "p. 4, Figure 3",
            "note": "Causal dependency in the published finite run.",
            "bidirectional": false
          },
          {
            "from": "sell",
            "to": "empty1",
            "type": "control",
            "source": "gap-petri-bakery",
            "locator": "p. 4, Figure 3",
            "note": "Causal dependency in the published finite run.",
            "bidirectional": false
          }
        ]
      },
      "originalCandidate": null
    },
    {
      "status": "dossier",
      "researchDepth": "architecture-dossier",
      "uses": [],
      "id": "flynn-misd-classification",
      "name": "MISD — Flynn’s stream classification",
      "aliases": [
        "Multiple instruction single data",
        "MISD taxonomy"
      ],
      "organization": "Michael J. Flynn",
      "year": 1972,
      "yearLabel": "1972 classification paper",
      "kind": "Architectural classification",
      "paradigms": [
        "parallel"
      ],
      "models": [],
      "architectures": [
        "misd"
      ],
      "substrates": [],
      "summary": "Multiple instruction streams operate on one data sequence and its derivatives; this record makes no built-machine assignment.",
      "config": "The p. 949 definition illustrated by an editorial three-stage stream. Stage count, operations and physical organization are unspecified by the class.",
      "sources": [
        "gap-flynn-1972"
      ],
      "fields": {
        "state": {
          "value": "One data sequence and derived values",
          "source": "gap-flynn-1972",
          "locator": "p. 949"
        },
        "compute": {
          "value": "Multiple instruction streams",
          "source": "gap-flynn-1972",
          "locator": "p. 949"
        },
        "memory": {
          "value": "No common memory topology required by the class",
          "source": "gap-flynn-1972",
          "locator": "pp. 949–951, classification dimensions"
        },
        "control": {
          "value": "Different instruction streams serve stream-processing roles",
          "source": "gap-flynn-1972",
          "locator": "p. 949"
        },
        "io": {
          "value": "Inter-operation communication matters separately",
          "source": "gap-flynn-1972",
          "locator": "pp. 950–951"
        },
        "software": {
          "value": "Program steps can form a request/service hierarchy",
          "source": "gap-flynn-1972",
          "locator": "p. 949"
        },
        "workload": {
          "value": "Specialized streaming organizations",
          "source": "gap-flynn-1972",
          "locator": "p. 949"
        }
      },
      "gaps": [
        "The three-stage picture is explanatory, not a claimed physical system.",
        "Redundant lockstep machines and ordinary pipelines are not automatically assigned to MISD.",
        "Instruction/data stream granularity must be declared before applying this qualitative class."
      ],
      "insight": "A stream classification is a lens; it does not replace a machine’s configuration or interconnect evidence.",
      "diagram": {
        "title": "Illustrating the definition without inventing a machine",
        "width": 1120,
        "height": 425,
        "scope": "Editorial three-stage specialization of p. 949. Solid arrows follow one data sequence and derivatives; control arrows show distinct instruction streams. No stage count is attributed to Flynn.",
        "nodes": [
          {
            "id": "input",
            "label": "Single data sequence",
            "subtitle": "INPUT STREAM",
            "text": "The one selected data-stream reference.",
            "x": 25,
            "y": 230,
            "w": 210,
            "h": 68,
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "control": false
          },
          {
            "id": "stage1",
            "label": "Operation stage 1",
            "subtitle": "ILLUSTRATIVE ROLE",
            "text": "Applies its instruction stream.",
            "x": 310,
            "y": 230,
            "w": 210,
            "h": 68,
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "control": false
          },
          {
            "id": "stage2",
            "label": "Operation stage 2",
            "subtitle": "ILLUSTRATIVE ROLE",
            "text": "Works on the sequence’s derived data.",
            "x": 595,
            "y": 230,
            "w": 210,
            "h": 68,
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "control": false
          },
          {
            "id": "stage3",
            "label": "Operation stage 3",
            "subtitle": "ILLUSTRATIVE ROLE",
            "text": "Continues the derived-data sequence.",
            "x": 880,
            "y": 230,
            "w": 210,
            "h": 68,
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "control": false
          },
          {
            "id": "definition",
            "label": "MISD classification",
            "subtitle": "QUALITATIVE LENS",
            "text": "Counts instruction/data streams at a chosen reference.",
            "x": 25,
            "y": 30,
            "w": 210,
            "h": 68,
            "source": "gap-flynn-1972",
            "locator": "pp. 949–951",
            "control": true
          },
          {
            "id": "i1",
            "label": "Instruction stream 1",
            "subtitle": "DISTINCT CONTROL",
            "text": "Controls the first illustrative role.",
            "x": 310,
            "y": 30,
            "w": 210,
            "h": 68,
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "control": true
          },
          {
            "id": "i2",
            "label": "Instruction stream 2",
            "subtitle": "DISTINCT CONTROL",
            "text": "Controls the second illustrative role.",
            "x": 595,
            "y": 30,
            "w": 210,
            "h": 68,
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "control": true
          },
          {
            "id": "i3",
            "label": "Instruction stream 3",
            "subtitle": "DISTINCT CONTROL",
            "text": "Controls the third illustrative role.",
            "x": 880,
            "y": 30,
            "w": 210,
            "h": 68,
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "control": true
          },
          {
            "id": "output",
            "label": "Derived result sequence",
            "subtitle": "SAME STREAM LINEAGE",
            "text": "Retains the selected single-data-stream interpretation.",
            "x": 880,
            "y": 345,
            "w": 210,
            "h": 68,
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "control": false
          }
        ],
        "edges": [
          {
            "from": "input",
            "to": "stage1",
            "type": "data",
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "stage1",
            "to": "stage2",
            "type": "data",
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "stage2",
            "to": "stage3",
            "type": "data",
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "stage3",
            "to": "output",
            "type": "data",
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "i1",
            "to": "stage1",
            "type": "control",
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "i2",
            "to": "stage2",
            "type": "control",
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "i3",
            "to": "stage3",
            "type": "control",
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "definition",
            "to": "i1",
            "type": "association",
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "definition",
            "to": "input",
            "type": "association",
            "source": "gap-flynn-1972",
            "locator": "p. 949",
            "note": "",
            "bidirectional": false
          }
        ]
      },
      "originalCandidate": null
    },
    {
      "status": "dossier",
      "researchDepth": "architecture-dossier",
      "uses": [],
      "id": "lispkit-secd-1983",
      "name": "LispKit — 1983 lazy SECD virtual machine",
      "aliases": [
        "LispKit Lisp",
        "SECD",
        "LDE",
        "AP0",
        "UPD"
      ],
      "organization": "Stirling / Oxford",
      "year": 1983,
      "yearLabel": "1983 PRG-32(1) manual",
      "kind": "Software virtual-machine architecture",
      "paradigms": [
        "digital"
      ],
      "models": [
        "lambda"
      ],
      "architectures": [
        "stack"
      ],
      "substrates": [],
      "summary": "A portable functional runtime adds delayed-expression recipes, forcing and memoization to a SECD-style machine.",
      "config": "The manual’s lazy LispKit VM and its documented LDE/AP0/UPD transitions. Host-specific Pascal, microcoded and machine-code realizations are separate implementations.",
      "sources": [
        "gap-lispkit-manual"
      ],
      "fields": {
        "state": {
          "value": "S-expressions, closures and delayed recipes",
          "source": "gap-lispkit-manual",
          "locator": "printed pp. 5, 108"
        },
        "compute": {
          "value": "SECD-style virtual instruction execution",
          "source": "gap-lispkit-manual",
          "locator": "printed pp. 107–109"
        },
        "memory": {
          "value": "Cell store; recipes retain code/environment",
          "source": "gap-lispkit-manual",
          "locator": "printed pp. 108–109, 112"
        },
        "control": {
          "value": "Stack, environment, control and dump transitions",
          "source": "gap-lispkit-manual",
          "locator": "printed pp. 108–109, 113"
        },
        "io": {
          "value": "Host-specific character and file interfaces",
          "source": "gap-lispkit-manual",
          "locator": "printed p. 107"
        },
        "software": {
          "value": "Functional compiler and portable support software",
          "source": "gap-lispkit-manual",
          "locator": "printed pp. 1, 107"
        },
        "workload": {
          "value": "Lazy evaluation of functional programs",
          "source": "gap-lispkit-manual",
          "locator": "printed pp. 5, 108–109"
        }
      },
      "gaps": [
        "The diagram shows semantic state and instruction effects, not separate hardware blocks.",
        "AP0 denotes the zero-argument forcing instruction; it does not imply a physical processor.",
        "The 1983 VM includes extensions beyond Landin’s original SECD; those editions are not conflated."
      ],
      "insight": "A pure source language may use internal mutation to memoize a delayed value while preserving its observable meaning.",
      "diagram": {
        "title": "Creating, forcing and updating a delayed expression",
        "width": 1120,
        "height": 535,
        "scope": "Semantic relationships from the printed pp. 108–109 transition rules. Dotted links retain recipe components; control links describe instruction effects.",
        "nodes": [
          {
            "id": "compiler",
            "label": "Functional compiler",
            "subtitle": "INSERTS LAZY OPERATIONS",
            "text": "Generates delays and forcing where needed.",
            "x": 25,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "gap-lispkit-manual",
            "locator": "printed p. 109",
            "control": true
          },
          {
            "id": "c",
            "label": "Control · C",
            "subtitle": "VIRTUAL CODE",
            "text": "Sequences the documented VM instructions.",
            "x": 310,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "gap-lispkit-manual",
            "locator": "printed pp. 108–109",
            "control": true
          },
          {
            "id": "lde",
            "label": "LDE",
            "subtitle": "CREATE RECIPE",
            "text": "Packages expression code and environment.",
            "x": 595,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "gap-lispkit-manual",
            "locator": "printed p. 108",
            "control": true
          },
          {
            "id": "recipe",
            "label": "Recipe cell",
            "subtitle": "CODE + ENVIRONMENT",
            "text": "Retains the delayed computation.",
            "x": 880,
            "y": 25,
            "w": 210,
            "h": 68,
            "source": "gap-lispkit-manual",
            "locator": "printed p. 108",
            "control": false
          },
          {
            "id": "e",
            "label": "Environment · E",
            "subtitle": "BINDINGS",
            "text": "Supplies the recipe’s lexical environment.",
            "x": 25,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-lispkit-manual",
            "locator": "printed pp. 108–109",
            "control": false
          },
          {
            "id": "s",
            "label": "Stack · S",
            "subtitle": "VALUES / RECIPES",
            "text": "Holds the candidate to force and eventual value.",
            "x": 310,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-lispkit-manual",
            "locator": "printed pp. 108–109",
            "control": false
          },
          {
            "id": "ap0",
            "label": "AP0",
            "subtitle": "FORCE IF RECIPE",
            "text": "Starts recipe evaluation; ordinary values pass through.",
            "x": 595,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-lispkit-manual",
            "locator": "printed pp. 108–109",
            "control": true
          },
          {
            "id": "d",
            "label": "Dump · D",
            "subtitle": "SAVED CALLER STATE",
            "text": "Retains the state restored by UPD.",
            "x": 880,
            "y": 215,
            "w": 210,
            "h": 68,
            "source": "gap-lispkit-manual",
            "locator": "printed p. 109",
            "control": false
          },
          {
            "id": "code",
            "label": "Recipe code",
            "subtitle": "DELAYED EXPRESSION",
            "text": "Executed under the retained environment.",
            "x": 25,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "gap-lispkit-manual",
            "locator": "printed p. 108",
            "control": false
          },
          {
            "id": "value",
            "label": "Computed value",
            "subtitle": "EVALUATION RESULT",
            "text": "Replaces the recipe to avoid recomputation.",
            "x": 310,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "gap-lispkit-manual",
            "locator": "printed p. 109",
            "control": false
          },
          {
            "id": "upd",
            "label": "UPD",
            "subtitle": "UPDATE + RETURN",
            "text": "Memoizes the value and restores caller state.",
            "x": 595,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "gap-lispkit-manual",
            "locator": "printed p. 109",
            "control": true
          },
          {
            "id": "resume",
            "label": "Resumed execution",
            "subtitle": "RESTORED S / E / C / D",
            "text": "Continues with the memoized result.",
            "x": 880,
            "y": 405,
            "w": 210,
            "h": 68,
            "source": "gap-lispkit-manual",
            "locator": "printed p. 109",
            "control": true
          }
        ],
        "edges": [
          {
            "from": "compiler",
            "to": "c",
            "type": "association",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 109",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "c",
            "to": "lde",
            "type": "control",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 108",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "lde",
            "to": "recipe",
            "type": "data",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 108",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "recipe",
            "to": "e",
            "type": "association",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 108",
            "note": "Retained environment component.",
            "bidirectional": false
          },
          {
            "from": "recipe",
            "to": "code",
            "type": "association",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 108",
            "note": "Retained code component.",
            "bidirectional": false
          },
          {
            "from": "lde",
            "to": "s",
            "type": "data",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 108",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "s",
            "to": "ap0",
            "type": "data",
            "source": "gap-lispkit-manual",
            "locator": "printed pp. 108–109",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "c",
            "to": "ap0",
            "type": "control",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 108",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "ap0",
            "to": "d",
            "type": "control",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 109",
            "note": "Saves the caller context while retaining the recipe.",
            "bidirectional": false
          },
          {
            "from": "ap0",
            "to": "code",
            "type": "control",
            "source": "gap-lispkit-manual",
            "locator": "printed pp. 108–109",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "code",
            "to": "value",
            "type": "association",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 109",
            "note": "Evaluation yields a value.",
            "bidirectional": false
          },
          {
            "from": "value",
            "to": "upd",
            "type": "data",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 109",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "d",
            "to": "upd",
            "type": "data",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 109",
            "note": "",
            "bidirectional": false
          },
          {
            "from": "upd",
            "to": "recipe",
            "type": "control",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 109",
            "note": "Overwrites the recipe with its value.",
            "bidirectional": false
          },
          {
            "from": "upd",
            "to": "resume",
            "type": "control",
            "source": "gap-lispkit-manual",
            "locator": "printed p. 109",
            "note": "",
            "bidirectional": false
          }
        ]
      },
      "originalCandidate": null
    }
  ],
  "reading": [
    {
      "source": "bennett-paper",
      "paradigm": "reversible"
    },
    {
      "source": "kung-paper",
      "architecture": "systolic"
    }
  ],
  "sweep": {
    "originalCandidates": 182,
    "resolved": 182,
    "remaining": 0,
    "ledger": [
      {
        "candidateId": "queue-001",
        "originalName": "Babbage Analytical Engine (design)",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-001",
        "disposition": "proposal",
        "rationale": "Resolved to the contemporary 1843 published design; construction is not inferred.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-002",
        "originalName": "Zuse Z3",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-002",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-003",
        "originalName": "Zuse Z4",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-003",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-004",
        "originalName": "Harvard Mark I",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-004",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-005",
        "originalName": "Atanasoff–Berry Computer",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-005",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-006",
        "originalName": "Colossus Mark II",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-006",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-007",
        "originalName": "Manchester Baby",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-007",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-008",
        "originalName": "Manchester Mark 1",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-008",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-009",
        "originalName": "EDSAC",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-009",
        "disposition": "representative-configuration",
        "rationale": "Separates full-store programming organization from the incompletely commissioned May 1949 machine.",
        "familyCoverage": "One EDSAC I programming configuration; excludes EDSAC 2 and later simulator conveniences."
      },
      {
        "candidateId": "queue-010",
        "originalName": "EDVAC",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-010",
        "disposition": "representative-configuration",
        "rationale": "Uses an operational installation survey, rather than conflating the constructed EDVAC with the 1945 First Draft.",
        "familyCoverage": "Upgraded BRL machine as surveyed in 1961 only."
      },
      {
        "candidateId": "queue-011",
        "originalName": "IAS computer",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-011",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-012",
        "originalName": "UNIVAC I",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-012",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-013",
        "originalName": "Ferranti Mark 1",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-013",
        "disposition": "representative-configuration",
        "rationale": "Pins the name to the eight-CRT organization explicitly stated by the designers.",
        "familyCoverage": "Early Ferranti Mark 1 configuration; excludes Mark 1 Star."
      },
      {
        "candidateId": "queue-014",
        "originalName": "Whirlwind I",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-014",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-015",
        "originalName": "IBM 701",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-015",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-016",
        "originalName": "IBM 650",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-016",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-017",
        "originalName": "BESM-6",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-017",
        "disposition": "representative-configuration",
        "rationale": "Separates the original architecture from later storage upgrades mentioned in the same source.",
        "familyCoverage": "Core architecture only; no single installation’s peripheral inventory claimed."
      },
      {
        "candidateId": "queue-018",
        "originalName": "MESM",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-018",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-019",
        "originalName": "Setun",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-019",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-020",
        "originalName": "MIR-2",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-020",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-021",
        "originalName": "CSIRAC",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-021",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-022",
        "originalName": "ZEBRA",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-022",
        "disposition": "representative-configuration",
        "rationale": "Pins the candidate to STC’s explicit basic configuration and separates optional extensions.",
        "familyCoverage": "Basic Stantec ZEBRA as documented in 1961."
      },
      {
        "candidateId": "queue-023",
        "originalName": "LGP-30",
        "track": "early",
        "trackName": "Early digital & mechanical",
        "status": "dossier",
        "systemId": "queue-023",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-024",
        "originalName": "IBM 7030 Stretch",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-024",
        "disposition": "representative-configuration",
        "rationale": "Uses the modular system in the designers’ monograph, with optional disk explicitly labelled.",
        "familyCoverage": "7030 architecture, not HARVEST or a particular customer installation."
      },
      {
        "candidateId": "queue-025",
        "originalName": "IBM 7090",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-025",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-026",
        "originalName": "IBM System/360 Model 30",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-026",
        "disposition": "representative-configuration",
        "rationale": "Selects the C30 main-storage size explicitly listed by IBM; optional units remain labelled.",
        "familyCoverage": "One Model 30 size; excludes other System/360 implementations."
      },
      {
        "candidateId": "queue-027",
        "originalName": "IBM System/360 Model 67",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-027",
        "disposition": "representative-configuration",
        "rationale": "Explicitly selects the 67-1 and standard translation width from the manual’s multiple variants.",
        "familyCoverage": "Single-processor virtual-memory variant only."
      },
      {
        "candidateId": "queue-028",
        "originalName": "IBM System/360 Model 91",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-028",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-029",
        "originalName": "IBM System/370",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-029",
        "disposition": "representative-configuration",
        "rationale": "Resolves the System/370 family to one named CPU/storage/cache configuration in the manufacturer manual.",
        "familyCoverage": "One Model 168-1; other System/370 models are not covered by substitution."
      },
      {
        "candidateId": "queue-030",
        "originalName": "IBM z16",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-030",
        "disposition": "representative-configuration",
        "rationale": "Resolves the z16 product family to the documented A01 CPC-drawer organization.",
        "familyCoverage": "A01 only; A02/AGZ are separate configurations."
      },
      {
        "candidateId": "queue-031",
        "originalName": "ICL 1900 series",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-031",
        "disposition": "representative-configuration",
        "rationale": "Resolves a heterogeneous family to one named 1904A processor/storage configuration.",
        "familyCoverage": "1904A 2044/1 only; other 1900 implementations differ internally."
      },
      {
        "candidateId": "queue-032",
        "originalName": "Burroughs B5000",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-032",
        "disposition": "representative-configuration",
        "rationale": "Selects Processor A’s documented organization without implying a second processor or maximum memory.",
        "familyCoverage": "Original B5000 processor organization only."
      },
      {
        "candidateId": "queue-033",
        "originalName": "Burroughs B6500",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-033",
        "disposition": "representative-configuration",
        "rationale": "Selects B6503 processor semantics and preserves variable system expansion.",
        "familyCoverage": "B6500 as specified in 1969, not the later B6700 manual."
      },
      {
        "candidateId": "queue-034",
        "originalName": "English Electric KDF9",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-034",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-035",
        "originalName": "GE-645 / Multics",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-035",
        "disposition": "representative-configuration",
        "rationale": "Selects the initial MIT operating installation; separates manufacturer plans from demonstrated service.",
        "familyCoverage": "GE-645-era Multics only, before the Honeywell 6180 upgrade."
      },
      {
        "candidateId": "queue-036",
        "originalName": "Tandem NonStop",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-036",
        "disposition": "representative-configuration",
        "rationale": "Selects a two-processor slice of the original Tandem 16 design instead of merging later NonStop generations.",
        "familyCoverage": "Original Tandem 16 hardware; 1981 kernel source is explicitly supplemental."
      },
      {
        "candidateId": "queue-037",
        "originalName": "Stratus fault-tolerant systems",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-037",
        "disposition": "representative-configuration",
        "rationale": "Resolves an unspecified Stratus family to a documented V2404 configuration.",
        "familyCoverage": "V2404 only; original FT-series and later models require separate records."
      },
      {
        "candidateId": "queue-038",
        "originalName": "Elbrus-1",
        "track": "mainframe",
        "trackName": "Mainframes & fault tolerance",
        "status": "dossier",
        "systemId": "queue-038",
        "disposition": "representative-configuration",
        "rationale": "Restricts a first-generation candidate to architectural roles supported by institutional and designer evidence.",
        "familyCoverage": "Elbrus-1 only; excludes Elbrus-2 performance and all later VLIW Elbrus machines."
      },
      {
        "candidateId": "queue-039",
        "originalName": "DEC PDP-1",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-039",
        "disposition": "representative-configuration",
        "rationale": "Uses a dated manufacturer configuration rather than conflating early and later PDP-1 equipment.",
        "familyCoverage": "October 1963 handbook standard equipment and explicitly marked options only."
      },
      {
        "candidateId": "queue-040",
        "originalName": "DEC PDP-8",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-040",
        "disposition": "representative-configuration",
        "rationale": "Restricts the PDP-8 family candidate to the original parallel machine documented in 1966.",
        "familyCoverage": "Original PDP-8 only; later family processors need separate configurations."
      },
      {
        "candidateId": "queue-041",
        "originalName": "DEC PDP-10 / KA10",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-041",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-042",
        "originalName": "DEC PDP-11/45",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-042",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-043",
        "originalName": "DEC PDP-11/70",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-043",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-044",
        "originalName": "DEC VAX-11/780",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-044",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-045",
        "originalName": "Data General Nova",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-045",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-046",
        "originalName": "HP 3000",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-046",
        "disposition": "representative-configuration",
        "rationale": "Resolves the broad HP 3000 family to the standard Series II Model 9 package described by its designers.",
        "familyCoverage": "1976 Series II Model 9 only; excludes original 1972 implementation and later PA-RISC HP 3000."
      },
      {
        "candidateId": "queue-047",
        "originalName": "Apollo Guidance Computer Block II",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-047",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-048",
        "originalName": "IBM PC 5150",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-048",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-049",
        "originalName": "Apple II",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-049",
        "disposition": "representative-configuration",
        "rationale": "Chooses the original 1978 reference and a supported 48KB fit rather than merging the Apple II family.",
        "familyCoverage": "Original Apple II only; Plus, IIe, IIc, IIgs and later expansion cards excluded."
      },
      {
        "candidateId": "queue-050",
        "originalName": "Apple Macintosh 128K",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-050",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-051",
        "originalName": "Acorn Archimedes",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-051",
        "disposition": "representative-configuration",
        "rationale": "Resolves the Archimedes family to the original A440 board documented by its manufacturer.",
        "familyCoverage": "Original A440 only; not A440/1 or later ARM3/ARM250 models."
      },
      {
        "candidateId": "queue-052",
        "originalName": "Sun-1",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-052",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-053",
        "originalName": "Sun SPARCstation 1",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-053",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-054",
        "originalName": "SGI IRIS 4D",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-054",
        "disposition": "representative-configuration",
        "rationale": "Resolves a large workstation family to the designer-documented 1988 GT graphics implementation; host SKU remains explicitly open.",
        "familyCoverage": "GT graphics pipeline and documented host interface only; no coverage claim for all IRIS 4D systems."
      },
      {
        "candidateId": "queue-055",
        "originalName": "Symbolics 3600",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-055",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-056",
        "originalName": "LMI Lambda",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-056",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-057",
        "originalName": "Commodore Amiga 1000",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-057",
        "disposition": "exact-system",
        "rationale": "The cited record identifies this machine and its stated configuration.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-058",
        "originalName": "Nintendo Entertainment System",
        "track": "mini",
        "trackName": "Minicomputers, workstations & personal systems",
        "status": "dossier",
        "systemId": "queue-058",
        "disposition": "representative-configuration",
        "rationale": "Resolves the regional console family to the NTSC NES-001 service configuration.",
        "familyCoverage": "NTSC front-loader functional architecture only; cartridge variants and other regions need separate records."
      },
      {
        "candidateId": "queue-059",
        "originalName": "Ferranti Atlas",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-059",
        "rationale": "Manchester/MUSE baseline in the 1962 paper; Atlas 2 and later installations are separate.",
        "familyCoverage": "Manchester baseline only; no family-wide capacity claim."
      },
      {
        "candidateId": "queue-060",
        "originalName": "CDC 7600",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-060",
        "rationale": "The preliminary manual’s 64Kword SCM/512Kword LCM organization; production revisions and draft timing are outside scope.",
        "familyCoverage": "Preliminary manual organization only; later production revisions remain unclaimed."
      },
      {
        "candidateId": "queue-061",
        "originalName": "CDC STAR-100",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-061",
        "rationale": "Basic524288-word system with four I/O channels in60256000-09; optional memory/channel expansions are excluded.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-062",
        "originalName": "Cray X-MP",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-062",
        "rationale": "X-MP/24: two CPUs and four million64-bit words; optional SSD represented separately.",
        "familyCoverage": "X-MP/24 only; later X-MP CPU counts and address extensions are separate."
      },
      {
        "candidateId": "queue-063",
        "originalName": "Cray-2",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-063",
        "rationale": "HR-2000 four-background-processor configuration; later memory variants are excluded.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-064",
        "originalName": "Cray Y-MP",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-064",
        "rationale": "Model832: eight CPUs and32Mwords, as documented in HR-04001-0C; not a named installation.",
        "familyCoverage": "One documented Y-MP8 configuration; other Y-MP models remain distinct."
      },
      {
        "candidateId": "queue-065",
        "originalName": "Cray T3D",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-065",
        "rationale": "HR-04033 architecture with32–2048 PEs; graph depicts one node, without asserting a specific installed size.",
        "familyCoverage": "Original two-PE-node architecture; installation size is deliberately unspecified."
      },
      {
        "candidateId": "queue-066",
        "originalName": "Cray T3E",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-066",
        "rationale": "Initial Alpha21164 T3E architecture; node count is parameterized rather than assigned to a site.",
        "familyCoverage": "Initial21164 architecture only; later speed grades and installations are separate."
      },
      {
        "candidateId": "queue-067",
        "originalName": "NEC SX-2",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-067",
        "rationale": "NEC Fuchu SX-2 configuration characterized by LA-UR-87-227; later SX-2A excluded.",
        "familyCoverage": "The original SX-2 tested at Fuchu; no family-wide memory claims."
      },
      {
        "candidateId": "queue-068",
        "originalName": "NEC SX-Aurora TSUBASA",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-068",
        "rationale": "One Type10AE Vector Engine with eight cores and48GB; later10-core/16-core cards are excluded.",
        "familyCoverage": "Type10AE engine only; system host, engine count and network are deployment-specific."
      },
      {
        "candidateId": "queue-069",
        "originalName": "Fujitsu VP200",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-069",
        "rationale": "Numazu VP-200 with64MB; timing organization from ANL-85-19.",
        "familyCoverage": "The original VP-200 Numazu64MB machine; VP2000 and later VP-E models excluded."
      },
      {
        "candidateId": "queue-070",
        "originalName": "Hitachi S-810",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-070",
        "rationale": "Model20 reference organization; paper specifies capacities as options, not one installed machine.",
        "familyCoverage": "Model20 reference in1983 paper; not Model10 or later S-820."
      },
      {
        "candidateId": "queue-071",
        "originalName": "Earth Simulator",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-071",
        "rationale": "Original640-node ES1 installation; ES2 and subsequent Earth Simulators are distinct.",
        "familyCoverage": "ES1 original installation only; not a family-wide claim."
      },
      {
        "candidateId": "queue-072",
        "originalName": "K computer",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-072",
        "rationale": "RIKEN K computer at full operation; processor-node and two-level-storage organization in the official handout.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-073",
        "originalName": "ILLIAC IV",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-073",
        "rationale": "One64-PE quadrant with B6700 control computer in the1974 brochure.",
        "familyCoverage": "The1974 single-quadrant/B6700 documentation only."
      },
      {
        "candidateId": "queue-074",
        "originalName": "Thinking Machines CM-1",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-074",
        "rationale": "The dissertation’s65536-cell CM-1 prototype, described during construction.",
        "familyCoverage": "Dissertation prototype design; commercial revisions require separate manuals."
      },
      {
        "candidateId": "queue-075",
        "originalName": "Thinking Machines CM-2",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-075",
        "rationale": "65536 data processors with the documented floating-point option; precision option remains explicit.",
        "familyCoverage": "April1987 full64K reference with optional FP; no CM-200 details imported."
      },
      {
        "candidateId": "queue-076",
        "originalName": "Thinking Machines CM-5",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-076",
        "rationale": "Initial-release nodes in the1992 report;32–16384-node range is a product parameter, not one installation.",
        "familyCoverage": "Initial-release report configuration only; no later CM-5E upgrades."
      },
      {
        "candidateId": "queue-077",
        "originalName": "MasPar MP-1",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-077",
        "rationale": "16384 PEs with16KB/PE in the1990 paper; later64KB variants and MP-2 excluded.",
        "familyCoverage": "The16K-PE/16KB-per-PE design point in Nickolls1990 only."
      },
      {
        "candidateId": "queue-078",
        "originalName": "Goodyear MPP",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-078",
        "rationale": "128×128 logical PEs,1024 bits/PE; spare columns preserve the logical array.",
        "familyCoverage": "1980 reference design only; delivered-machine revisions require separate evidence."
      },
      {
        "candidateId": "queue-079",
        "originalName": "Intel iPSC",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-079",
        "rationale": "Original32-node d5; memory-board and later vector/iPSC860 variants excluded.",
        "familyCoverage": "Original d5 only; iPSC/2 and iPSC/860 are separate."
      },
      {
        "candidateId": "queue-080",
        "originalName": "Intel Paragon",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-080",
        "rationale": "Basic dual-i860XP node in the1991 overview; MP-node development and installation counts excluded.",
        "familyCoverage": "Basic1991 dual-processor node and scalable system roles; later MP nodes remain distinct."
      },
      {
        "candidateId": "queue-081",
        "originalName": "ASCI Red",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-081",
        "rationale": "Table2’s4536 compute nodes and200MHz Pentium Pro generation; later upgrades excluded.",
        "familyCoverage": "Pentium Pro system as documented in Q1,1998; no PentiumII OverDrive upgrade."
      },
      {
        "candidateId": "queue-082",
        "originalName": "IBM Blue Gene/L",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-082",
        "rationale": "65536-node/512MB-per-node design point in the2005 article; modes remain selectable.",
        "familyCoverage": "The2005 paper’s512MB node design point, not every installed BGL revision."
      },
      {
        "candidateId": "queue-083",
        "originalName": "IBM Blue Gene/Q",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-083",
        "rationale": "Standard16GB compute card and2012 system organization; installation/rack count unspecified.",
        "familyCoverage": "Standard16GB card and2012 rack architecture; no specific installation claimed."
      },
      {
        "candidateId": "queue-084",
        "originalName": "SGI Origin2000",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-084",
        "rationale": "Dual-R10000 node architecture in the1997 paper; no maximal installation asserted.",
        "familyCoverage": "1997 dual-R10000 node architecture; later CPU/memory upgrades are excluded."
      },
      {
        "candidateId": "queue-085",
        "originalName": "Sequent Symmetry",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-085",
        "rationale": "S2000/200 with80486 processor board,SSM/SSM-I/O and VME peripherals.",
        "familyCoverage": "S2000/200 in1991 only; classic80386 Symmetry and later NUMA-Q are excluded."
      },
      {
        "candidateId": "queue-086",
        "originalName": "Kendall Square KSR1",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-086",
        "rationale": "The report’s one-ring32-cell system running KSR OS R1.0.5.",
        "familyCoverage": "The32-cell OS R1.0.5 experiment only; no higher-ring capacity claim."
      },
      {
        "candidateId": "queue-087",
        "originalName": "DASH",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-087",
        "rationale": "Four-cluster16-processor prototype used by the article’s running OS; larger64-processor target not implied.",
        "familyCoverage": "The article’s four-cluster running prototype, not the larger architectural scaling envelope."
      },
      {
        "candidateId": "queue-088",
        "originalName": "Alewife",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-088",
        "rationale": "The32-node first-silicon machine measured in the1995 paper.",
        "familyCoverage": "First-silicon32-node paper configuration; intended clock and later respins are excluded."
      },
      {
        "candidateId": "queue-089",
        "originalName": "Beowulf cluster",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-089",
        "rationale": "Original16-node100MHz DX4 system; later Pentium/Fast Ethernet generation excluded.",
        "familyCoverage": "Original DX4 prototype only; the broader Beowulf class remains configuration-dependent."
      },
      {
        "candidateId": "queue-090",
        "originalName": "Summit",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-090",
        "rationale": "Standard512GB DDR4/96GB HBM2 node in the archived guide; high-memory nodes excluded.",
        "familyCoverage": "Standard AC922 node; later high-memory nodes are separate."
      },
      {
        "candidateId": "queue-091",
        "originalName": "Frontier",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-091",
        "rationale": "The guide’s64-core EPYC/four-MI250X node; launch and software revisions are not conflated.",
        "familyCoverage": "Operator-documented MI250X compute node only; ranks and changing software versions are not architectural constants."
      },
      {
        "candidateId": "queue-092",
        "originalName": "Aurora",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-092",
        "rationale": "Dual9470C/six1550 node in the February2025 machine overview.",
        "familyCoverage": "February2025 hardware overview; physical tile-unit totals deliberately not generalized."
      },
      {
        "candidateId": "queue-093",
        "originalName": "El Capitan",
        "track": "super",
        "trackName": "Vector & large parallel machines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-093",
        "rationale": "FourMI300A/512GiB compute node; queue counts and software revision are separate operational facts.",
        "familyCoverage": "The commissioned system’s four-MI300A compute-node building block."
      },
      {
        "candidateId": "queue-094",
        "originalName": "MIT Tagged-Token Dataflow Machine",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "model",
        "systemId": "queue-094",
        "rationale": "The1990 paper’s n-cube TTDA model; physical packaging and processor count are unspecified.",
        "familyCoverage": "The1990 TTDA model only; Monsoon is a separate dossier."
      },
      {
        "candidateId": "queue-095",
        "originalName": "Manchester Dataflow Machine",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-095",
        "rationale": "1985 documented ring with software-emulated overflow; future overflow hardware is excluded.",
        "familyCoverage": "The1985 prototype ring, not proposed later stores or multiprocessors."
      },
      {
        "candidateId": "queue-096",
        "originalName": "Monsoon",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-096",
        "rationale": "The operational single-PE prototype in §4, hosted by a TI Explorer through NuBus; multiprocessor plans are excluded.",
        "familyCoverage": "The1988 operational single-PE prototype as measured in1990; later multiprocessors are distinct."
      },
      {
        "candidateId": "queue-097",
        "originalName": "TRIPS",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-097",
        "rationale": "Two16-wide cores and1MB configurable NUCA in the2006 prototype paper.",
        "familyCoverage": "The2006 two-core prototype only; later EDGE variants are excluded."
      },
      {
        "candidateId": "queue-098",
        "originalName": "WaveScalar",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "proposal",
        "systemId": "queue-098",
        "rationale": "Original2003 WaveCache proposal: roughly2K PEs in16-PE clusters, eight instruction slots/PE.",
        "familyCoverage": "The2003 WaveCache proposal and simulations only; later revisions are excluded."
      },
      {
        "candidateId": "queue-099",
        "originalName": "INMOS Transputer T800 systems",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-099",
        "rationale": "B401-3 module: T800-20,4KB internal RAM and32KB external SRAM; unspecified motherboard wiring is excluded.",
        "familyCoverage": "One B401-3 T800 node; other TRAMs, motherboards and link networks require separate records."
      },
      {
        "candidateId": "queue-100",
        "originalName": "iWarp",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-100",
        "rationale": "The1990 iWarp cell and pathway mechanisms; the paper’s planned8×8 torus is not claimed as delivered.",
        "familyCoverage": "The original cell architecture only; no family-wide system size or topology."
      },
      {
        "candidateId": "queue-101",
        "originalName": "RAW machine",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-101",
        "rationale": "Single16-tile Raw chip with SDRAM, I/O and interface FPGAs in the2004 prototype motherboard.",
        "familyCoverage": "The16-tile Raw prototype and motherboard only; the larger proposed64-chip system is excluded."
      },
      {
        "candidateId": "queue-102",
        "originalName": "MIT Eyeriss",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-102",
        "rationale": "The original168-PE Eyeriss chip; Eyerissv2 is distinct.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-103",
        "originalName": "Google TPU v1",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-103",
        "rationale": "The first-generation TPU disclosed at ISCA2017; not a training TPU or later pod.",
        "familyCoverage": "This exact configuration only."
      },
      {
        "candidateId": "queue-104",
        "originalName": "Google TPU v4 pod",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-104",
        "rationale": "The4096-chip,64-rack TPUv4 system in the2023 paper; optical communication does not make its arithmetic photonic.",
        "familyCoverage": "4096-chip paper configuration; later TPU generations excluded."
      },
      {
        "candidateId": "queue-105",
        "originalName": "NVIDIA DGX-1",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-105",
        "rationale": "V10016GB edition, eight GPUs/512GB host RAM; P100 and32GB variants excluded.",
        "familyCoverage": "The16GB Volta configuration only; no Pascal or32GB capacity mixing."
      },
      {
        "candidateId": "queue-106",
        "originalName": "NVIDIA DGX H100",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-106",
        "rationale": "H100640GB model in October2026 manual; H200 is excluded.",
        "familyCoverage": "H100640GB server configuration in this manual edition; H200 and B200 are separate."
      },
      {
        "candidateId": "queue-107",
        "originalName": "NVIDIA GB200 NVL72",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-107",
        "rationale": "DGX GB20072×1 rack:36 Grace CPUs,72 B200 GPUs, nine two-chip switch trays.",
        "familyCoverage": "DGX GB20072×1 reference rack only; no claim over all OEM systems or GB300."
      },
      {
        "candidateId": "queue-108",
        "originalName": "Cerebras CS-2",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-108",
        "rationale": "WSE-2/CS-2 weight-streaming organization described in2023; WSE-3 is excluded.",
        "familyCoverage": "WSE-2 with external weight streaming; later wafers and cluster sizes are excluded."
      },
      {
        "candidateId": "queue-109",
        "originalName": "Graphcore IPU systems",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-109",
        "rationale": "One M2000 with default2×64GB DDR4, external Poplar host and RoCEv2 link; Bow variants excluded.",
        "familyCoverage": "One2020 GC200 M2000 default configuration; Mk1/Bow and larger PODs are not collapsed into it."
      },
      {
        "candidateId": "queue-110",
        "originalName": "Groq TSP systems",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-110",
        "rationale": "2020 first-generation ASIC; later multi-TSP systems excluded.",
        "familyCoverage": "The2020 single-chip PCIe implementation only."
      },
      {
        "candidateId": "queue-111",
        "originalName": "Anton2",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-111",
        "rationale": "512-node machine reported operational in2014.",
        "familyCoverage": "The512-node2014 machine only."
      },
      {
        "candidateId": "queue-112",
        "originalName": "GRAPE-6",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-112",
        "rationale": "Four clusters,16 boards/cluster,32 chips/board.",
        "familyCoverage": "The2003 four-cluster system; early proposals and GRAPE-6A excluded."
      },
      {
        "candidateId": "queue-113",
        "originalName": "Ambric AM2045",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-113",
        "rationale": "Production336-processor Am2045 described at HPEC2008.",
        "familyCoverage": "Production2008 device; no assumption that every partial bric contains eight enabled CPUs."
      },
      {
        "candidateId": "queue-114",
        "originalName": "DIMA / compute-in-memory prototypes",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-114",
        "rationale": "One measured512×256-bit6T SRAM array in65nm CMOS.",
        "familyCoverage": "The2016 UIUC measured multifunctional SRAM IC; DIMA is treated as a lineage, not one universal product."
      },
      {
        "candidateId": "queue-115",
        "originalName": "UPMEM",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-115",
        "rationale": "P21:20 DIMMs,2556 usable DPUs, dual Xeon Silver4215.",
        "familyCoverage": "The measured P21 server in paper revisionv7; not the nominal2560-DPU maximum or E19 system."
      },
      {
        "candidateId": "queue-116",
        "originalName": "Mythic M1076",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-116",
        "rationale": "M1076 chip or one-chip M.2 card; M1108/M1 excluded.",
        "familyCoverage": "M1076 only; no inheritance of2018 prototype conversion choices or2026 M1 capabilities."
      },
      {
        "candidateId": "queue-117",
        "originalName": "Samsung HBM-PIM",
        "track": "special",
        "trackName": "Spatial, dataflow & specialized engines",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-117",
        "rationale": "U280-PIM board with two Aquabolt-XL stacks and12GB memory.",
        "familyCoverage": "Aquabolt-XL on U280 only; MI50/MI100 and LPDDR/AXDIMM variants remain separate."
      },
      {
        "candidateId": "queue-118",
        "originalName": "Rockefeller Differential Analyzer",
        "track": "analog",
        "trackName": "Analog, hybrid & physical dynamics",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-118",
        "rationale": "Kopal’s published setup on the Rockefeller analyzer, using nine of its 18 integrators; the date identifies this application, not machine completion.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-119",
        "originalName": "EAI 231R",
        "track": "analog",
        "trackName": "Analog, hybrid & physical dynamics",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-119",
        "rationale": "231R-V system described in the 1964 manual; complement varies with expansion and accessories.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-120",
        "originalName": "EAI 680",
        "track": "analog",
        "trackName": "Analog, hybrid & physical dynamics",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-120",
        "rationale": "Standard 680 reference architecture, up to 30 combination integrator/summers when fully expanded; not a particular attached digital host.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-121",
        "originalName": "Heathkit EC-1",
        "track": "analog",
        "trackName": "Analog, hybrid & physical dynamics",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-121",
        "rationale": "EC-1 manual’s damped spring–mass example, Fig. 30; nine DC amplifiers are available, with only the illustrated subset used here.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-122",
        "originalName": "PACE analog computer",
        "track": "analog",
        "trackName": "Analog, hybrid & physical dynamics",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-122",
        "rationale": "Basic TR-10 linear differential-equation example on brochure p. 6; nonlinear plug-in complements vary.",
        "familyCoverage": "PACE is a product-family name; this resolves it to TR-10, separately from 231R-V and HYDAC."
      },
      {
        "candidateId": "queue-123",
        "originalName": "HYDAC 2400 hybrid computer",
        "track": "analog",
        "trackName": "Analog, hybrid & physical dynamics",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-123",
        "rationale": "231R-V analog section + DOS 350 parallel digital operations + EAI 375 (3C DDP-24) sequential digital computer, as specified in the seminar.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-124",
        "originalName": "MONIAC",
        "track": "analog",
        "trackName": "Analog, hybrid & physical dynamics",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-124",
        "rationale": "National-income/savings/investment model of Fig. 3 in Phillips (1950), not every later MONIAC arrangement.",
        "familyCoverage": "The closed-economy national-income configuration in Fig. 3; later tax/foreign-sector MONIAC variants differ."
      },
      {
        "candidateId": "queue-125",
        "originalName": "Lukyanov water integrator",
        "track": "analog",
        "trackName": "Analog, hybrid & physical dynamics",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-125",
        "rationale": "One-dimensional 1-IGL-1-3 named in the museum illustration; diagram shows the account’s documented method, not a complete specimen piping plan.",
        "familyCoverage": "Named one-dimensional museum specimen and documented operating principle; original designer manual not obtained."
      },
      {
        "candidateId": "queue-126",
        "originalName": "FPAA analog computing systems",
        "track": "analog",
        "trackName": "Analog, hybrid & physical dynamics",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-126",
        "rationale": "AN231E04 architecture in datasheet rev. 1.5; the date identifies this documentation revision, not original device introduction.",
        "familyCoverage": "AN231E04 device architecture; other floating-gate and continuous-time FPAAs are distinct."
      },
      {
        "candidateId": "queue-127",
        "originalName": "Coupled-oscillator Ising prototypes",
        "track": "analog",
        "trackName": "Analog, hybrid & physical dynamics",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-127",
        "rationale": "32-node perfboard prototype, Chimera-like connectivity, rotary coupling potentiometers and sign-selecting jumpers.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-128",
        "originalName": "Acoustic reservoir experiments",
        "track": "analog",
        "trackName": "Analog, hybrid & physical dynamics",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-128",
        "rationale": "GaAs/AlAs waveguide capped by patterned FeGa; visual shapes drawn by a write laser are classified using a PC ANN.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-129",
        "originalName": "Reaction–diffusion processors",
        "track": "analog",
        "trackName": "Analog, hybrid & physical dynamics",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-129",
        "rationale": "Experimentally demonstrated OR(x,y,z) gate in Fig. 1, using printed bathoferroin membrane on BZ-containing agarose.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-130",
        "originalName": "IBM TrueNorth",
        "track": "neural",
        "trackName": "Neuromorphic & reservoirs",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-130",
        "rationale": "The 4,096-core TrueNorth chip in Merolla et al. (2014), not a later multi-board system.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-131",
        "originalName": "IBM NorthPole",
        "track": "neural",
        "trackName": "Neuromorphic & reservoirs",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-131",
        "rationale": "The 256-core 12 nm prototype described by IBM in 2023; not a training accelerator.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-132",
        "originalName": "SpiNNaker",
        "track": "neural",
        "trackName": "Neuromorphic & reservoirs",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-132",
        "rationale": "First-generation 18-core SpiNNaker chip and sPyNNaker execution model described in 2018; full machine size is configuration-specific.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-133",
        "originalName": "SpiNNaker2",
        "track": "neural",
        "trackName": "Neuromorphic & reservoirs",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-133",
        "rationale": "152-PE chip in Scholze et al. v1 (2026); usable application PE counts depend on firmware reservations.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-134",
        "originalName": "BrainScaleS-1",
        "track": "neural",
        "trackName": "Neuromorphic & reservoirs",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-134",
        "rationale": "The BrainScaleS wafer module and hardware-in-the-loop experiment in Schmitt et al. (2017).",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-135",
        "originalName": "BrainScaleS-2",
        "track": "neural",
        "trackName": "Neuromorphic & reservoirs",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-135",
        "rationale": "Single-core BrainScaleS-2 architecture commissioned and described by Pehle et al. (2022).",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-136",
        "originalName": "Neurogrid",
        "track": "neural",
        "trackName": "Neuromorphic & reservoirs",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-136",
        "rationale": "Sixteen-Neurocore board described in Benjamin et al. (2014); neuron capacity and connection counts are model-dependent.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-137",
        "originalName": "DYNAP-SE",
        "track": "neural",
        "trackName": "Neuromorphic & reservoirs",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-137",
        "rationale": "The four-core DYNAPs prototype in Moradi et al. (2017), the architecture underlying first-generation DYNAP-SE; not DYNAP-SE2.",
        "familyCoverage": "First-generation four-core architecture only; board variants and SE2 are excluded."
      },
      {
        "candidateId": "queue-138",
        "originalName": "Tianjic",
        "track": "neural",
        "trackName": "Neuromorphic & reservoirs",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-138",
        "rationale": "Tianjic FCore/chip in Pei et al. (2019); hybrid here means ANN/SNN operation, not analog electronics.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-139",
        "originalName": "Intel Pohoiki Springs",
        "track": "neural",
        "trackName": "Neuromorphic & reservoirs",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-139",
        "rationale": "Fully configured five-rack-unit chassis in the 2020 nearest-neighbor-search paper; first-generation Loihi, not Loihi 2.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-140",
        "originalName": "Memristive neural crossbar experiments",
        "track": "neural",
        "trackName": "Neuromorphic & reservoirs",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-140",
        "rationale": "10-input, 3-output perceptron using a 10×6 crossbar fragment and 60 memristors in Prezioso et al.",
        "familyCoverage": "Representative metal-oxide crossbar experiment; not every memristive neural architecture."
      },
      {
        "candidateId": "queue-141",
        "originalName": "Delay-based photonic reservoir experiments",
        "track": "neural",
        "trackName": "Neuromorphic & reservoirs",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-141",
        "rationale": "Paquot et al. experimental loop; output is digitized and reconstructed offline, not an all-optical trained readout.",
        "familyCoverage": "One optoelectronic delay reservoir; not the full family of optical reservoirs."
      },
      {
        "candidateId": "queue-142",
        "originalName": "IBM Quantum System One",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-142",
        "rationale": "2019 System One and its 20-qubit processor used by Wei et al.; later System One installations have different processors.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-143",
        "originalName": "Google Sycamore",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-143",
        "rationale": "The 54-qubit design with one inoperable qubit; the reported sampling experiments used 53 qubits.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-144",
        "originalName": "Google Willow",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-144",
        "rationale": "105-qubit processor: distance-7 memory using 49 data, 48 measure and four boundary leakage-removal qubits; not the separate 72-qubit real-time-decoding experiment.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-145",
        "originalName": "Rigetti Aspen-M",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-145",
        "rationale": "Aspen-M-1 deployed 15 February 2022, not the later M-2/M-3 or Ankaa processors.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-146",
        "originalName": "IonQ Forte",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-146",
        "rationale": "35-ion chain, central 31 computational qubits, 32 detection channels, as described in the initial Forte report.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-147",
        "originalName": "Quantinuum H2",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-147",
        "rationale": "Original 32-qubit H2 with 32 Yb–Ba pairs; DG01–DG04 perform gates, preparation and measurement. Upper zones support rearrangement.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-148",
        "originalName": "Quantinuum H1",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-148",
        "rationale": "H1-1 after the June 2022 upgrade: 20 computational qubits and five simultaneously addressed gate zones.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-149",
        "originalName": "Atom Computing neutral-atom systems",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-149",
        "rationale": "21-qubit 7 × 3 computational subarray inside 110 optical tweezer sites; no entangling-gate network is claimed by this paper.",
        "familyCoverage": "Phoenix register experiment only; later Atom Computing arrays are separate configurations."
      },
      {
        "candidateId": "queue-150",
        "originalName": "QuEra Aquila",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-150",
        "rationale": "Aquila public analog-mode configuration documented in white paper v1.0, supporting up to 256 atoms.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-151",
        "originalName": "Pasqal neutral-atom simulators",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-151",
        "rationale": "Orion Alpha (formerly Fresnel), up to 100 cloud-accessible qubits; 2D layouts and 6 µs maximum sequence in the cited brochure.",
        "familyCoverage": "Orion Alpha configuration in the 2025 brochure; later Orion Beta and other Pasqal machines are separate."
      },
      {
        "candidateId": "queue-152",
        "originalName": "D-Wave 2000Q",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-152",
        "rationale": "The lower-noise 2000Q used in the 2021 report’s 3D-lattice study; footnote 3 reports 2,041 operable qubits. Other study embeddings use different subgraphs.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-153",
        "originalName": "D-Wave Advantage",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-153",
        "rationale": "Advantage 4.1 in the October 2021 report; its 3D-lattice study reports 5,627 operable qubits. This is not Advantage2.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-154",
        "originalName": "Xanadu Borealis",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-154",
        "rationale": "216-mode Gaussian boson sampling experiment in Madsen et al.; not a universal fault-tolerant quantum computer.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-155",
        "originalName": "USTC Jiuzhang",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-155",
        "rationale": "Original 2020 100-mode experiment: 25 two-mode sources equivalent to 50 squeezed inputs, with 100 single-photon detectors.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-156",
        "originalName": "USTC Zuchongzhi",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-156",
        "rationale": "Original 66-qubit, 110-coupler processor; random circuits used a selected 56-qubit subset and up to 20 cycles.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-157",
        "originalName": "Silicon spin-qubit arrays",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-157",
        "rationale": "Six computational spins in a linear 28Si/SiGe quantum-dot array; middle-spin readout is mapped to outer neighbors.",
        "familyCoverage": "This six-spin linear-array experiment; other silicon spin and donor platforms require separate records."
      },
      {
        "candidateId": "queue-158",
        "originalName": "Topological quantum proposals",
        "track": "quantum",
        "trackName": "Quantum systems & simulation",
        "status": "dossier",
        "disposition": "proposal",
        "systemId": "queue-158",
        "rationale": "Kitaev’s local-Hamiltonian construction, with nonabelian models considered for universal computation; a formal proposal, not built apparatus.",
        "familyCoverage": "Kitaev’s lattice/anyon models; not a claim that a present commercial topological qubit has been demonstrated."
      },
      {
        "candidateId": "queue-159",
        "originalName": "LightOn optical processing unit",
        "track": "light",
        "trackName": "Photonic processors",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-159",
        "rationale": "LightOn Appliance described in the July 2021 paper; fixed optical matrix, not an arbitrary programmable weight matrix.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-160",
        "originalName": "Lightmatter Envise",
        "track": "light",
        "trackName": "Photonic processors",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-160",
        "rationale": "The 4U, 16-chip blade described in Lightmatter’s 2021 announcement. Internal datapath details are not publicly specified by this source.",
        "familyCoverage": "Published 2021 blade configuration; no assertion of current availability or shipped configuration."
      },
      {
        "candidateId": "queue-161",
        "originalName": "Lightelligence PACE",
        "track": "light",
        "trackName": "Photonic processors",
        "status": "dossier",
        "disposition": "exact-system",
        "systemId": "queue-161",
        "rationale": "The 64×64 PACE SiP and board in Hua et al. (2025); PCIe-card-sized form factor communicates through Ethernet/SOM/SPI, not an inferred PCIe data interface.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-162",
        "originalName": "Photonic tensor-core experiments",
        "track": "light",
        "trackName": "Photonic processors",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-162",
        "rationale": "Integrated tensor-core experiments in Feldmann et al.; array sizes and demonstrated convolution cases are explicitly experiment-dependent.",
        "familyCoverage": "Representative phase-change photonic tensor core; not every photonic tensor architecture."
      },
      {
        "candidateId": "queue-163",
        "originalName": "Coherent Ising machines",
        "track": "light",
        "trackName": "Photonic processors",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-163",
        "rationale": "Measurement-feedback CIM in the NTT report corresponding to the 2016 2,000-node optimization experiments.",
        "familyCoverage": "Representative NTT 2,048-node measurement-feedback CIM; delay-coupled variants are distinct."
      },
      {
        "candidateId": "queue-164",
        "originalName": "Programmable MZI mesh processors",
        "track": "light",
        "trackName": "Photonic processors",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-164",
        "rationale": "The six-mode silica-on-silicon LPU in Carolan et al. (2015), with photon sources and detection as external system components.",
        "familyCoverage": "One six-mode universal interferometer; later rectangular and larger meshes are outside scope."
      },
      {
        "candidateId": "queue-165",
        "originalName": "Shapiro DNA automaton",
        "track": "molecular",
        "trackName": "Molecular, cellular & chemical",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-165",
        "rationale": "Original FokI-and-ligase two-state, two-symbol automaton; even-ones program is one experimentally tested configuration.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-166",
        "originalName": "DNA strand-displacement circuits",
        "track": "molecular",
        "trackName": "Molecular, cellular & chemical",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-166",
        "rationale": "Fig. 4 four-bit integer square root: 130 strands interacting in one tube, with all sixteen input combinations tested.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-167",
        "originalName": "DNA tile self-assembly computers",
        "track": "molecular",
        "trackName": "Molecular, cellular & chemical",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-167",
        "rationale": "DAE-E implementation in Figs. 4A and 5; bulk annealing and AFM inspection of imperfect crystals.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-168",
        "originalName": "Cello genetic circuits",
        "track": "molecular",
        "trackName": "Molecular, cellular & chemical",
        "status": "dossier",
        "disposition": "representative-configuration",
        "systemId": "queue-168",
        "rationale": "Original Eco1C1G1T1 UCF, E. coli NEB 10-beta and two-plasmid specification; Priority Detector is the named example.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-169",
        "originalName": "Bacterial logic-gate experiments",
        "track": "molecular",
        "trackName": "Molecular, cellular & chemical",
        "status": "dossier",
        "disposition": "experiment",
        "systemId": "queue-169",
        "rationale": "Four-strain agar-plate XOR in Fig. 3: three NOR colonies and a final buffer colony.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-170",
        "originalName": "Chemical reaction-network computers",
        "track": "molecular",
        "trackName": "Molecular, cellular & chemical",
        "status": "dossier",
        "disposition": "proposal",
        "systemId": "queue-170",
        "rationale": "2010 construction; diagram expands the proposed X1 → X2 + X3 unimolecular module in Fig. 2.",
        "familyCoverage": "This exact configuration only; other revisions are not implied."
      },
      {
        "candidateId": "queue-171",
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